15614e71bSYork Sun /* 25614e71bSYork Sun * Copyright 2008-2012 Freescale Semiconductor, Inc. 35614e71bSYork Sun * 45614e71bSYork Sun * This program is free software; you can redistribute it and/or 55614e71bSYork Sun * modify it under the terms of the GNU General Public License 65614e71bSYork Sun * Version 2 as published by the Free Software Foundation. 75614e71bSYork Sun */ 85614e71bSYork Sun 95614e71bSYork Sun #include <common.h> 109ac4ffbdSYork Sun #ifdef CONFIG_PPC 115614e71bSYork Sun #include <asm/fsl_law.h> 129ac4ffbdSYork Sun #endif 135614e71bSYork Sun #include <div64.h> 145614e71bSYork Sun 155614e71bSYork Sun #include <fsl_ddr.h> 169a17eb5bSYork Sun #include <fsl_immap.h> 175614e71bSYork Sun #include <asm/io.h> 185614e71bSYork Sun 195614e71bSYork Sun /* To avoid 64-bit full-divides, we factor this here */ 205614e71bSYork Sun #define ULL_2E12 2000000000000ULL 215614e71bSYork Sun #define UL_5POW12 244140625UL 225614e71bSYork Sun #define UL_2POW13 (1UL << 13) 235614e71bSYork Sun 245614e71bSYork Sun #define ULL_8FS 0xFFFFFFFFULL 255614e71bSYork Sun 265614e71bSYork Sun /* 275614e71bSYork Sun * Round up mclk_ps to nearest 1 ps in memory controller code 285614e71bSYork Sun * if the error is 0.5ps or more. 295614e71bSYork Sun * 305614e71bSYork Sun * If an imprecise data rate is too high due to rounding error 315614e71bSYork Sun * propagation, compute a suitably rounded mclk_ps to compute 325614e71bSYork Sun * a working memory controller configuration. 335614e71bSYork Sun */ 345614e71bSYork Sun unsigned int get_memory_clk_period_ps(void) 355614e71bSYork Sun { 365614e71bSYork Sun unsigned int data_rate = get_ddr_freq(0); 375614e71bSYork Sun unsigned int result; 385614e71bSYork Sun 395614e71bSYork Sun /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ 405614e71bSYork Sun unsigned long long rem, mclk_ps = ULL_2E12; 415614e71bSYork Sun 425614e71bSYork Sun /* Now perform the big divide, the result fits in 32-bits */ 435614e71bSYork Sun rem = do_div(mclk_ps, data_rate); 445614e71bSYork Sun result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; 455614e71bSYork Sun 465614e71bSYork Sun return result; 475614e71bSYork Sun } 485614e71bSYork Sun 495614e71bSYork Sun /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ 505614e71bSYork Sun unsigned int picos_to_mclk(unsigned int picos) 515614e71bSYork Sun { 525614e71bSYork Sun unsigned long long clks, clks_rem; 535614e71bSYork Sun unsigned long data_rate = get_ddr_freq(0); 545614e71bSYork Sun 555614e71bSYork Sun /* Short circuit for zero picos */ 565614e71bSYork Sun if (!picos) 575614e71bSYork Sun return 0; 585614e71bSYork Sun 595614e71bSYork Sun /* First multiply the time by the data rate (32x32 => 64) */ 605614e71bSYork Sun clks = picos * (unsigned long long)data_rate; 615614e71bSYork Sun /* 625614e71bSYork Sun * Now divide by 5^12 and track the 32-bit remainder, then divide 635614e71bSYork Sun * by 2*(2^12) using shifts (and updating the remainder). 645614e71bSYork Sun */ 655614e71bSYork Sun clks_rem = do_div(clks, UL_5POW12); 665614e71bSYork Sun clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; 675614e71bSYork Sun clks >>= 13; 685614e71bSYork Sun 695614e71bSYork Sun /* If we had a remainder greater than the 1ps error, then round up */ 705614e71bSYork Sun if (clks_rem > data_rate) 715614e71bSYork Sun clks++; 725614e71bSYork Sun 735614e71bSYork Sun /* Clamp to the maximum representable value */ 745614e71bSYork Sun if (clks > ULL_8FS) 755614e71bSYork Sun clks = ULL_8FS; 765614e71bSYork Sun return (unsigned int) clks; 775614e71bSYork Sun } 785614e71bSYork Sun 795614e71bSYork Sun unsigned int mclk_to_picos(unsigned int mclk) 805614e71bSYork Sun { 815614e71bSYork Sun return get_memory_clk_period_ps() * mclk; 825614e71bSYork Sun } 835614e71bSYork Sun 849ac4ffbdSYork Sun #ifdef CONFIG_PPC 855614e71bSYork Sun void 865614e71bSYork Sun __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 875614e71bSYork Sun unsigned int law_memctl, 885614e71bSYork Sun unsigned int ctrl_num) 895614e71bSYork Sun { 905614e71bSYork Sun unsigned long long base = memctl_common_params->base_address; 915614e71bSYork Sun unsigned long long size = memctl_common_params->total_mem; 925614e71bSYork Sun 935614e71bSYork Sun /* 945614e71bSYork Sun * If no DIMMs on this controller, do not proceed any further. 955614e71bSYork Sun */ 965614e71bSYork Sun if (!memctl_common_params->ndimms_present) { 975614e71bSYork Sun return; 985614e71bSYork Sun } 995614e71bSYork Sun 1005614e71bSYork Sun #if !defined(CONFIG_PHYS_64BIT) 1015614e71bSYork Sun if (base >= CONFIG_MAX_MEM_MAPPED) 1025614e71bSYork Sun return; 1035614e71bSYork Sun if ((base + size) >= CONFIG_MAX_MEM_MAPPED) 1045614e71bSYork Sun size = CONFIG_MAX_MEM_MAPPED - base; 1055614e71bSYork Sun #endif 1065614e71bSYork Sun if (set_ddr_laws(base, size, law_memctl) < 0) { 1075614e71bSYork Sun printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, 1085614e71bSYork Sun law_memctl); 1095614e71bSYork Sun return ; 1105614e71bSYork Sun } 1115614e71bSYork Sun debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", 1125614e71bSYork Sun base, size, law_memctl); 1135614e71bSYork Sun } 1145614e71bSYork Sun 1155614e71bSYork Sun __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void 1165614e71bSYork Sun fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 1175614e71bSYork Sun unsigned int memctl_interleaved, 1185614e71bSYork Sun unsigned int ctrl_num); 1199ac4ffbdSYork Sun #endif 1205614e71bSYork Sun 1215614e71bSYork Sun void fsl_ddr_set_intl3r(const unsigned int granule_size) 1225614e71bSYork Sun { 1235614e71bSYork Sun #ifdef CONFIG_E6500 1245614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1255614e71bSYork Sun *mcintl3r = 0x80000000 | (granule_size & 0x1f); 1265614e71bSYork Sun debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); 1275614e71bSYork Sun #endif 1285614e71bSYork Sun } 1295614e71bSYork Sun 1305614e71bSYork Sun u32 fsl_ddr_get_intl3r(void) 1315614e71bSYork Sun { 1325614e71bSYork Sun u32 val = 0; 1335614e71bSYork Sun #ifdef CONFIG_E6500 1345614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1355614e71bSYork Sun val = *mcintl3r; 1365614e71bSYork Sun #endif 1375614e71bSYork Sun return val; 1385614e71bSYork Sun } 1395614e71bSYork Sun 1405614e71bSYork Sun void board_add_ram_info(int use_default) 1415614e71bSYork Sun { 1429a17eb5bSYork Sun struct ccsr_ddr __iomem *ddr = 1439a17eb5bSYork Sun (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 1445614e71bSYork Sun 1455614e71bSYork Sun #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) 1465614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1475614e71bSYork Sun #endif 1485614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS > 1) 1494e5b1bd0SYork Sun uint32_t cs0_config = ddr_in32(&ddr->cs0_config); 1505614e71bSYork Sun #endif 1514e5b1bd0SYork Sun uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); 1525614e71bSYork Sun int cas_lat; 1535614e71bSYork Sun 1545614e71bSYork Sun #if CONFIG_NUM_DDR_CONTROLLERS >= 2 1555614e71bSYork Sun if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 1565614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; 1574e5b1bd0SYork Sun sdram_cfg = ddr_in32(&ddr->sdram_cfg); 1585614e71bSYork Sun } 1595614e71bSYork Sun #endif 1605614e71bSYork Sun #if CONFIG_NUM_DDR_CONTROLLERS >= 3 1615614e71bSYork Sun if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 1625614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; 1634e5b1bd0SYork Sun sdram_cfg = ddr_in32(&ddr->sdram_cfg); 1645614e71bSYork Sun } 1655614e71bSYork Sun #endif 1665614e71bSYork Sun puts(" (DDR"); 1675614e71bSYork Sun switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> 1685614e71bSYork Sun SDRAM_CFG_SDRAM_TYPE_SHIFT) { 1695614e71bSYork Sun case SDRAM_TYPE_DDR1: 1705614e71bSYork Sun puts("1"); 1715614e71bSYork Sun break; 1725614e71bSYork Sun case SDRAM_TYPE_DDR2: 1735614e71bSYork Sun puts("2"); 1745614e71bSYork Sun break; 1755614e71bSYork Sun case SDRAM_TYPE_DDR3: 1765614e71bSYork Sun puts("3"); 1775614e71bSYork Sun break; 1785614e71bSYork Sun default: 1795614e71bSYork Sun puts("?"); 1805614e71bSYork Sun break; 1815614e71bSYork Sun } 1825614e71bSYork Sun 1835614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_32_BE) 1845614e71bSYork Sun puts(", 32-bit"); 1855614e71bSYork Sun else if (sdram_cfg & SDRAM_CFG_16_BE) 1865614e71bSYork Sun puts(", 16-bit"); 1875614e71bSYork Sun else 1885614e71bSYork Sun puts(", 64-bit"); 1895614e71bSYork Sun 1905614e71bSYork Sun /* Calculate CAS latency based on timing cfg values */ 1914e5b1bd0SYork Sun cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; 1924e5b1bd0SYork Sun if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1) 1935614e71bSYork Sun cas_lat += (8 << 1); 1945614e71bSYork Sun printf(", CL=%d", cas_lat >> 1); 1955614e71bSYork Sun if (cas_lat & 0x1) 1965614e71bSYork Sun puts(".5"); 1975614e71bSYork Sun 1985614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_ECC_EN) 1995614e71bSYork Sun puts(", ECC on)"); 2005614e71bSYork Sun else 2015614e71bSYork Sun puts(", ECC off)"); 2025614e71bSYork Sun 2035614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS == 3) 2045614e71bSYork Sun #ifdef CONFIG_E6500 2055614e71bSYork Sun if (*mcintl3r & 0x80000000) { 2065614e71bSYork Sun puts("\n"); 2075614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 2085614e71bSYork Sun switch (*mcintl3r & 0x1f) { 2095614e71bSYork Sun case FSL_DDR_3WAY_1KB_INTERLEAVING: 2105614e71bSYork Sun puts("3-way 1KB"); 2115614e71bSYork Sun break; 2125614e71bSYork Sun case FSL_DDR_3WAY_4KB_INTERLEAVING: 2135614e71bSYork Sun puts("3-way 4KB"); 2145614e71bSYork Sun break; 2155614e71bSYork Sun case FSL_DDR_3WAY_8KB_INTERLEAVING: 2165614e71bSYork Sun puts("3-way 8KB"); 2175614e71bSYork Sun break; 2185614e71bSYork Sun default: 2195614e71bSYork Sun puts("3-way UNKNOWN"); 2205614e71bSYork Sun break; 2215614e71bSYork Sun } 2225614e71bSYork Sun } 2235614e71bSYork Sun #endif 2245614e71bSYork Sun #endif 2255614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 2265614e71bSYork Sun if (cs0_config & 0x20000000) { 2275614e71bSYork Sun puts("\n"); 2285614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 2295614e71bSYork Sun 2305614e71bSYork Sun switch ((cs0_config >> 24) & 0xf) { 231*6b1e1254SYork Sun case FSL_DDR_256B_INTERLEAVING: 232*6b1e1254SYork Sun puts("256B"); 233*6b1e1254SYork Sun break; 2345614e71bSYork Sun case FSL_DDR_CACHE_LINE_INTERLEAVING: 2355614e71bSYork Sun puts("cache line"); 2365614e71bSYork Sun break; 2375614e71bSYork Sun case FSL_DDR_PAGE_INTERLEAVING: 2385614e71bSYork Sun puts("page"); 2395614e71bSYork Sun break; 2405614e71bSYork Sun case FSL_DDR_BANK_INTERLEAVING: 2415614e71bSYork Sun puts("bank"); 2425614e71bSYork Sun break; 2435614e71bSYork Sun case FSL_DDR_SUPERBANK_INTERLEAVING: 2445614e71bSYork Sun puts("super-bank"); 2455614e71bSYork Sun break; 2465614e71bSYork Sun default: 2475614e71bSYork Sun puts("invalid"); 2485614e71bSYork Sun break; 2495614e71bSYork Sun } 2505614e71bSYork Sun } 2515614e71bSYork Sun #endif 2525614e71bSYork Sun 2535614e71bSYork Sun if ((sdram_cfg >> 8) & 0x7f) { 2545614e71bSYork Sun puts("\n"); 2555614e71bSYork Sun puts(" DDR Chip-Select Interleaving Mode: "); 2565614e71bSYork Sun switch(sdram_cfg >> 8 & 0x7f) { 2575614e71bSYork Sun case FSL_DDR_CS0_CS1_CS2_CS3: 2585614e71bSYork Sun puts("CS0+CS1+CS2+CS3"); 2595614e71bSYork Sun break; 2605614e71bSYork Sun case FSL_DDR_CS0_CS1: 2615614e71bSYork Sun puts("CS0+CS1"); 2625614e71bSYork Sun break; 2635614e71bSYork Sun case FSL_DDR_CS2_CS3: 2645614e71bSYork Sun puts("CS2+CS3"); 2655614e71bSYork Sun break; 2665614e71bSYork Sun case FSL_DDR_CS0_CS1_AND_CS2_CS3: 2675614e71bSYork Sun puts("CS0+CS1 and CS2+CS3"); 2685614e71bSYork Sun break; 2695614e71bSYork Sun default: 2705614e71bSYork Sun puts("invalid"); 2715614e71bSYork Sun break; 2725614e71bSYork Sun } 2735614e71bSYork Sun } 2745614e71bSYork Sun } 275