15614e71bSYork Sun /* 234e026f9SYork Sun * Copyright 2008-2014 Freescale Semiconductor, Inc. 35614e71bSYork Sun * 45614e71bSYork Sun * This program is free software; you can redistribute it and/or 55614e71bSYork Sun * modify it under the terms of the GNU General Public License 65614e71bSYork Sun * Version 2 as published by the Free Software Foundation. 75614e71bSYork Sun */ 85614e71bSYork Sun 95614e71bSYork Sun #include <common.h> 109ac4ffbdSYork Sun #ifdef CONFIG_PPC 115614e71bSYork Sun #include <asm/fsl_law.h> 129ac4ffbdSYork Sun #endif 135614e71bSYork Sun #include <div64.h> 145614e71bSYork Sun 155614e71bSYork Sun #include <fsl_ddr.h> 169a17eb5bSYork Sun #include <fsl_immap.h> 175614e71bSYork Sun #include <asm/io.h> 185614e71bSYork Sun 195614e71bSYork Sun /* To avoid 64-bit full-divides, we factor this here */ 205614e71bSYork Sun #define ULL_2E12 2000000000000ULL 215614e71bSYork Sun #define UL_5POW12 244140625UL 225614e71bSYork Sun #define UL_2POW13 (1UL << 13) 235614e71bSYork Sun 245614e71bSYork Sun #define ULL_8FS 0xFFFFFFFFULL 255614e71bSYork Sun 26*66869f95SYork Sun u32 fsl_ddr_get_version(unsigned int ctrl_num) 2734e026f9SYork Sun { 2834e026f9SYork Sun struct ccsr_ddr __iomem *ddr; 2934e026f9SYork Sun u32 ver_major_minor_errata; 3034e026f9SYork Sun 31*66869f95SYork Sun switch (ctrl_num) { 32*66869f95SYork Sun case 0: 33*66869f95SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 34*66869f95SYork Sun break; 35*66869f95SYork Sun #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 36*66869f95SYork Sun case 1: 37*66869f95SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 38*66869f95SYork Sun break; 39*66869f95SYork Sun #endif 40*66869f95SYork Sun #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 41*66869f95SYork Sun case 2: 42*66869f95SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 43*66869f95SYork Sun break; 44*66869f95SYork Sun #endif 45*66869f95SYork Sun #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 46*66869f95SYork Sun case 3: 47*66869f95SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 48*66869f95SYork Sun break; 49*66869f95SYork Sun #endif 50*66869f95SYork Sun default: 51*66869f95SYork Sun printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 52*66869f95SYork Sun return 0; 53*66869f95SYork Sun } 5434e026f9SYork Sun ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; 5534e026f9SYork Sun ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; 5634e026f9SYork Sun 5734e026f9SYork Sun return ver_major_minor_errata; 5834e026f9SYork Sun } 5934e026f9SYork Sun 605614e71bSYork Sun /* 615614e71bSYork Sun * Round up mclk_ps to nearest 1 ps in memory controller code 625614e71bSYork Sun * if the error is 0.5ps or more. 635614e71bSYork Sun * 645614e71bSYork Sun * If an imprecise data rate is too high due to rounding error 655614e71bSYork Sun * propagation, compute a suitably rounded mclk_ps to compute 665614e71bSYork Sun * a working memory controller configuration. 675614e71bSYork Sun */ 6803e664d8SYork Sun unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num) 695614e71bSYork Sun { 7003e664d8SYork Sun unsigned int data_rate = get_ddr_freq(ctrl_num); 715614e71bSYork Sun unsigned int result; 725614e71bSYork Sun 735614e71bSYork Sun /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ 745614e71bSYork Sun unsigned long long rem, mclk_ps = ULL_2E12; 755614e71bSYork Sun 765614e71bSYork Sun /* Now perform the big divide, the result fits in 32-bits */ 775614e71bSYork Sun rem = do_div(mclk_ps, data_rate); 785614e71bSYork Sun result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; 795614e71bSYork Sun 805614e71bSYork Sun return result; 815614e71bSYork Sun } 825614e71bSYork Sun 835614e71bSYork Sun /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ 8403e664d8SYork Sun unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos) 855614e71bSYork Sun { 865614e71bSYork Sun unsigned long long clks, clks_rem; 8703e664d8SYork Sun unsigned long data_rate = get_ddr_freq(ctrl_num); 885614e71bSYork Sun 895614e71bSYork Sun /* Short circuit for zero picos */ 905614e71bSYork Sun if (!picos) 915614e71bSYork Sun return 0; 925614e71bSYork Sun 935614e71bSYork Sun /* First multiply the time by the data rate (32x32 => 64) */ 945614e71bSYork Sun clks = picos * (unsigned long long)data_rate; 955614e71bSYork Sun /* 965614e71bSYork Sun * Now divide by 5^12 and track the 32-bit remainder, then divide 975614e71bSYork Sun * by 2*(2^12) using shifts (and updating the remainder). 985614e71bSYork Sun */ 995614e71bSYork Sun clks_rem = do_div(clks, UL_5POW12); 1005614e71bSYork Sun clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; 1015614e71bSYork Sun clks >>= 13; 1025614e71bSYork Sun 1035614e71bSYork Sun /* If we had a remainder greater than the 1ps error, then round up */ 1045614e71bSYork Sun if (clks_rem > data_rate) 1055614e71bSYork Sun clks++; 1065614e71bSYork Sun 1075614e71bSYork Sun /* Clamp to the maximum representable value */ 1085614e71bSYork Sun if (clks > ULL_8FS) 1095614e71bSYork Sun clks = ULL_8FS; 1105614e71bSYork Sun return (unsigned int) clks; 1115614e71bSYork Sun } 1125614e71bSYork Sun 11303e664d8SYork Sun unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk) 1145614e71bSYork Sun { 11503e664d8SYork Sun return get_memory_clk_period_ps(ctrl_num) * mclk; 1165614e71bSYork Sun } 1175614e71bSYork Sun 1189ac4ffbdSYork Sun #ifdef CONFIG_PPC 1195614e71bSYork Sun void 1205614e71bSYork Sun __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 1215614e71bSYork Sun unsigned int law_memctl, 1225614e71bSYork Sun unsigned int ctrl_num) 1235614e71bSYork Sun { 1245614e71bSYork Sun unsigned long long base = memctl_common_params->base_address; 1255614e71bSYork Sun unsigned long long size = memctl_common_params->total_mem; 1265614e71bSYork Sun 1275614e71bSYork Sun /* 1285614e71bSYork Sun * If no DIMMs on this controller, do not proceed any further. 1295614e71bSYork Sun */ 1305614e71bSYork Sun if (!memctl_common_params->ndimms_present) { 1315614e71bSYork Sun return; 1325614e71bSYork Sun } 1335614e71bSYork Sun 1345614e71bSYork Sun #if !defined(CONFIG_PHYS_64BIT) 1355614e71bSYork Sun if (base >= CONFIG_MAX_MEM_MAPPED) 1365614e71bSYork Sun return; 1375614e71bSYork Sun if ((base + size) >= CONFIG_MAX_MEM_MAPPED) 1385614e71bSYork Sun size = CONFIG_MAX_MEM_MAPPED - base; 1395614e71bSYork Sun #endif 1405614e71bSYork Sun if (set_ddr_laws(base, size, law_memctl) < 0) { 1415614e71bSYork Sun printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, 1425614e71bSYork Sun law_memctl); 1435614e71bSYork Sun return ; 1445614e71bSYork Sun } 1455614e71bSYork Sun debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", 1465614e71bSYork Sun base, size, law_memctl); 1475614e71bSYork Sun } 1485614e71bSYork Sun 1495614e71bSYork Sun __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void 1505614e71bSYork Sun fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 1515614e71bSYork Sun unsigned int memctl_interleaved, 1525614e71bSYork Sun unsigned int ctrl_num); 1539ac4ffbdSYork Sun #endif 1545614e71bSYork Sun 1555614e71bSYork Sun void fsl_ddr_set_intl3r(const unsigned int granule_size) 1565614e71bSYork Sun { 1575614e71bSYork Sun #ifdef CONFIG_E6500 1585614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1595614e71bSYork Sun *mcintl3r = 0x80000000 | (granule_size & 0x1f); 1605614e71bSYork Sun debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); 1615614e71bSYork Sun #endif 1625614e71bSYork Sun } 1635614e71bSYork Sun 1645614e71bSYork Sun u32 fsl_ddr_get_intl3r(void) 1655614e71bSYork Sun { 1665614e71bSYork Sun u32 val = 0; 1675614e71bSYork Sun #ifdef CONFIG_E6500 1685614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1695614e71bSYork Sun val = *mcintl3r; 1705614e71bSYork Sun #endif 1715614e71bSYork Sun return val; 1725614e71bSYork Sun } 1735614e71bSYork Sun 1741d71efbbSYork Sun void print_ddr_info(unsigned int start_ctrl) 1755614e71bSYork Sun { 1769a17eb5bSYork Sun struct ccsr_ddr __iomem *ddr = 1779a17eb5bSYork Sun (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 1785614e71bSYork Sun 1795614e71bSYork Sun #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) 1805614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1815614e71bSYork Sun #endif 1825614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS > 1) 1834e5b1bd0SYork Sun uint32_t cs0_config = ddr_in32(&ddr->cs0_config); 1845614e71bSYork Sun #endif 1854e5b1bd0SYork Sun uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); 1865614e71bSYork Sun int cas_lat; 1875614e71bSYork Sun 1885614e71bSYork Sun #if CONFIG_NUM_DDR_CONTROLLERS >= 2 1891d71efbbSYork Sun if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || 1901d71efbbSYork Sun (start_ctrl == 1)) { 1915614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; 1924e5b1bd0SYork Sun sdram_cfg = ddr_in32(&ddr->sdram_cfg); 1935614e71bSYork Sun } 1945614e71bSYork Sun #endif 1955614e71bSYork Sun #if CONFIG_NUM_DDR_CONTROLLERS >= 3 1961d71efbbSYork Sun if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || 1971d71efbbSYork Sun (start_ctrl == 2)) { 1985614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; 1994e5b1bd0SYork Sun sdram_cfg = ddr_in32(&ddr->sdram_cfg); 2005614e71bSYork Sun } 2015614e71bSYork Sun #endif 2021d71efbbSYork Sun 2031d71efbbSYork Sun if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 2041d71efbbSYork Sun puts(" (DDR not enabled)\n"); 2051d71efbbSYork Sun return; 2061d71efbbSYork Sun } 2071d71efbbSYork Sun 2085614e71bSYork Sun puts(" (DDR"); 2095614e71bSYork Sun switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> 2105614e71bSYork Sun SDRAM_CFG_SDRAM_TYPE_SHIFT) { 2115614e71bSYork Sun case SDRAM_TYPE_DDR1: 2125614e71bSYork Sun puts("1"); 2135614e71bSYork Sun break; 2145614e71bSYork Sun case SDRAM_TYPE_DDR2: 2155614e71bSYork Sun puts("2"); 2165614e71bSYork Sun break; 2175614e71bSYork Sun case SDRAM_TYPE_DDR3: 2185614e71bSYork Sun puts("3"); 2195614e71bSYork Sun break; 22034e026f9SYork Sun case SDRAM_TYPE_DDR4: 22134e026f9SYork Sun puts("4"); 22234e026f9SYork Sun break; 2235614e71bSYork Sun default: 2245614e71bSYork Sun puts("?"); 2255614e71bSYork Sun break; 2265614e71bSYork Sun } 2275614e71bSYork Sun 2285614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_32_BE) 2295614e71bSYork Sun puts(", 32-bit"); 2305614e71bSYork Sun else if (sdram_cfg & SDRAM_CFG_16_BE) 2315614e71bSYork Sun puts(", 16-bit"); 2325614e71bSYork Sun else 2335614e71bSYork Sun puts(", 64-bit"); 2345614e71bSYork Sun 2355614e71bSYork Sun /* Calculate CAS latency based on timing cfg values */ 23634e026f9SYork Sun cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); 237*66869f95SYork Sun if (fsl_ddr_get_version(0) <= 0x40400) 23834e026f9SYork Sun cas_lat += 1; 23934e026f9SYork Sun else 24034e026f9SYork Sun cas_lat += 2; 24134e026f9SYork Sun cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; 2425614e71bSYork Sun printf(", CL=%d", cas_lat >> 1); 2435614e71bSYork Sun if (cas_lat & 0x1) 2445614e71bSYork Sun puts(".5"); 2455614e71bSYork Sun 2465614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_ECC_EN) 2475614e71bSYork Sun puts(", ECC on)"); 2485614e71bSYork Sun else 2495614e71bSYork Sun puts(", ECC off)"); 2505614e71bSYork Sun 2515614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS == 3) 2525614e71bSYork Sun #ifdef CONFIG_E6500 2535614e71bSYork Sun if (*mcintl3r & 0x80000000) { 2545614e71bSYork Sun puts("\n"); 2555614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 2565614e71bSYork Sun switch (*mcintl3r & 0x1f) { 2575614e71bSYork Sun case FSL_DDR_3WAY_1KB_INTERLEAVING: 2585614e71bSYork Sun puts("3-way 1KB"); 2595614e71bSYork Sun break; 2605614e71bSYork Sun case FSL_DDR_3WAY_4KB_INTERLEAVING: 2615614e71bSYork Sun puts("3-way 4KB"); 2625614e71bSYork Sun break; 2635614e71bSYork Sun case FSL_DDR_3WAY_8KB_INTERLEAVING: 2645614e71bSYork Sun puts("3-way 8KB"); 2655614e71bSYork Sun break; 2665614e71bSYork Sun default: 2675614e71bSYork Sun puts("3-way UNKNOWN"); 2685614e71bSYork Sun break; 2695614e71bSYork Sun } 2705614e71bSYork Sun } 2715614e71bSYork Sun #endif 2725614e71bSYork Sun #endif 2735614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 2741d71efbbSYork Sun if ((cs0_config & 0x20000000) && (start_ctrl == 0)) { 2755614e71bSYork Sun puts("\n"); 2765614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 2775614e71bSYork Sun 2785614e71bSYork Sun switch ((cs0_config >> 24) & 0xf) { 2796b1e1254SYork Sun case FSL_DDR_256B_INTERLEAVING: 2806b1e1254SYork Sun puts("256B"); 2816b1e1254SYork Sun break; 2825614e71bSYork Sun case FSL_DDR_CACHE_LINE_INTERLEAVING: 2835614e71bSYork Sun puts("cache line"); 2845614e71bSYork Sun break; 2855614e71bSYork Sun case FSL_DDR_PAGE_INTERLEAVING: 2865614e71bSYork Sun puts("page"); 2875614e71bSYork Sun break; 2885614e71bSYork Sun case FSL_DDR_BANK_INTERLEAVING: 2895614e71bSYork Sun puts("bank"); 2905614e71bSYork Sun break; 2915614e71bSYork Sun case FSL_DDR_SUPERBANK_INTERLEAVING: 2925614e71bSYork Sun puts("super-bank"); 2935614e71bSYork Sun break; 2945614e71bSYork Sun default: 2955614e71bSYork Sun puts("invalid"); 2965614e71bSYork Sun break; 2975614e71bSYork Sun } 2985614e71bSYork Sun } 2995614e71bSYork Sun #endif 3005614e71bSYork Sun 3015614e71bSYork Sun if ((sdram_cfg >> 8) & 0x7f) { 3025614e71bSYork Sun puts("\n"); 3035614e71bSYork Sun puts(" DDR Chip-Select Interleaving Mode: "); 3045614e71bSYork Sun switch(sdram_cfg >> 8 & 0x7f) { 3055614e71bSYork Sun case FSL_DDR_CS0_CS1_CS2_CS3: 3065614e71bSYork Sun puts("CS0+CS1+CS2+CS3"); 3075614e71bSYork Sun break; 3085614e71bSYork Sun case FSL_DDR_CS0_CS1: 3095614e71bSYork Sun puts("CS0+CS1"); 3105614e71bSYork Sun break; 3115614e71bSYork Sun case FSL_DDR_CS2_CS3: 3125614e71bSYork Sun puts("CS2+CS3"); 3135614e71bSYork Sun break; 3145614e71bSYork Sun case FSL_DDR_CS0_CS1_AND_CS2_CS3: 3155614e71bSYork Sun puts("CS0+CS1 and CS2+CS3"); 3165614e71bSYork Sun break; 3175614e71bSYork Sun default: 3185614e71bSYork Sun puts("invalid"); 3195614e71bSYork Sun break; 3205614e71bSYork Sun } 3215614e71bSYork Sun } 3225614e71bSYork Sun } 3231d71efbbSYork Sun 3241d71efbbSYork Sun void __weak detail_board_ddr_info(void) 3251d71efbbSYork Sun { 3261d71efbbSYork Sun print_ddr_info(0); 3271d71efbbSYork Sun } 3281d71efbbSYork Sun 3291d71efbbSYork Sun void board_add_ram_info(int use_default) 3301d71efbbSYork Sun { 3311d71efbbSYork Sun detail_board_ddr_info(); 3321d71efbbSYork Sun } 333e32d59a2SYork Sun 334e32d59a2SYork Sun #ifdef CONFIG_FSL_DDR_SYNC_REFRESH 335e32d59a2SYork Sun #define DDRC_DEBUG20_INIT_DONE 0x80000000 336e32d59a2SYork Sun #define DDRC_DEBUG2_RF 0x00000040 337e32d59a2SYork Sun void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, 338e32d59a2SYork Sun unsigned int last_ctrl) 339e32d59a2SYork Sun { 340e32d59a2SYork Sun unsigned int i; 341e32d59a2SYork Sun u32 ddrc_debug20; 342e32d59a2SYork Sun u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {}; 343e32d59a2SYork Sun u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {}; 344e32d59a2SYork Sun struct ccsr_ddr __iomem *ddr; 345e32d59a2SYork Sun 346e32d59a2SYork Sun for (i = first_ctrl; i <= last_ctrl; i++) { 347e32d59a2SYork Sun switch (i) { 348e32d59a2SYork Sun case 0: 349e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 350e32d59a2SYork Sun break; 351e32d59a2SYork Sun #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 352e32d59a2SYork Sun case 1: 353e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 354e32d59a2SYork Sun break; 355e32d59a2SYork Sun #endif 356e32d59a2SYork Sun #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 357e32d59a2SYork Sun case 2: 358e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 359e32d59a2SYork Sun break; 360e32d59a2SYork Sun #endif 361e32d59a2SYork Sun #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 362e32d59a2SYork Sun case 3: 363e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 364e32d59a2SYork Sun break; 365e32d59a2SYork Sun #endif 366e32d59a2SYork Sun default: 367e32d59a2SYork Sun printf("%s unexpected ctrl = %u\n", __func__, i); 368e32d59a2SYork Sun return; 369e32d59a2SYork Sun } 370e32d59a2SYork Sun ddrc_debug20 = ddr_in32(&ddr->debug[19]); 371e32d59a2SYork Sun ddrc_debug2_p[i] = &ddr->debug[1]; 372e32d59a2SYork Sun while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) { 373e32d59a2SYork Sun /* keep polling until DDRC init is done */ 374e32d59a2SYork Sun udelay(100); 375e32d59a2SYork Sun ddrc_debug20 = ddr_in32(&ddr->debug[19]); 376e32d59a2SYork Sun } 377e32d59a2SYork Sun ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF; 378e32d59a2SYork Sun } 379e32d59a2SYork Sun /* 380e32d59a2SYork Sun * Sync refresh 381e32d59a2SYork Sun * This is put together to make sure the refresh reqeusts are sent 382e32d59a2SYork Sun * closely to each other. 383e32d59a2SYork Sun */ 384e32d59a2SYork Sun for (i = first_ctrl; i <= last_ctrl; i++) 385e32d59a2SYork Sun ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]); 386e32d59a2SYork Sun } 387e32d59a2SYork Sun #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */ 388