1*5614e71bSYork Sun /* 2*5614e71bSYork Sun * Copyright 2008-2012 Freescale Semiconductor, Inc. 3*5614e71bSYork Sun * 4*5614e71bSYork Sun * This program is free software; you can redistribute it and/or 5*5614e71bSYork Sun * modify it under the terms of the GNU General Public License 6*5614e71bSYork Sun * Version 2 as published by the Free Software Foundation. 7*5614e71bSYork Sun */ 8*5614e71bSYork Sun 9*5614e71bSYork Sun #include <common.h> 10*5614e71bSYork Sun #include <asm/fsl_law.h> 11*5614e71bSYork Sun #include <div64.h> 12*5614e71bSYork Sun 13*5614e71bSYork Sun #include <fsl_ddr.h> 14*5614e71bSYork Sun #include <asm/io.h> 15*5614e71bSYork Sun 16*5614e71bSYork Sun /* To avoid 64-bit full-divides, we factor this here */ 17*5614e71bSYork Sun #define ULL_2E12 2000000000000ULL 18*5614e71bSYork Sun #define UL_5POW12 244140625UL 19*5614e71bSYork Sun #define UL_2POW13 (1UL << 13) 20*5614e71bSYork Sun 21*5614e71bSYork Sun #define ULL_8FS 0xFFFFFFFFULL 22*5614e71bSYork Sun 23*5614e71bSYork Sun /* 24*5614e71bSYork Sun * Round up mclk_ps to nearest 1 ps in memory controller code 25*5614e71bSYork Sun * if the error is 0.5ps or more. 26*5614e71bSYork Sun * 27*5614e71bSYork Sun * If an imprecise data rate is too high due to rounding error 28*5614e71bSYork Sun * propagation, compute a suitably rounded mclk_ps to compute 29*5614e71bSYork Sun * a working memory controller configuration. 30*5614e71bSYork Sun */ 31*5614e71bSYork Sun unsigned int get_memory_clk_period_ps(void) 32*5614e71bSYork Sun { 33*5614e71bSYork Sun unsigned int data_rate = get_ddr_freq(0); 34*5614e71bSYork Sun unsigned int result; 35*5614e71bSYork Sun 36*5614e71bSYork Sun /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ 37*5614e71bSYork Sun unsigned long long rem, mclk_ps = ULL_2E12; 38*5614e71bSYork Sun 39*5614e71bSYork Sun /* Now perform the big divide, the result fits in 32-bits */ 40*5614e71bSYork Sun rem = do_div(mclk_ps, data_rate); 41*5614e71bSYork Sun result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; 42*5614e71bSYork Sun 43*5614e71bSYork Sun return result; 44*5614e71bSYork Sun } 45*5614e71bSYork Sun 46*5614e71bSYork Sun /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ 47*5614e71bSYork Sun unsigned int picos_to_mclk(unsigned int picos) 48*5614e71bSYork Sun { 49*5614e71bSYork Sun unsigned long long clks, clks_rem; 50*5614e71bSYork Sun unsigned long data_rate = get_ddr_freq(0); 51*5614e71bSYork Sun 52*5614e71bSYork Sun /* Short circuit for zero picos */ 53*5614e71bSYork Sun if (!picos) 54*5614e71bSYork Sun return 0; 55*5614e71bSYork Sun 56*5614e71bSYork Sun /* First multiply the time by the data rate (32x32 => 64) */ 57*5614e71bSYork Sun clks = picos * (unsigned long long)data_rate; 58*5614e71bSYork Sun /* 59*5614e71bSYork Sun * Now divide by 5^12 and track the 32-bit remainder, then divide 60*5614e71bSYork Sun * by 2*(2^12) using shifts (and updating the remainder). 61*5614e71bSYork Sun */ 62*5614e71bSYork Sun clks_rem = do_div(clks, UL_5POW12); 63*5614e71bSYork Sun clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; 64*5614e71bSYork Sun clks >>= 13; 65*5614e71bSYork Sun 66*5614e71bSYork Sun /* If we had a remainder greater than the 1ps error, then round up */ 67*5614e71bSYork Sun if (clks_rem > data_rate) 68*5614e71bSYork Sun clks++; 69*5614e71bSYork Sun 70*5614e71bSYork Sun /* Clamp to the maximum representable value */ 71*5614e71bSYork Sun if (clks > ULL_8FS) 72*5614e71bSYork Sun clks = ULL_8FS; 73*5614e71bSYork Sun return (unsigned int) clks; 74*5614e71bSYork Sun } 75*5614e71bSYork Sun 76*5614e71bSYork Sun unsigned int mclk_to_picos(unsigned int mclk) 77*5614e71bSYork Sun { 78*5614e71bSYork Sun return get_memory_clk_period_ps() * mclk; 79*5614e71bSYork Sun } 80*5614e71bSYork Sun 81*5614e71bSYork Sun void 82*5614e71bSYork Sun __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 83*5614e71bSYork Sun unsigned int law_memctl, 84*5614e71bSYork Sun unsigned int ctrl_num) 85*5614e71bSYork Sun { 86*5614e71bSYork Sun unsigned long long base = memctl_common_params->base_address; 87*5614e71bSYork Sun unsigned long long size = memctl_common_params->total_mem; 88*5614e71bSYork Sun 89*5614e71bSYork Sun /* 90*5614e71bSYork Sun * If no DIMMs on this controller, do not proceed any further. 91*5614e71bSYork Sun */ 92*5614e71bSYork Sun if (!memctl_common_params->ndimms_present) { 93*5614e71bSYork Sun return; 94*5614e71bSYork Sun } 95*5614e71bSYork Sun 96*5614e71bSYork Sun #if !defined(CONFIG_PHYS_64BIT) 97*5614e71bSYork Sun if (base >= CONFIG_MAX_MEM_MAPPED) 98*5614e71bSYork Sun return; 99*5614e71bSYork Sun if ((base + size) >= CONFIG_MAX_MEM_MAPPED) 100*5614e71bSYork Sun size = CONFIG_MAX_MEM_MAPPED - base; 101*5614e71bSYork Sun #endif 102*5614e71bSYork Sun if (set_ddr_laws(base, size, law_memctl) < 0) { 103*5614e71bSYork Sun printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, 104*5614e71bSYork Sun law_memctl); 105*5614e71bSYork Sun return ; 106*5614e71bSYork Sun } 107*5614e71bSYork Sun debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", 108*5614e71bSYork Sun base, size, law_memctl); 109*5614e71bSYork Sun } 110*5614e71bSYork Sun 111*5614e71bSYork Sun __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void 112*5614e71bSYork Sun fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 113*5614e71bSYork Sun unsigned int memctl_interleaved, 114*5614e71bSYork Sun unsigned int ctrl_num); 115*5614e71bSYork Sun 116*5614e71bSYork Sun void fsl_ddr_set_intl3r(const unsigned int granule_size) 117*5614e71bSYork Sun { 118*5614e71bSYork Sun #ifdef CONFIG_E6500 119*5614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 120*5614e71bSYork Sun *mcintl3r = 0x80000000 | (granule_size & 0x1f); 121*5614e71bSYork Sun debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); 122*5614e71bSYork Sun #endif 123*5614e71bSYork Sun } 124*5614e71bSYork Sun 125*5614e71bSYork Sun u32 fsl_ddr_get_intl3r(void) 126*5614e71bSYork Sun { 127*5614e71bSYork Sun u32 val = 0; 128*5614e71bSYork Sun #ifdef CONFIG_E6500 129*5614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 130*5614e71bSYork Sun val = *mcintl3r; 131*5614e71bSYork Sun #endif 132*5614e71bSYork Sun return val; 133*5614e71bSYork Sun } 134*5614e71bSYork Sun 135*5614e71bSYork Sun void board_add_ram_info(int use_default) 136*5614e71bSYork Sun { 137*5614e71bSYork Sun ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); 138*5614e71bSYork Sun 139*5614e71bSYork Sun #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) 140*5614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 141*5614e71bSYork Sun #endif 142*5614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS > 1) 143*5614e71bSYork Sun uint32_t cs0_config = in_be32(&ddr->cs0_config); 144*5614e71bSYork Sun #endif 145*5614e71bSYork Sun uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); 146*5614e71bSYork Sun int cas_lat; 147*5614e71bSYork Sun 148*5614e71bSYork Sun #if CONFIG_NUM_DDR_CONTROLLERS >= 2 149*5614e71bSYork Sun if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 150*5614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; 151*5614e71bSYork Sun sdram_cfg = in_be32(&ddr->sdram_cfg); 152*5614e71bSYork Sun } 153*5614e71bSYork Sun #endif 154*5614e71bSYork Sun #if CONFIG_NUM_DDR_CONTROLLERS >= 3 155*5614e71bSYork Sun if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 156*5614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; 157*5614e71bSYork Sun sdram_cfg = in_be32(&ddr->sdram_cfg); 158*5614e71bSYork Sun } 159*5614e71bSYork Sun #endif 160*5614e71bSYork Sun puts(" (DDR"); 161*5614e71bSYork Sun switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> 162*5614e71bSYork Sun SDRAM_CFG_SDRAM_TYPE_SHIFT) { 163*5614e71bSYork Sun case SDRAM_TYPE_DDR1: 164*5614e71bSYork Sun puts("1"); 165*5614e71bSYork Sun break; 166*5614e71bSYork Sun case SDRAM_TYPE_DDR2: 167*5614e71bSYork Sun puts("2"); 168*5614e71bSYork Sun break; 169*5614e71bSYork Sun case SDRAM_TYPE_DDR3: 170*5614e71bSYork Sun puts("3"); 171*5614e71bSYork Sun break; 172*5614e71bSYork Sun default: 173*5614e71bSYork Sun puts("?"); 174*5614e71bSYork Sun break; 175*5614e71bSYork Sun } 176*5614e71bSYork Sun 177*5614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_32_BE) 178*5614e71bSYork Sun puts(", 32-bit"); 179*5614e71bSYork Sun else if (sdram_cfg & SDRAM_CFG_16_BE) 180*5614e71bSYork Sun puts(", 16-bit"); 181*5614e71bSYork Sun else 182*5614e71bSYork Sun puts(", 64-bit"); 183*5614e71bSYork Sun 184*5614e71bSYork Sun /* Calculate CAS latency based on timing cfg values */ 185*5614e71bSYork Sun cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; 186*5614e71bSYork Sun if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) 187*5614e71bSYork Sun cas_lat += (8 << 1); 188*5614e71bSYork Sun printf(", CL=%d", cas_lat >> 1); 189*5614e71bSYork Sun if (cas_lat & 0x1) 190*5614e71bSYork Sun puts(".5"); 191*5614e71bSYork Sun 192*5614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_ECC_EN) 193*5614e71bSYork Sun puts(", ECC on)"); 194*5614e71bSYork Sun else 195*5614e71bSYork Sun puts(", ECC off)"); 196*5614e71bSYork Sun 197*5614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS == 3) 198*5614e71bSYork Sun #ifdef CONFIG_E6500 199*5614e71bSYork Sun if (*mcintl3r & 0x80000000) { 200*5614e71bSYork Sun puts("\n"); 201*5614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 202*5614e71bSYork Sun switch (*mcintl3r & 0x1f) { 203*5614e71bSYork Sun case FSL_DDR_3WAY_1KB_INTERLEAVING: 204*5614e71bSYork Sun puts("3-way 1KB"); 205*5614e71bSYork Sun break; 206*5614e71bSYork Sun case FSL_DDR_3WAY_4KB_INTERLEAVING: 207*5614e71bSYork Sun puts("3-way 4KB"); 208*5614e71bSYork Sun break; 209*5614e71bSYork Sun case FSL_DDR_3WAY_8KB_INTERLEAVING: 210*5614e71bSYork Sun puts("3-way 8KB"); 211*5614e71bSYork Sun break; 212*5614e71bSYork Sun default: 213*5614e71bSYork Sun puts("3-way UNKNOWN"); 214*5614e71bSYork Sun break; 215*5614e71bSYork Sun } 216*5614e71bSYork Sun } 217*5614e71bSYork Sun #endif 218*5614e71bSYork Sun #endif 219*5614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 220*5614e71bSYork Sun if (cs0_config & 0x20000000) { 221*5614e71bSYork Sun puts("\n"); 222*5614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 223*5614e71bSYork Sun 224*5614e71bSYork Sun switch ((cs0_config >> 24) & 0xf) { 225*5614e71bSYork Sun case FSL_DDR_CACHE_LINE_INTERLEAVING: 226*5614e71bSYork Sun puts("cache line"); 227*5614e71bSYork Sun break; 228*5614e71bSYork Sun case FSL_DDR_PAGE_INTERLEAVING: 229*5614e71bSYork Sun puts("page"); 230*5614e71bSYork Sun break; 231*5614e71bSYork Sun case FSL_DDR_BANK_INTERLEAVING: 232*5614e71bSYork Sun puts("bank"); 233*5614e71bSYork Sun break; 234*5614e71bSYork Sun case FSL_DDR_SUPERBANK_INTERLEAVING: 235*5614e71bSYork Sun puts("super-bank"); 236*5614e71bSYork Sun break; 237*5614e71bSYork Sun default: 238*5614e71bSYork Sun puts("invalid"); 239*5614e71bSYork Sun break; 240*5614e71bSYork Sun } 241*5614e71bSYork Sun } 242*5614e71bSYork Sun #endif 243*5614e71bSYork Sun 244*5614e71bSYork Sun if ((sdram_cfg >> 8) & 0x7f) { 245*5614e71bSYork Sun puts("\n"); 246*5614e71bSYork Sun puts(" DDR Chip-Select Interleaving Mode: "); 247*5614e71bSYork Sun switch(sdram_cfg >> 8 & 0x7f) { 248*5614e71bSYork Sun case FSL_DDR_CS0_CS1_CS2_CS3: 249*5614e71bSYork Sun puts("CS0+CS1+CS2+CS3"); 250*5614e71bSYork Sun break; 251*5614e71bSYork Sun case FSL_DDR_CS0_CS1: 252*5614e71bSYork Sun puts("CS0+CS1"); 253*5614e71bSYork Sun break; 254*5614e71bSYork Sun case FSL_DDR_CS2_CS3: 255*5614e71bSYork Sun puts("CS2+CS3"); 256*5614e71bSYork Sun break; 257*5614e71bSYork Sun case FSL_DDR_CS0_CS1_AND_CS2_CS3: 258*5614e71bSYork Sun puts("CS0+CS1 and CS2+CS3"); 259*5614e71bSYork Sun break; 260*5614e71bSYork Sun default: 261*5614e71bSYork Sun puts("invalid"); 262*5614e71bSYork Sun break; 263*5614e71bSYork Sun } 264*5614e71bSYork Sun } 265*5614e71bSYork Sun } 266