15614e71bSYork Sun /* 234e026f9SYork Sun * Copyright 2008-2014 Freescale Semiconductor, Inc. 35614e71bSYork Sun * 45b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0 55614e71bSYork Sun */ 65614e71bSYork Sun 75614e71bSYork Sun #include <common.h> 89ac4ffbdSYork Sun #ifdef CONFIG_PPC 95614e71bSYork Sun #include <asm/fsl_law.h> 109ac4ffbdSYork Sun #endif 115614e71bSYork Sun #include <div64.h> 125614e71bSYork Sun 135614e71bSYork Sun #include <fsl_ddr.h> 149a17eb5bSYork Sun #include <fsl_immap.h> 155614e71bSYork Sun #include <asm/io.h> 16*457e51cfSSimon Glass #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ 17*457e51cfSSimon Glass defined(CONFIG_ARM) 186e2941d7SSimon Glass #include <asm/arch/clock.h> 196e2941d7SSimon Glass #endif 205614e71bSYork Sun 215614e71bSYork Sun /* To avoid 64-bit full-divides, we factor this here */ 225614e71bSYork Sun #define ULL_2E12 2000000000000ULL 235614e71bSYork Sun #define UL_5POW12 244140625UL 245614e71bSYork Sun #define UL_2POW13 (1UL << 13) 255614e71bSYork Sun 265614e71bSYork Sun #define ULL_8FS 0xFFFFFFFFULL 275614e71bSYork Sun 2866869f95SYork Sun u32 fsl_ddr_get_version(unsigned int ctrl_num) 2934e026f9SYork Sun { 3034e026f9SYork Sun struct ccsr_ddr __iomem *ddr; 3134e026f9SYork Sun u32 ver_major_minor_errata; 3234e026f9SYork Sun 3366869f95SYork Sun switch (ctrl_num) { 3466869f95SYork Sun case 0: 3566869f95SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 3666869f95SYork Sun break; 3751370d56SYork Sun #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) 3866869f95SYork Sun case 1: 3966869f95SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 4066869f95SYork Sun break; 4166869f95SYork Sun #endif 4251370d56SYork Sun #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) 4366869f95SYork Sun case 2: 4466869f95SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 4566869f95SYork Sun break; 4666869f95SYork Sun #endif 4751370d56SYork Sun #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) 4866869f95SYork Sun case 3: 4966869f95SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 5066869f95SYork Sun break; 5166869f95SYork Sun #endif 5266869f95SYork Sun default: 5366869f95SYork Sun printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 5466869f95SYork Sun return 0; 5566869f95SYork Sun } 5634e026f9SYork Sun ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; 5734e026f9SYork Sun ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; 5834e026f9SYork Sun 5934e026f9SYork Sun return ver_major_minor_errata; 6034e026f9SYork Sun } 6134e026f9SYork Sun 625614e71bSYork Sun /* 635614e71bSYork Sun * Round up mclk_ps to nearest 1 ps in memory controller code 645614e71bSYork Sun * if the error is 0.5ps or more. 655614e71bSYork Sun * 665614e71bSYork Sun * If an imprecise data rate is too high due to rounding error 675614e71bSYork Sun * propagation, compute a suitably rounded mclk_ps to compute 685614e71bSYork Sun * a working memory controller configuration. 695614e71bSYork Sun */ 7003e664d8SYork Sun unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num) 715614e71bSYork Sun { 7203e664d8SYork Sun unsigned int data_rate = get_ddr_freq(ctrl_num); 735614e71bSYork Sun unsigned int result; 745614e71bSYork Sun 755614e71bSYork Sun /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ 765614e71bSYork Sun unsigned long long rem, mclk_ps = ULL_2E12; 775614e71bSYork Sun 785614e71bSYork Sun /* Now perform the big divide, the result fits in 32-bits */ 795614e71bSYork Sun rem = do_div(mclk_ps, data_rate); 805614e71bSYork Sun result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; 815614e71bSYork Sun 825614e71bSYork Sun return result; 835614e71bSYork Sun } 845614e71bSYork Sun 855614e71bSYork Sun /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ 8603e664d8SYork Sun unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos) 875614e71bSYork Sun { 885614e71bSYork Sun unsigned long long clks, clks_rem; 8903e664d8SYork Sun unsigned long data_rate = get_ddr_freq(ctrl_num); 905614e71bSYork Sun 915614e71bSYork Sun /* Short circuit for zero picos */ 925614e71bSYork Sun if (!picos) 935614e71bSYork Sun return 0; 945614e71bSYork Sun 955614e71bSYork Sun /* First multiply the time by the data rate (32x32 => 64) */ 965614e71bSYork Sun clks = picos * (unsigned long long)data_rate; 975614e71bSYork Sun /* 985614e71bSYork Sun * Now divide by 5^12 and track the 32-bit remainder, then divide 995614e71bSYork Sun * by 2*(2^12) using shifts (and updating the remainder). 1005614e71bSYork Sun */ 1015614e71bSYork Sun clks_rem = do_div(clks, UL_5POW12); 1025614e71bSYork Sun clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; 1035614e71bSYork Sun clks >>= 13; 1045614e71bSYork Sun 1055614e71bSYork Sun /* If we had a remainder greater than the 1ps error, then round up */ 1065614e71bSYork Sun if (clks_rem > data_rate) 1075614e71bSYork Sun clks++; 1085614e71bSYork Sun 1095614e71bSYork Sun /* Clamp to the maximum representable value */ 1105614e71bSYork Sun if (clks > ULL_8FS) 1115614e71bSYork Sun clks = ULL_8FS; 1125614e71bSYork Sun return (unsigned int) clks; 1135614e71bSYork Sun } 1145614e71bSYork Sun 11503e664d8SYork Sun unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk) 1165614e71bSYork Sun { 11703e664d8SYork Sun return get_memory_clk_period_ps(ctrl_num) * mclk; 1185614e71bSYork Sun } 1195614e71bSYork Sun 1209ac4ffbdSYork Sun #ifdef CONFIG_PPC 1215614e71bSYork Sun void 1225614e71bSYork Sun __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 1235614e71bSYork Sun unsigned int law_memctl, 1245614e71bSYork Sun unsigned int ctrl_num) 1255614e71bSYork Sun { 1265614e71bSYork Sun unsigned long long base = memctl_common_params->base_address; 1275614e71bSYork Sun unsigned long long size = memctl_common_params->total_mem; 1285614e71bSYork Sun 1295614e71bSYork Sun /* 1305614e71bSYork Sun * If no DIMMs on this controller, do not proceed any further. 1315614e71bSYork Sun */ 1325614e71bSYork Sun if (!memctl_common_params->ndimms_present) { 1335614e71bSYork Sun return; 1345614e71bSYork Sun } 1355614e71bSYork Sun 1365614e71bSYork Sun #if !defined(CONFIG_PHYS_64BIT) 1375614e71bSYork Sun if (base >= CONFIG_MAX_MEM_MAPPED) 1385614e71bSYork Sun return; 1395614e71bSYork Sun if ((base + size) >= CONFIG_MAX_MEM_MAPPED) 1405614e71bSYork Sun size = CONFIG_MAX_MEM_MAPPED - base; 1415614e71bSYork Sun #endif 1425614e71bSYork Sun if (set_ddr_laws(base, size, law_memctl) < 0) { 1435614e71bSYork Sun printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, 1445614e71bSYork Sun law_memctl); 1455614e71bSYork Sun return ; 1465614e71bSYork Sun } 1475614e71bSYork Sun debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", 1485614e71bSYork Sun base, size, law_memctl); 1495614e71bSYork Sun } 1505614e71bSYork Sun 1515614e71bSYork Sun __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void 1525614e71bSYork Sun fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 1535614e71bSYork Sun unsigned int memctl_interleaved, 1545614e71bSYork Sun unsigned int ctrl_num); 1559ac4ffbdSYork Sun #endif 1565614e71bSYork Sun 1575614e71bSYork Sun void fsl_ddr_set_intl3r(const unsigned int granule_size) 1585614e71bSYork Sun { 1595614e71bSYork Sun #ifdef CONFIG_E6500 1605614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1615614e71bSYork Sun *mcintl3r = 0x80000000 | (granule_size & 0x1f); 1625614e71bSYork Sun debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); 1635614e71bSYork Sun #endif 1645614e71bSYork Sun } 1655614e71bSYork Sun 1665614e71bSYork Sun u32 fsl_ddr_get_intl3r(void) 1675614e71bSYork Sun { 1685614e71bSYork Sun u32 val = 0; 1695614e71bSYork Sun #ifdef CONFIG_E6500 1705614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1715614e71bSYork Sun val = *mcintl3r; 1725614e71bSYork Sun #endif 1735614e71bSYork Sun return val; 1745614e71bSYork Sun } 1755614e71bSYork Sun 1761d71efbbSYork Sun void print_ddr_info(unsigned int start_ctrl) 1775614e71bSYork Sun { 1789a17eb5bSYork Sun struct ccsr_ddr __iomem *ddr = 1799a17eb5bSYork Sun (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 1805614e71bSYork Sun 18151370d56SYork Sun #if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3) 1825614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1835614e71bSYork Sun #endif 18451370d56SYork Sun #if (CONFIG_SYS_NUM_DDR_CTLRS > 1) 1854e5b1bd0SYork Sun uint32_t cs0_config = ddr_in32(&ddr->cs0_config); 1865614e71bSYork Sun #endif 1874e5b1bd0SYork Sun uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); 1885614e71bSYork Sun int cas_lat; 1895614e71bSYork Sun 19051370d56SYork Sun #if CONFIG_SYS_NUM_DDR_CTLRS >= 2 1911d71efbbSYork Sun if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || 1921d71efbbSYork Sun (start_ctrl == 1)) { 1935614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; 1944e5b1bd0SYork Sun sdram_cfg = ddr_in32(&ddr->sdram_cfg); 1955614e71bSYork Sun } 1965614e71bSYork Sun #endif 19751370d56SYork Sun #if CONFIG_SYS_NUM_DDR_CTLRS >= 3 1981d71efbbSYork Sun if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || 1991d71efbbSYork Sun (start_ctrl == 2)) { 2005614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; 2014e5b1bd0SYork Sun sdram_cfg = ddr_in32(&ddr->sdram_cfg); 2025614e71bSYork Sun } 2035614e71bSYork Sun #endif 2041d71efbbSYork Sun 2051d71efbbSYork Sun if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 2061d71efbbSYork Sun puts(" (DDR not enabled)\n"); 2071d71efbbSYork Sun return; 2081d71efbbSYork Sun } 2091d71efbbSYork Sun 2105614e71bSYork Sun puts(" (DDR"); 2115614e71bSYork Sun switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> 2125614e71bSYork Sun SDRAM_CFG_SDRAM_TYPE_SHIFT) { 2135614e71bSYork Sun case SDRAM_TYPE_DDR1: 2145614e71bSYork Sun puts("1"); 2155614e71bSYork Sun break; 2165614e71bSYork Sun case SDRAM_TYPE_DDR2: 2175614e71bSYork Sun puts("2"); 2185614e71bSYork Sun break; 2195614e71bSYork Sun case SDRAM_TYPE_DDR3: 2205614e71bSYork Sun puts("3"); 2215614e71bSYork Sun break; 22234e026f9SYork Sun case SDRAM_TYPE_DDR4: 22334e026f9SYork Sun puts("4"); 22434e026f9SYork Sun break; 2255614e71bSYork Sun default: 2265614e71bSYork Sun puts("?"); 2275614e71bSYork Sun break; 2285614e71bSYork Sun } 2295614e71bSYork Sun 2305614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_32_BE) 2315614e71bSYork Sun puts(", 32-bit"); 2325614e71bSYork Sun else if (sdram_cfg & SDRAM_CFG_16_BE) 2335614e71bSYork Sun puts(", 16-bit"); 2345614e71bSYork Sun else 2355614e71bSYork Sun puts(", 64-bit"); 2365614e71bSYork Sun 2375614e71bSYork Sun /* Calculate CAS latency based on timing cfg values */ 23834e026f9SYork Sun cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); 23966869f95SYork Sun if (fsl_ddr_get_version(0) <= 0x40400) 24034e026f9SYork Sun cas_lat += 1; 24134e026f9SYork Sun else 24234e026f9SYork Sun cas_lat += 2; 24334e026f9SYork Sun cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; 2445614e71bSYork Sun printf(", CL=%d", cas_lat >> 1); 2455614e71bSYork Sun if (cas_lat & 0x1) 2465614e71bSYork Sun puts(".5"); 2475614e71bSYork Sun 2485614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_ECC_EN) 2495614e71bSYork Sun puts(", ECC on)"); 2505614e71bSYork Sun else 2515614e71bSYork Sun puts(", ECC off)"); 2525614e71bSYork Sun 25351370d56SYork Sun #if (CONFIG_SYS_NUM_DDR_CTLRS == 3) 2545614e71bSYork Sun #ifdef CONFIG_E6500 2555614e71bSYork Sun if (*mcintl3r & 0x80000000) { 2565614e71bSYork Sun puts("\n"); 2575614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 2585614e71bSYork Sun switch (*mcintl3r & 0x1f) { 2595614e71bSYork Sun case FSL_DDR_3WAY_1KB_INTERLEAVING: 2605614e71bSYork Sun puts("3-way 1KB"); 2615614e71bSYork Sun break; 2625614e71bSYork Sun case FSL_DDR_3WAY_4KB_INTERLEAVING: 2635614e71bSYork Sun puts("3-way 4KB"); 2645614e71bSYork Sun break; 2655614e71bSYork Sun case FSL_DDR_3WAY_8KB_INTERLEAVING: 2665614e71bSYork Sun puts("3-way 8KB"); 2675614e71bSYork Sun break; 2685614e71bSYork Sun default: 2695614e71bSYork Sun puts("3-way UNKNOWN"); 2705614e71bSYork Sun break; 2715614e71bSYork Sun } 2725614e71bSYork Sun } 2735614e71bSYork Sun #endif 2745614e71bSYork Sun #endif 27551370d56SYork Sun #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 2761d71efbbSYork Sun if ((cs0_config & 0x20000000) && (start_ctrl == 0)) { 2775614e71bSYork Sun puts("\n"); 2785614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 2795614e71bSYork Sun 2805614e71bSYork Sun switch ((cs0_config >> 24) & 0xf) { 2816b1e1254SYork Sun case FSL_DDR_256B_INTERLEAVING: 2826b1e1254SYork Sun puts("256B"); 2836b1e1254SYork Sun break; 2845614e71bSYork Sun case FSL_DDR_CACHE_LINE_INTERLEAVING: 2855614e71bSYork Sun puts("cache line"); 2865614e71bSYork Sun break; 2875614e71bSYork Sun case FSL_DDR_PAGE_INTERLEAVING: 2885614e71bSYork Sun puts("page"); 2895614e71bSYork Sun break; 2905614e71bSYork Sun case FSL_DDR_BANK_INTERLEAVING: 2915614e71bSYork Sun puts("bank"); 2925614e71bSYork Sun break; 2935614e71bSYork Sun case FSL_DDR_SUPERBANK_INTERLEAVING: 2945614e71bSYork Sun puts("super-bank"); 2955614e71bSYork Sun break; 2965614e71bSYork Sun default: 2975614e71bSYork Sun puts("invalid"); 2985614e71bSYork Sun break; 2995614e71bSYork Sun } 3005614e71bSYork Sun } 3015614e71bSYork Sun #endif 3025614e71bSYork Sun 3035614e71bSYork Sun if ((sdram_cfg >> 8) & 0x7f) { 3045614e71bSYork Sun puts("\n"); 3055614e71bSYork Sun puts(" DDR Chip-Select Interleaving Mode: "); 3065614e71bSYork Sun switch(sdram_cfg >> 8 & 0x7f) { 3075614e71bSYork Sun case FSL_DDR_CS0_CS1_CS2_CS3: 3085614e71bSYork Sun puts("CS0+CS1+CS2+CS3"); 3095614e71bSYork Sun break; 3105614e71bSYork Sun case FSL_DDR_CS0_CS1: 3115614e71bSYork Sun puts("CS0+CS1"); 3125614e71bSYork Sun break; 3135614e71bSYork Sun case FSL_DDR_CS2_CS3: 3145614e71bSYork Sun puts("CS2+CS3"); 3155614e71bSYork Sun break; 3165614e71bSYork Sun case FSL_DDR_CS0_CS1_AND_CS2_CS3: 3175614e71bSYork Sun puts("CS0+CS1 and CS2+CS3"); 3185614e71bSYork Sun break; 3195614e71bSYork Sun default: 3205614e71bSYork Sun puts("invalid"); 3215614e71bSYork Sun break; 3225614e71bSYork Sun } 3235614e71bSYork Sun } 3245614e71bSYork Sun } 3251d71efbbSYork Sun 3261d71efbbSYork Sun void __weak detail_board_ddr_info(void) 3271d71efbbSYork Sun { 3281d71efbbSYork Sun print_ddr_info(0); 3291d71efbbSYork Sun } 3301d71efbbSYork Sun 3311d71efbbSYork Sun void board_add_ram_info(int use_default) 3321d71efbbSYork Sun { 3331d71efbbSYork Sun detail_board_ddr_info(); 3341d71efbbSYork Sun } 335e32d59a2SYork Sun 336e32d59a2SYork Sun #ifdef CONFIG_FSL_DDR_SYNC_REFRESH 337e32d59a2SYork Sun #define DDRC_DEBUG20_INIT_DONE 0x80000000 338e32d59a2SYork Sun #define DDRC_DEBUG2_RF 0x00000040 339e32d59a2SYork Sun void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, 340e32d59a2SYork Sun unsigned int last_ctrl) 341e32d59a2SYork Sun { 342e32d59a2SYork Sun unsigned int i; 343e32d59a2SYork Sun u32 ddrc_debug20; 34451370d56SYork Sun u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {}; 34551370d56SYork Sun u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {}; 346e32d59a2SYork Sun struct ccsr_ddr __iomem *ddr; 347e32d59a2SYork Sun 348e32d59a2SYork Sun for (i = first_ctrl; i <= last_ctrl; i++) { 349e32d59a2SYork Sun switch (i) { 350e32d59a2SYork Sun case 0: 351e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 352e32d59a2SYork Sun break; 35351370d56SYork Sun #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) 354e32d59a2SYork Sun case 1: 355e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 356e32d59a2SYork Sun break; 357e32d59a2SYork Sun #endif 35851370d56SYork Sun #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) 359e32d59a2SYork Sun case 2: 360e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 361e32d59a2SYork Sun break; 362e32d59a2SYork Sun #endif 36351370d56SYork Sun #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) 364e32d59a2SYork Sun case 3: 365e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 366e32d59a2SYork Sun break; 367e32d59a2SYork Sun #endif 368e32d59a2SYork Sun default: 369e32d59a2SYork Sun printf("%s unexpected ctrl = %u\n", __func__, i); 370e32d59a2SYork Sun return; 371e32d59a2SYork Sun } 372e32d59a2SYork Sun ddrc_debug20 = ddr_in32(&ddr->debug[19]); 373e32d59a2SYork Sun ddrc_debug2_p[i] = &ddr->debug[1]; 374e32d59a2SYork Sun while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) { 375e32d59a2SYork Sun /* keep polling until DDRC init is done */ 376e32d59a2SYork Sun udelay(100); 377e32d59a2SYork Sun ddrc_debug20 = ddr_in32(&ddr->debug[19]); 378e32d59a2SYork Sun } 379e32d59a2SYork Sun ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF; 380e32d59a2SYork Sun } 381e32d59a2SYork Sun /* 382e32d59a2SYork Sun * Sync refresh 383e32d59a2SYork Sun * This is put together to make sure the refresh reqeusts are sent 384e32d59a2SYork Sun * closely to each other. 385e32d59a2SYork Sun */ 386e32d59a2SYork Sun for (i = first_ctrl; i <= last_ctrl; i++) 387e32d59a2SYork Sun ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]); 388e32d59a2SYork Sun } 389e32d59a2SYork Sun #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */ 39061bd2f75SYork Sun 39161bd2f75SYork Sun void remove_unused_controllers(fsl_ddr_info_t *info) 39261bd2f75SYork Sun { 39361bd2f75SYork Sun #ifdef CONFIG_FSL_LSCH3 39461bd2f75SYork Sun int i; 39561bd2f75SYork Sun u64 nodeid; 39661bd2f75SYork Sun void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL); 39761bd2f75SYork Sun bool ddr0_used = false; 39861bd2f75SYork Sun bool ddr1_used = false; 39961bd2f75SYork Sun 40061bd2f75SYork Sun for (i = 0; i < 8; i++) { 40161bd2f75SYork Sun nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK; 40261bd2f75SYork Sun if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) { 40361bd2f75SYork Sun ddr0_used = true; 40461bd2f75SYork Sun } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) { 40561bd2f75SYork Sun ddr1_used = true; 40661bd2f75SYork Sun } else { 40761bd2f75SYork Sun printf("Unknown nodeid in HN-F SAM control: 0x%llx\n", 40861bd2f75SYork Sun nodeid); 40961bd2f75SYork Sun } 41061bd2f75SYork Sun hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE); 41161bd2f75SYork Sun } 41261bd2f75SYork Sun if (!ddr0_used && !ddr1_used) { 41361bd2f75SYork Sun printf("Invalid configuration in HN-F SAM control\n"); 41461bd2f75SYork Sun return; 41561bd2f75SYork Sun } 41661bd2f75SYork Sun 41761bd2f75SYork Sun if (!ddr0_used && info->first_ctrl == 0) { 41861bd2f75SYork Sun info->first_ctrl = 1; 41961bd2f75SYork Sun info->num_ctrls = 1; 42061bd2f75SYork Sun debug("First DDR controller disabled\n"); 42161bd2f75SYork Sun return; 42261bd2f75SYork Sun } 42361bd2f75SYork Sun 42461bd2f75SYork Sun if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) { 42561bd2f75SYork Sun info->num_ctrls = 1; 42661bd2f75SYork Sun debug("Second DDR controller disabled\n"); 42761bd2f75SYork Sun } 42861bd2f75SYork Sun #endif 42961bd2f75SYork Sun } 430