1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2008, 2010-2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP Semiconductor 5 */ 6 7 #include <common.h> 8 #include <hwconfig.h> 9 #include <fsl_ddr_sdram.h> 10 11 #include <fsl_ddr.h> 12 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ 13 defined(CONFIG_ARM) 14 #include <asm/arch/clock.h> 15 #endif 16 17 /* 18 * Use our own stack based buffer before relocation to allow accessing longer 19 * hwconfig strings that might be in the environment before we've relocated. 20 * This is pretty fragile on both the use of stack and if the buffer is big 21 * enough. However we will get a warning from env_get_f() for the latter. 22 */ 23 24 /* Board-specific functions defined in each board's ddr.c */ 25 extern void fsl_ddr_board_options(memctl_options_t *popts, 26 dimm_params_t *pdimm, 27 unsigned int ctrl_num); 28 29 struct dynamic_odt { 30 unsigned int odt_rd_cfg; 31 unsigned int odt_wr_cfg; 32 unsigned int odt_rtt_norm; 33 unsigned int odt_rtt_wr; 34 }; 35 36 #ifdef CONFIG_SYS_FSL_DDR4 37 /* Quad rank is not verified yet due availability. 38 * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option 39 */ 40 static __maybe_unused const struct dynamic_odt single_Q[4] = { 41 { /* cs0 */ 42 FSL_DDR_ODT_NEVER, 43 FSL_DDR_ODT_CS_AND_OTHER_DIMM, 44 DDR4_RTT_34_OHM, /* unverified */ 45 DDR4_RTT_120_OHM 46 }, 47 { /* cs1 */ 48 FSL_DDR_ODT_NEVER, 49 FSL_DDR_ODT_NEVER, 50 DDR4_RTT_OFF, 51 DDR4_RTT_120_OHM 52 }, 53 { /* cs2 */ 54 FSL_DDR_ODT_NEVER, 55 FSL_DDR_ODT_CS_AND_OTHER_DIMM, 56 DDR4_RTT_34_OHM, 57 DDR4_RTT_120_OHM 58 }, 59 { /* cs3 */ 60 FSL_DDR_ODT_NEVER, 61 FSL_DDR_ODT_NEVER, /* tied high */ 62 DDR4_RTT_OFF, 63 DDR4_RTT_120_OHM 64 } 65 }; 66 67 static __maybe_unused const struct dynamic_odt single_D[4] = { 68 { /* cs0 */ 69 FSL_DDR_ODT_NEVER, 70 FSL_DDR_ODT_ALL, 71 DDR4_RTT_40_OHM, 72 DDR4_RTT_OFF 73 }, 74 { /* cs1 */ 75 FSL_DDR_ODT_NEVER, 76 FSL_DDR_ODT_NEVER, 77 DDR4_RTT_OFF, 78 DDR4_RTT_OFF 79 }, 80 {0, 0, 0, 0}, 81 {0, 0, 0, 0} 82 }; 83 84 static __maybe_unused const struct dynamic_odt single_S[4] = { 85 { /* cs0 */ 86 FSL_DDR_ODT_NEVER, 87 FSL_DDR_ODT_ALL, 88 DDR4_RTT_40_OHM, 89 DDR4_RTT_OFF 90 }, 91 {0, 0, 0, 0}, 92 {0, 0, 0, 0}, 93 {0, 0, 0, 0}, 94 }; 95 96 static __maybe_unused const struct dynamic_odt dual_DD[4] = { 97 { /* cs0 */ 98 FSL_DDR_ODT_NEVER, 99 FSL_DDR_ODT_SAME_DIMM, 100 DDR4_RTT_120_OHM, 101 DDR4_RTT_OFF 102 }, 103 { /* cs1 */ 104 FSL_DDR_ODT_OTHER_DIMM, 105 FSL_DDR_ODT_OTHER_DIMM, 106 DDR4_RTT_34_OHM, 107 DDR4_RTT_OFF 108 }, 109 { /* cs2 */ 110 FSL_DDR_ODT_NEVER, 111 FSL_DDR_ODT_SAME_DIMM, 112 DDR4_RTT_120_OHM, 113 DDR4_RTT_OFF 114 }, 115 { /* cs3 */ 116 FSL_DDR_ODT_OTHER_DIMM, 117 FSL_DDR_ODT_OTHER_DIMM, 118 DDR4_RTT_34_OHM, 119 DDR4_RTT_OFF 120 } 121 }; 122 123 static __maybe_unused const struct dynamic_odt dual_DS[4] = { 124 { /* cs0 */ 125 FSL_DDR_ODT_NEVER, 126 FSL_DDR_ODT_SAME_DIMM, 127 DDR4_RTT_120_OHM, 128 DDR4_RTT_OFF 129 }, 130 { /* cs1 */ 131 FSL_DDR_ODT_OTHER_DIMM, 132 FSL_DDR_ODT_OTHER_DIMM, 133 DDR4_RTT_34_OHM, 134 DDR4_RTT_OFF 135 }, 136 { /* cs2 */ 137 FSL_DDR_ODT_OTHER_DIMM, 138 FSL_DDR_ODT_ALL, 139 DDR4_RTT_34_OHM, 140 DDR4_RTT_120_OHM 141 }, 142 {0, 0, 0, 0} 143 }; 144 static __maybe_unused const struct dynamic_odt dual_SD[4] = { 145 { /* cs0 */ 146 FSL_DDR_ODT_OTHER_DIMM, 147 FSL_DDR_ODT_ALL, 148 DDR4_RTT_34_OHM, 149 DDR4_RTT_120_OHM 150 }, 151 {0, 0, 0, 0}, 152 { /* cs2 */ 153 FSL_DDR_ODT_NEVER, 154 FSL_DDR_ODT_SAME_DIMM, 155 DDR4_RTT_120_OHM, 156 DDR4_RTT_OFF 157 }, 158 { /* cs3 */ 159 FSL_DDR_ODT_OTHER_DIMM, 160 FSL_DDR_ODT_OTHER_DIMM, 161 DDR4_RTT_34_OHM, 162 DDR4_RTT_OFF 163 } 164 }; 165 166 static __maybe_unused const struct dynamic_odt dual_SS[4] = { 167 { /* cs0 */ 168 FSL_DDR_ODT_OTHER_DIMM, 169 FSL_DDR_ODT_ALL, 170 DDR4_RTT_34_OHM, 171 DDR4_RTT_120_OHM 172 }, 173 {0, 0, 0, 0}, 174 { /* cs2 */ 175 FSL_DDR_ODT_OTHER_DIMM, 176 FSL_DDR_ODT_ALL, 177 DDR4_RTT_34_OHM, 178 DDR4_RTT_120_OHM 179 }, 180 {0, 0, 0, 0} 181 }; 182 183 static __maybe_unused const struct dynamic_odt dual_D0[4] = { 184 { /* cs0 */ 185 FSL_DDR_ODT_NEVER, 186 FSL_DDR_ODT_SAME_DIMM, 187 DDR4_RTT_40_OHM, 188 DDR4_RTT_OFF 189 }, 190 { /* cs1 */ 191 FSL_DDR_ODT_NEVER, 192 FSL_DDR_ODT_NEVER, 193 DDR4_RTT_OFF, 194 DDR4_RTT_OFF 195 }, 196 {0, 0, 0, 0}, 197 {0, 0, 0, 0} 198 }; 199 200 static __maybe_unused const struct dynamic_odt dual_0D[4] = { 201 {0, 0, 0, 0}, 202 {0, 0, 0, 0}, 203 { /* cs2 */ 204 FSL_DDR_ODT_NEVER, 205 FSL_DDR_ODT_SAME_DIMM, 206 DDR4_RTT_40_OHM, 207 DDR4_RTT_OFF 208 }, 209 { /* cs3 */ 210 FSL_DDR_ODT_NEVER, 211 FSL_DDR_ODT_NEVER, 212 DDR4_RTT_OFF, 213 DDR4_RTT_OFF 214 } 215 }; 216 217 static __maybe_unused const struct dynamic_odt dual_S0[4] = { 218 { /* cs0 */ 219 FSL_DDR_ODT_NEVER, 220 FSL_DDR_ODT_CS, 221 DDR4_RTT_40_OHM, 222 DDR4_RTT_OFF 223 }, 224 {0, 0, 0, 0}, 225 {0, 0, 0, 0}, 226 {0, 0, 0, 0} 227 228 }; 229 230 static __maybe_unused const struct dynamic_odt dual_0S[4] = { 231 {0, 0, 0, 0}, 232 {0, 0, 0, 0}, 233 { /* cs2 */ 234 FSL_DDR_ODT_NEVER, 235 FSL_DDR_ODT_CS, 236 DDR4_RTT_40_OHM, 237 DDR4_RTT_OFF 238 }, 239 {0, 0, 0, 0} 240 241 }; 242 243 static __maybe_unused const struct dynamic_odt odt_unknown[4] = { 244 { /* cs0 */ 245 FSL_DDR_ODT_NEVER, 246 FSL_DDR_ODT_CS, 247 DDR4_RTT_120_OHM, 248 DDR4_RTT_OFF 249 }, 250 { /* cs1 */ 251 FSL_DDR_ODT_NEVER, 252 FSL_DDR_ODT_CS, 253 DDR4_RTT_120_OHM, 254 DDR4_RTT_OFF 255 }, 256 { /* cs2 */ 257 FSL_DDR_ODT_NEVER, 258 FSL_DDR_ODT_CS, 259 DDR4_RTT_120_OHM, 260 DDR4_RTT_OFF 261 }, 262 { /* cs3 */ 263 FSL_DDR_ODT_NEVER, 264 FSL_DDR_ODT_CS, 265 DDR4_RTT_120_OHM, 266 DDR4_RTT_OFF 267 } 268 }; 269 #elif defined(CONFIG_SYS_FSL_DDR3) 270 static __maybe_unused const struct dynamic_odt single_Q[4] = { 271 { /* cs0 */ 272 FSL_DDR_ODT_NEVER, 273 FSL_DDR_ODT_CS_AND_OTHER_DIMM, 274 DDR3_RTT_20_OHM, 275 DDR3_RTT_120_OHM 276 }, 277 { /* cs1 */ 278 FSL_DDR_ODT_NEVER, 279 FSL_DDR_ODT_NEVER, /* tied high */ 280 DDR3_RTT_OFF, 281 DDR3_RTT_120_OHM 282 }, 283 { /* cs2 */ 284 FSL_DDR_ODT_NEVER, 285 FSL_DDR_ODT_CS_AND_OTHER_DIMM, 286 DDR3_RTT_20_OHM, 287 DDR3_RTT_120_OHM 288 }, 289 { /* cs3 */ 290 FSL_DDR_ODT_NEVER, 291 FSL_DDR_ODT_NEVER, /* tied high */ 292 DDR3_RTT_OFF, 293 DDR3_RTT_120_OHM 294 } 295 }; 296 297 static __maybe_unused const struct dynamic_odt single_D[4] = { 298 { /* cs0 */ 299 FSL_DDR_ODT_NEVER, 300 FSL_DDR_ODT_ALL, 301 DDR3_RTT_40_OHM, 302 DDR3_RTT_OFF 303 }, 304 { /* cs1 */ 305 FSL_DDR_ODT_NEVER, 306 FSL_DDR_ODT_NEVER, 307 DDR3_RTT_OFF, 308 DDR3_RTT_OFF 309 }, 310 {0, 0, 0, 0}, 311 {0, 0, 0, 0} 312 }; 313 314 static __maybe_unused const struct dynamic_odt single_S[4] = { 315 { /* cs0 */ 316 FSL_DDR_ODT_NEVER, 317 FSL_DDR_ODT_ALL, 318 DDR3_RTT_40_OHM, 319 DDR3_RTT_OFF 320 }, 321 {0, 0, 0, 0}, 322 {0, 0, 0, 0}, 323 {0, 0, 0, 0}, 324 }; 325 326 static __maybe_unused const struct dynamic_odt dual_DD[4] = { 327 { /* cs0 */ 328 FSL_DDR_ODT_NEVER, 329 FSL_DDR_ODT_SAME_DIMM, 330 DDR3_RTT_120_OHM, 331 DDR3_RTT_OFF 332 }, 333 { /* cs1 */ 334 FSL_DDR_ODT_OTHER_DIMM, 335 FSL_DDR_ODT_OTHER_DIMM, 336 DDR3_RTT_30_OHM, 337 DDR3_RTT_OFF 338 }, 339 { /* cs2 */ 340 FSL_DDR_ODT_NEVER, 341 FSL_DDR_ODT_SAME_DIMM, 342 DDR3_RTT_120_OHM, 343 DDR3_RTT_OFF 344 }, 345 { /* cs3 */ 346 FSL_DDR_ODT_OTHER_DIMM, 347 FSL_DDR_ODT_OTHER_DIMM, 348 DDR3_RTT_30_OHM, 349 DDR3_RTT_OFF 350 } 351 }; 352 353 static __maybe_unused const struct dynamic_odt dual_DS[4] = { 354 { /* cs0 */ 355 FSL_DDR_ODT_NEVER, 356 FSL_DDR_ODT_SAME_DIMM, 357 DDR3_RTT_120_OHM, 358 DDR3_RTT_OFF 359 }, 360 { /* cs1 */ 361 FSL_DDR_ODT_OTHER_DIMM, 362 FSL_DDR_ODT_OTHER_DIMM, 363 DDR3_RTT_30_OHM, 364 DDR3_RTT_OFF 365 }, 366 { /* cs2 */ 367 FSL_DDR_ODT_OTHER_DIMM, 368 FSL_DDR_ODT_ALL, 369 DDR3_RTT_20_OHM, 370 DDR3_RTT_120_OHM 371 }, 372 {0, 0, 0, 0} 373 }; 374 static __maybe_unused const struct dynamic_odt dual_SD[4] = { 375 { /* cs0 */ 376 FSL_DDR_ODT_OTHER_DIMM, 377 FSL_DDR_ODT_ALL, 378 DDR3_RTT_20_OHM, 379 DDR3_RTT_120_OHM 380 }, 381 {0, 0, 0, 0}, 382 { /* cs2 */ 383 FSL_DDR_ODT_NEVER, 384 FSL_DDR_ODT_SAME_DIMM, 385 DDR3_RTT_120_OHM, 386 DDR3_RTT_OFF 387 }, 388 { /* cs3 */ 389 FSL_DDR_ODT_OTHER_DIMM, 390 FSL_DDR_ODT_OTHER_DIMM, 391 DDR3_RTT_20_OHM, 392 DDR3_RTT_OFF 393 } 394 }; 395 396 static __maybe_unused const struct dynamic_odt dual_SS[4] = { 397 { /* cs0 */ 398 FSL_DDR_ODT_OTHER_DIMM, 399 FSL_DDR_ODT_ALL, 400 DDR3_RTT_30_OHM, 401 DDR3_RTT_120_OHM 402 }, 403 {0, 0, 0, 0}, 404 { /* cs2 */ 405 FSL_DDR_ODT_OTHER_DIMM, 406 FSL_DDR_ODT_ALL, 407 DDR3_RTT_30_OHM, 408 DDR3_RTT_120_OHM 409 }, 410 {0, 0, 0, 0} 411 }; 412 413 static __maybe_unused const struct dynamic_odt dual_D0[4] = { 414 { /* cs0 */ 415 FSL_DDR_ODT_NEVER, 416 FSL_DDR_ODT_SAME_DIMM, 417 DDR3_RTT_40_OHM, 418 DDR3_RTT_OFF 419 }, 420 { /* cs1 */ 421 FSL_DDR_ODT_NEVER, 422 FSL_DDR_ODT_NEVER, 423 DDR3_RTT_OFF, 424 DDR3_RTT_OFF 425 }, 426 {0, 0, 0, 0}, 427 {0, 0, 0, 0} 428 }; 429 430 static __maybe_unused const struct dynamic_odt dual_0D[4] = { 431 {0, 0, 0, 0}, 432 {0, 0, 0, 0}, 433 { /* cs2 */ 434 FSL_DDR_ODT_NEVER, 435 FSL_DDR_ODT_SAME_DIMM, 436 DDR3_RTT_40_OHM, 437 DDR3_RTT_OFF 438 }, 439 { /* cs3 */ 440 FSL_DDR_ODT_NEVER, 441 FSL_DDR_ODT_NEVER, 442 DDR3_RTT_OFF, 443 DDR3_RTT_OFF 444 } 445 }; 446 447 static __maybe_unused const struct dynamic_odt dual_S0[4] = { 448 { /* cs0 */ 449 FSL_DDR_ODT_NEVER, 450 FSL_DDR_ODT_CS, 451 DDR3_RTT_40_OHM, 452 DDR3_RTT_OFF 453 }, 454 {0, 0, 0, 0}, 455 {0, 0, 0, 0}, 456 {0, 0, 0, 0} 457 458 }; 459 460 static __maybe_unused const struct dynamic_odt dual_0S[4] = { 461 {0, 0, 0, 0}, 462 {0, 0, 0, 0}, 463 { /* cs2 */ 464 FSL_DDR_ODT_NEVER, 465 FSL_DDR_ODT_CS, 466 DDR3_RTT_40_OHM, 467 DDR3_RTT_OFF 468 }, 469 {0, 0, 0, 0} 470 471 }; 472 473 static __maybe_unused const struct dynamic_odt odt_unknown[4] = { 474 { /* cs0 */ 475 FSL_DDR_ODT_NEVER, 476 FSL_DDR_ODT_CS, 477 DDR3_RTT_120_OHM, 478 DDR3_RTT_OFF 479 }, 480 { /* cs1 */ 481 FSL_DDR_ODT_NEVER, 482 FSL_DDR_ODT_CS, 483 DDR3_RTT_120_OHM, 484 DDR3_RTT_OFF 485 }, 486 { /* cs2 */ 487 FSL_DDR_ODT_NEVER, 488 FSL_DDR_ODT_CS, 489 DDR3_RTT_120_OHM, 490 DDR3_RTT_OFF 491 }, 492 { /* cs3 */ 493 FSL_DDR_ODT_NEVER, 494 FSL_DDR_ODT_CS, 495 DDR3_RTT_120_OHM, 496 DDR3_RTT_OFF 497 } 498 }; 499 #else /* CONFIG_SYS_FSL_DDR3 */ 500 static __maybe_unused const struct dynamic_odt single_Q[4] = { 501 {0, 0, 0, 0}, 502 {0, 0, 0, 0}, 503 {0, 0, 0, 0}, 504 {0, 0, 0, 0} 505 }; 506 507 static __maybe_unused const struct dynamic_odt single_D[4] = { 508 { /* cs0 */ 509 FSL_DDR_ODT_NEVER, 510 FSL_DDR_ODT_ALL, 511 DDR2_RTT_150_OHM, 512 DDR2_RTT_OFF 513 }, 514 { /* cs1 */ 515 FSL_DDR_ODT_NEVER, 516 FSL_DDR_ODT_NEVER, 517 DDR2_RTT_OFF, 518 DDR2_RTT_OFF 519 }, 520 {0, 0, 0, 0}, 521 {0, 0, 0, 0} 522 }; 523 524 static __maybe_unused const struct dynamic_odt single_S[4] = { 525 { /* cs0 */ 526 FSL_DDR_ODT_NEVER, 527 FSL_DDR_ODT_ALL, 528 DDR2_RTT_150_OHM, 529 DDR2_RTT_OFF 530 }, 531 {0, 0, 0, 0}, 532 {0, 0, 0, 0}, 533 {0, 0, 0, 0}, 534 }; 535 536 static __maybe_unused const struct dynamic_odt dual_DD[4] = { 537 { /* cs0 */ 538 FSL_DDR_ODT_OTHER_DIMM, 539 FSL_DDR_ODT_OTHER_DIMM, 540 DDR2_RTT_75_OHM, 541 DDR2_RTT_OFF 542 }, 543 { /* cs1 */ 544 FSL_DDR_ODT_NEVER, 545 FSL_DDR_ODT_NEVER, 546 DDR2_RTT_OFF, 547 DDR2_RTT_OFF 548 }, 549 { /* cs2 */ 550 FSL_DDR_ODT_OTHER_DIMM, 551 FSL_DDR_ODT_OTHER_DIMM, 552 DDR2_RTT_75_OHM, 553 DDR2_RTT_OFF 554 }, 555 { /* cs3 */ 556 FSL_DDR_ODT_NEVER, 557 FSL_DDR_ODT_NEVER, 558 DDR2_RTT_OFF, 559 DDR2_RTT_OFF 560 } 561 }; 562 563 static __maybe_unused const struct dynamic_odt dual_DS[4] = { 564 { /* cs0 */ 565 FSL_DDR_ODT_OTHER_DIMM, 566 FSL_DDR_ODT_OTHER_DIMM, 567 DDR2_RTT_75_OHM, 568 DDR2_RTT_OFF 569 }, 570 { /* cs1 */ 571 FSL_DDR_ODT_NEVER, 572 FSL_DDR_ODT_NEVER, 573 DDR2_RTT_OFF, 574 DDR2_RTT_OFF 575 }, 576 { /* cs2 */ 577 FSL_DDR_ODT_OTHER_DIMM, 578 FSL_DDR_ODT_OTHER_DIMM, 579 DDR2_RTT_75_OHM, 580 DDR2_RTT_OFF 581 }, 582 {0, 0, 0, 0} 583 }; 584 585 static __maybe_unused const struct dynamic_odt dual_SD[4] = { 586 { /* cs0 */ 587 FSL_DDR_ODT_OTHER_DIMM, 588 FSL_DDR_ODT_OTHER_DIMM, 589 DDR2_RTT_75_OHM, 590 DDR2_RTT_OFF 591 }, 592 {0, 0, 0, 0}, 593 { /* cs2 */ 594 FSL_DDR_ODT_OTHER_DIMM, 595 FSL_DDR_ODT_OTHER_DIMM, 596 DDR2_RTT_75_OHM, 597 DDR2_RTT_OFF 598 }, 599 { /* cs3 */ 600 FSL_DDR_ODT_NEVER, 601 FSL_DDR_ODT_NEVER, 602 DDR2_RTT_OFF, 603 DDR2_RTT_OFF 604 } 605 }; 606 607 static __maybe_unused const struct dynamic_odt dual_SS[4] = { 608 { /* cs0 */ 609 FSL_DDR_ODT_OTHER_DIMM, 610 FSL_DDR_ODT_OTHER_DIMM, 611 DDR2_RTT_75_OHM, 612 DDR2_RTT_OFF 613 }, 614 {0, 0, 0, 0}, 615 { /* cs2 */ 616 FSL_DDR_ODT_OTHER_DIMM, 617 FSL_DDR_ODT_OTHER_DIMM, 618 DDR2_RTT_75_OHM, 619 DDR2_RTT_OFF 620 }, 621 {0, 0, 0, 0} 622 }; 623 624 static __maybe_unused const struct dynamic_odt dual_D0[4] = { 625 { /* cs0 */ 626 FSL_DDR_ODT_NEVER, 627 FSL_DDR_ODT_ALL, 628 DDR2_RTT_150_OHM, 629 DDR2_RTT_OFF 630 }, 631 { /* cs1 */ 632 FSL_DDR_ODT_NEVER, 633 FSL_DDR_ODT_NEVER, 634 DDR2_RTT_OFF, 635 DDR2_RTT_OFF 636 }, 637 {0, 0, 0, 0}, 638 {0, 0, 0, 0} 639 }; 640 641 static __maybe_unused const struct dynamic_odt dual_0D[4] = { 642 {0, 0, 0, 0}, 643 {0, 0, 0, 0}, 644 { /* cs2 */ 645 FSL_DDR_ODT_NEVER, 646 FSL_DDR_ODT_ALL, 647 DDR2_RTT_150_OHM, 648 DDR2_RTT_OFF 649 }, 650 { /* cs3 */ 651 FSL_DDR_ODT_NEVER, 652 FSL_DDR_ODT_NEVER, 653 DDR2_RTT_OFF, 654 DDR2_RTT_OFF 655 } 656 }; 657 658 static __maybe_unused const struct dynamic_odt dual_S0[4] = { 659 { /* cs0 */ 660 FSL_DDR_ODT_NEVER, 661 FSL_DDR_ODT_CS, 662 DDR2_RTT_150_OHM, 663 DDR2_RTT_OFF 664 }, 665 {0, 0, 0, 0}, 666 {0, 0, 0, 0}, 667 {0, 0, 0, 0} 668 669 }; 670 671 static __maybe_unused const struct dynamic_odt dual_0S[4] = { 672 {0, 0, 0, 0}, 673 {0, 0, 0, 0}, 674 { /* cs2 */ 675 FSL_DDR_ODT_NEVER, 676 FSL_DDR_ODT_CS, 677 DDR2_RTT_150_OHM, 678 DDR2_RTT_OFF 679 }, 680 {0, 0, 0, 0} 681 682 }; 683 684 static __maybe_unused const struct dynamic_odt odt_unknown[4] = { 685 { /* cs0 */ 686 FSL_DDR_ODT_NEVER, 687 FSL_DDR_ODT_CS, 688 DDR2_RTT_75_OHM, 689 DDR2_RTT_OFF 690 }, 691 { /* cs1 */ 692 FSL_DDR_ODT_NEVER, 693 FSL_DDR_ODT_NEVER, 694 DDR2_RTT_OFF, 695 DDR2_RTT_OFF 696 }, 697 { /* cs2 */ 698 FSL_DDR_ODT_NEVER, 699 FSL_DDR_ODT_CS, 700 DDR2_RTT_75_OHM, 701 DDR2_RTT_OFF 702 }, 703 { /* cs3 */ 704 FSL_DDR_ODT_NEVER, 705 FSL_DDR_ODT_NEVER, 706 DDR2_RTT_OFF, 707 DDR2_RTT_OFF 708 } 709 }; 710 #endif 711 712 /* 713 * Automatically seleect bank interleaving mode based on DIMMs 714 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null. 715 * This function only deal with one or two slots per controller. 716 */ 717 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm) 718 { 719 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 720 if (pdimm[0].n_ranks == 4) 721 return FSL_DDR_CS0_CS1_CS2_CS3; 722 else if (pdimm[0].n_ranks == 2) 723 return FSL_DDR_CS0_CS1; 724 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 725 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 726 if (pdimm[0].n_ranks == 4) 727 return FSL_DDR_CS0_CS1_CS2_CS3; 728 #endif 729 if (pdimm[0].n_ranks == 2) { 730 if (pdimm[1].n_ranks == 2) 731 return FSL_DDR_CS0_CS1_CS2_CS3; 732 else 733 return FSL_DDR_CS0_CS1; 734 } 735 #endif 736 return 0; 737 } 738 739 unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, 740 memctl_options_t *popts, 741 dimm_params_t *pdimm, 742 unsigned int ctrl_num) 743 { 744 unsigned int i; 745 char buf[HWCONFIG_BUFFER_SIZE]; 746 #if defined(CONFIG_SYS_FSL_DDR3) || \ 747 defined(CONFIG_SYS_FSL_DDR2) || \ 748 defined(CONFIG_SYS_FSL_DDR4) 749 const struct dynamic_odt *pdodt = odt_unknown; 750 #endif 751 #if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) 752 ulong ddr_freq; 753 #endif 754 755 /* 756 * Extract hwconfig from environment since we have not properly setup 757 * the environment but need it for ddr config params 758 */ 759 if (env_get_f("hwconfig", buf, sizeof(buf)) < 0) 760 buf[0] = '\0'; 761 762 #if defined(CONFIG_SYS_FSL_DDR3) || \ 763 defined(CONFIG_SYS_FSL_DDR2) || \ 764 defined(CONFIG_SYS_FSL_DDR4) 765 /* Chip select options. */ 766 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 767 switch (pdimm[0].n_ranks) { 768 case 1: 769 pdodt = single_S; 770 break; 771 case 2: 772 pdodt = single_D; 773 break; 774 case 4: 775 pdodt = single_Q; 776 break; 777 } 778 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 779 switch (pdimm[0].n_ranks) { 780 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 781 case 4: 782 pdodt = single_Q; 783 if (pdimm[1].n_ranks) 784 printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n"); 785 break; 786 #endif 787 case 2: 788 switch (pdimm[1].n_ranks) { 789 case 2: 790 pdodt = dual_DD; 791 break; 792 case 1: 793 pdodt = dual_DS; 794 break; 795 case 0: 796 pdodt = dual_D0; 797 break; 798 } 799 break; 800 case 1: 801 switch (pdimm[1].n_ranks) { 802 case 2: 803 pdodt = dual_SD; 804 break; 805 case 1: 806 pdodt = dual_SS; 807 break; 808 case 0: 809 pdodt = dual_S0; 810 break; 811 } 812 break; 813 case 0: 814 switch (pdimm[1].n_ranks) { 815 case 2: 816 pdodt = dual_0D; 817 break; 818 case 1: 819 pdodt = dual_0S; 820 break; 821 } 822 break; 823 } 824 #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */ 825 #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */ 826 827 /* Pick chip-select local options. */ 828 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 829 #if defined(CONFIG_SYS_FSL_DDR3) || \ 830 defined(CONFIG_SYS_FSL_DDR2) || \ 831 defined(CONFIG_SYS_FSL_DDR4) 832 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; 833 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; 834 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; 835 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr; 836 #else 837 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 838 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 839 #endif 840 popts->cs_local_opts[i].auto_precharge = 0; 841 } 842 843 /* Pick interleaving mode. */ 844 845 /* 846 * 0 = no interleaving 847 * 1 = interleaving between 2 controllers 848 */ 849 popts->memctl_interleaving = 0; 850 851 /* 852 * 0 = cacheline 853 * 1 = page 854 * 2 = (logical) bank 855 * 3 = superbank (only if CS interleaving is enabled) 856 */ 857 popts->memctl_interleaving_mode = 0; 858 859 /* 860 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl 861 * 1: page: bit to the left of the column bits selects the memctl 862 * 2: bank: bit to the left of the bank bits selects the memctl 863 * 3: superbank: bit to the left of the chip select selects the memctl 864 * 865 * NOTE: ba_intlv (rank interleaving) is independent of memory 866 * controller interleaving; it is only within a memory controller. 867 * Must use superbank interleaving if rank interleaving is used and 868 * memory controller interleaving is enabled. 869 */ 870 871 /* 872 * 0 = no 873 * 0x40 = CS0,CS1 874 * 0x20 = CS2,CS3 875 * 0x60 = CS0,CS1 + CS2,CS3 876 * 0x04 = CS0,CS1,CS2,CS3 877 */ 878 popts->ba_intlv_ctl = 0; 879 880 /* Memory Organization Parameters */ 881 popts->registered_dimm_en = common_dimm->all_dimms_registered; 882 883 /* Operational Mode Paramters */ 884 885 /* Pick ECC modes */ 886 popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */ 887 #ifdef CONFIG_DDR_ECC 888 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) { 889 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf)) 890 popts->ecc_mode = 1; 891 } else 892 popts->ecc_mode = 1; 893 #endif 894 /* 1 = use memory controler to init data */ 895 popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0; 896 897 /* 898 * Choose DQS config 899 * 0 for DDR1 900 * 1 for DDR2 901 */ 902 #if defined(CONFIG_SYS_FSL_DDR1) 903 popts->dqs_config = 0; 904 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) 905 popts->dqs_config = 1; 906 #endif 907 908 /* Choose self-refresh during sleep. */ 909 popts->self_refresh_in_sleep = 1; 910 911 /* Choose dynamic power management mode. */ 912 popts->dynamic_power = 0; 913 914 /* 915 * check first dimm for primary sdram width 916 * presuming all dimms are similar 917 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit 918 */ 919 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 920 if (pdimm[0].n_ranks != 0) { 921 if ((pdimm[0].data_width >= 64) && \ 922 (pdimm[0].data_width <= 72)) 923 popts->data_bus_width = 0; 924 else if ((pdimm[0].data_width >= 32) && \ 925 (pdimm[0].data_width <= 40)) 926 popts->data_bus_width = 1; 927 else { 928 panic("Error: data width %u is invalid!\n", 929 pdimm[0].data_width); 930 } 931 } 932 #else 933 if (pdimm[0].n_ranks != 0) { 934 if (pdimm[0].primary_sdram_width == 64) 935 popts->data_bus_width = 0; 936 else if (pdimm[0].primary_sdram_width == 32) 937 popts->data_bus_width = 1; 938 else if (pdimm[0].primary_sdram_width == 16) 939 popts->data_bus_width = 2; 940 else { 941 panic("Error: primary sdram width %u is invalid!\n", 942 pdimm[0].primary_sdram_width); 943 } 944 } 945 #endif 946 947 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0; 948 949 /* Choose burst length. */ 950 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 951 #if defined(CONFIG_E500MC) 952 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */ 953 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ 954 #else 955 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { 956 /* 32-bit or 16-bit bus */ 957 popts->otf_burst_chop_en = 0; 958 popts->burst_length = DDR_BL8; 959 } else { 960 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */ 961 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ 962 } 963 #endif 964 #else 965 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ 966 #endif 967 968 /* Choose ddr controller address mirror mode */ 969 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 970 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 971 if (pdimm[i].n_ranks) { 972 popts->mirrored_dimm = pdimm[i].mirrored_dimm; 973 break; 974 } 975 } 976 #endif 977 978 /* Global Timing Parameters. */ 979 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num)); 980 981 /* Pick a caslat override. */ 982 popts->cas_latency_override = 0; 983 popts->cas_latency_override_value = 3; 984 if (popts->cas_latency_override) { 985 debug("using caslat override value = %u\n", 986 popts->cas_latency_override_value); 987 } 988 989 /* Decide whether to use the computed derated latency */ 990 popts->use_derated_caslat = 0; 991 992 /* Choose an additive latency. */ 993 popts->additive_latency_override = 0; 994 popts->additive_latency_override_value = 3; 995 if (popts->additive_latency_override) { 996 debug("using additive latency override value = %u\n", 997 popts->additive_latency_override_value); 998 } 999 1000 /* 1001 * 2T_EN setting 1002 * 1003 * Factors to consider for 2T_EN: 1004 * - number of DIMMs installed 1005 * - number of components, number of active ranks 1006 * - how much time you want to spend playing around 1007 */ 1008 popts->twot_en = 0; 1009 popts->threet_en = 0; 1010 1011 /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */ 1012 if (popts->registered_dimm_en) 1013 popts->ap_en = 1; /* 0 = disable, 1 = enable */ 1014 else 1015 popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */ 1016 1017 if (hwconfig_sub_f("fsl_ddr", "parity", buf)) { 1018 if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) { 1019 if (popts->registered_dimm_en || 1020 (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4)) 1021 popts->ap_en = 1; 1022 } 1023 } 1024 1025 /* 1026 * BSTTOPRE precharge interval 1027 * 1028 * Set this to 0 for global auto precharge 1029 * The value of 0x100 has been used for DDR1, DDR2, DDR3. 1030 * It is not wrong. Any value should be OK. The performance depends on 1031 * applications. There is no one good value for all. One way to set 1032 * is to use 1/4 of refint value. 1033 */ 1034 popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps) 1035 >> 2; 1036 1037 /* 1038 * Window for four activates -- tFAW 1039 * 1040 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only 1041 * FIXME: varies depending upon number of column addresses or data 1042 * FIXME: width, was considering looking at pdimm->primary_sdram_width 1043 */ 1044 #if defined(CONFIG_SYS_FSL_DDR1) 1045 popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1); 1046 1047 #elif defined(CONFIG_SYS_FSL_DDR2) 1048 /* 1049 * x4/x8; some datasheets have 35000 1050 * x16 wide columns only? Use 50000? 1051 */ 1052 popts->tfaw_window_four_activates_ps = 37500; 1053 1054 #else 1055 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps; 1056 #endif 1057 popts->zq_en = 0; 1058 popts->wrlvl_en = 0; 1059 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 1060 /* 1061 * due to ddr3 dimm is fly-by topology 1062 * we suggest to enable write leveling to 1063 * meet the tQDSS under different loading. 1064 */ 1065 popts->wrlvl_en = 1; 1066 popts->zq_en = 1; 1067 popts->wrlvl_override = 0; 1068 #endif 1069 1070 /* 1071 * Check interleaving configuration from environment. 1072 * Please refer to doc/README.fsl-ddr for the detail. 1073 * 1074 * If memory controller interleaving is enabled, then the data 1075 * bus widths must be programmed identically for all memory controllers. 1076 * 1077 * Attempt to set all controllers to the same chip select 1078 * interleaving mode. It will do a best effort to get the 1079 * requested ranks interleaved together such that the result 1080 * should be a subset of the requested configuration. 1081 * 1082 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving 1083 * with 256 Byte is enabled. 1084 */ 1085 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1) 1086 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) 1087 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B 1088 ; 1089 #else 1090 goto done; 1091 #endif 1092 if (pdimm[0].n_ranks == 0) { 1093 printf("There is no rank on CS0 for controller %d.\n", ctrl_num); 1094 popts->memctl_interleaving = 0; 1095 goto done; 1096 } 1097 popts->memctl_interleaving = 1; 1098 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B 1099 popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING; 1100 popts->memctl_interleaving = 1; 1101 debug("256 Byte interleaving\n"); 1102 #else 1103 /* 1104 * test null first. if CONFIG_HWCONFIG is not defined 1105 * hwconfig_arg_cmp returns non-zero 1106 */ 1107 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", 1108 "null", buf)) { 1109 popts->memctl_interleaving = 0; 1110 debug("memory controller interleaving disabled.\n"); 1111 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 1112 "ctlr_intlv", 1113 "cacheline", buf)) { 1114 popts->memctl_interleaving_mode = 1115 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 1116 0 : FSL_DDR_CACHE_LINE_INTERLEAVING; 1117 popts->memctl_interleaving = 1118 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 1119 0 : 1; 1120 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 1121 "ctlr_intlv", 1122 "page", buf)) { 1123 popts->memctl_interleaving_mode = 1124 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 1125 0 : FSL_DDR_PAGE_INTERLEAVING; 1126 popts->memctl_interleaving = 1127 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 1128 0 : 1; 1129 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 1130 "ctlr_intlv", 1131 "bank", buf)) { 1132 popts->memctl_interleaving_mode = 1133 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 1134 0 : FSL_DDR_BANK_INTERLEAVING; 1135 popts->memctl_interleaving = 1136 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 1137 0 : 1; 1138 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 1139 "ctlr_intlv", 1140 "superbank", buf)) { 1141 popts->memctl_interleaving_mode = 1142 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 1143 0 : FSL_DDR_SUPERBANK_INTERLEAVING; 1144 popts->memctl_interleaving = 1145 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 1146 0 : 1; 1147 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3) 1148 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 1149 "ctlr_intlv", 1150 "3way_1KB", buf)) { 1151 popts->memctl_interleaving_mode = 1152 FSL_DDR_3WAY_1KB_INTERLEAVING; 1153 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 1154 "ctlr_intlv", 1155 "3way_4KB", buf)) { 1156 popts->memctl_interleaving_mode = 1157 FSL_DDR_3WAY_4KB_INTERLEAVING; 1158 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 1159 "ctlr_intlv", 1160 "3way_8KB", buf)) { 1161 popts->memctl_interleaving_mode = 1162 FSL_DDR_3WAY_8KB_INTERLEAVING; 1163 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 4) 1164 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 1165 "ctlr_intlv", 1166 "4way_1KB", buf)) { 1167 popts->memctl_interleaving_mode = 1168 FSL_DDR_4WAY_1KB_INTERLEAVING; 1169 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 1170 "ctlr_intlv", 1171 "4way_4KB", buf)) { 1172 popts->memctl_interleaving_mode = 1173 FSL_DDR_4WAY_4KB_INTERLEAVING; 1174 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 1175 "ctlr_intlv", 1176 "4way_8KB", buf)) { 1177 popts->memctl_interleaving_mode = 1178 FSL_DDR_4WAY_8KB_INTERLEAVING; 1179 #endif 1180 } else { 1181 popts->memctl_interleaving = 0; 1182 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); 1183 } 1184 #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */ 1185 done: 1186 #endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */ 1187 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && 1188 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { 1189 /* test null first. if CONFIG_HWCONFIG is not defined, 1190 * hwconfig_subarg_cmp_f returns non-zero */ 1191 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 1192 "null", buf)) 1193 debug("bank interleaving disabled.\n"); 1194 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 1195 "cs0_cs1", buf)) 1196 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; 1197 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 1198 "cs2_cs3", buf)) 1199 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; 1200 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 1201 "cs0_cs1_and_cs2_cs3", buf)) 1202 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; 1203 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 1204 "cs0_cs1_cs2_cs3", buf)) 1205 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; 1206 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 1207 "auto", buf)) 1208 popts->ba_intlv_ctl = auto_bank_intlv(pdimm); 1209 else 1210 printf("hwconfig has unrecognized parameter for bank_intlv.\n"); 1211 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { 1212 case FSL_DDR_CS0_CS1_CS2_CS3: 1213 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 1214 if (pdimm[0].n_ranks < 4) { 1215 popts->ba_intlv_ctl = 0; 1216 printf("Not enough bank(chip-select) for " 1217 "CS0+CS1+CS2+CS3 on controller %d, " 1218 "interleaving disabled!\n", ctrl_num); 1219 } 1220 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 1221 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 1222 if (pdimm[0].n_ranks == 4) 1223 break; 1224 #endif 1225 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { 1226 popts->ba_intlv_ctl = 0; 1227 printf("Not enough bank(chip-select) for " 1228 "CS0+CS1+CS2+CS3 on controller %d, " 1229 "interleaving disabled!\n", ctrl_num); 1230 } 1231 if (pdimm[0].capacity != pdimm[1].capacity) { 1232 popts->ba_intlv_ctl = 0; 1233 printf("Not identical DIMM size for " 1234 "CS0+CS1+CS2+CS3 on controller %d, " 1235 "interleaving disabled!\n", ctrl_num); 1236 } 1237 #endif 1238 break; 1239 case FSL_DDR_CS0_CS1: 1240 if (pdimm[0].n_ranks < 2) { 1241 popts->ba_intlv_ctl = 0; 1242 printf("Not enough bank(chip-select) for " 1243 "CS0+CS1 on controller %d, " 1244 "interleaving disabled!\n", ctrl_num); 1245 } 1246 break; 1247 case FSL_DDR_CS2_CS3: 1248 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 1249 if (pdimm[0].n_ranks < 4) { 1250 popts->ba_intlv_ctl = 0; 1251 printf("Not enough bank(chip-select) for CS2+CS3 " 1252 "on controller %d, interleaving disabled!\n", ctrl_num); 1253 } 1254 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 1255 if (pdimm[1].n_ranks < 2) { 1256 popts->ba_intlv_ctl = 0; 1257 printf("Not enough bank(chip-select) for CS2+CS3 " 1258 "on controller %d, interleaving disabled!\n", ctrl_num); 1259 } 1260 #endif 1261 break; 1262 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 1263 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 1264 if (pdimm[0].n_ranks < 4) { 1265 popts->ba_intlv_ctl = 0; 1266 printf("Not enough bank(CS) for CS0+CS1 and " 1267 "CS2+CS3 on controller %d, " 1268 "interleaving disabled!\n", ctrl_num); 1269 } 1270 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 1271 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) { 1272 popts->ba_intlv_ctl = 0; 1273 printf("Not enough bank(CS) for CS0+CS1 and " 1274 "CS2+CS3 on controller %d, " 1275 "interleaving disabled!\n", ctrl_num); 1276 } 1277 #endif 1278 break; 1279 default: 1280 popts->ba_intlv_ctl = 0; 1281 break; 1282 } 1283 } 1284 1285 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) { 1286 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf)) 1287 popts->addr_hash = 0; 1288 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", 1289 "true", buf)) 1290 popts->addr_hash = 1; 1291 } 1292 1293 if (pdimm[0].n_ranks == 4) 1294 popts->quad_rank_present = 1; 1295 1296 popts->package_3ds = pdimm->package_3ds; 1297 1298 #if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) 1299 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; 1300 if (popts->registered_dimm_en) { 1301 popts->rcw_override = 1; 1302 popts->rcw_1 = 0x000a5a00; 1303 if (ddr_freq <= 800) 1304 popts->rcw_2 = 0x00000000; 1305 else if (ddr_freq <= 1066) 1306 popts->rcw_2 = 0x00100000; 1307 else if (ddr_freq <= 1333) 1308 popts->rcw_2 = 0x00200000; 1309 else 1310 popts->rcw_2 = 0x00300000; 1311 } 1312 #endif 1313 1314 fsl_ddr_board_options(popts, pdimm, ctrl_num); 1315 1316 return 0; 1317 } 1318 1319 void check_interleaving_options(fsl_ddr_info_t *pinfo) 1320 { 1321 int i, j, k, check_n_ranks, intlv_invalid = 0; 1322 unsigned int check_intlv, check_n_row_addr, check_n_col_addr; 1323 unsigned long long check_rank_density; 1324 struct dimm_params_s *dimm; 1325 int first_ctrl = pinfo->first_ctrl; 1326 int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; 1327 1328 /* 1329 * Check if all controllers are configured for memory 1330 * controller interleaving. Identical dimms are recommended. At least 1331 * the size, row and col address should be checked. 1332 */ 1333 j = 0; 1334 check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks; 1335 check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density; 1336 check_n_row_addr = pinfo->dimm_params[first_ctrl][0].n_row_addr; 1337 check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr; 1338 check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode; 1339 for (i = first_ctrl; i <= last_ctrl; i++) { 1340 dimm = &pinfo->dimm_params[i][0]; 1341 if (!pinfo->memctl_opts[i].memctl_interleaving) { 1342 continue; 1343 } else if (((check_rank_density != dimm->rank_density) || 1344 (check_n_ranks != dimm->n_ranks) || 1345 (check_n_row_addr != dimm->n_row_addr) || 1346 (check_n_col_addr != dimm->n_col_addr) || 1347 (check_intlv != 1348 pinfo->memctl_opts[i].memctl_interleaving_mode))){ 1349 intlv_invalid = 1; 1350 break; 1351 } else { 1352 j++; 1353 } 1354 1355 } 1356 if (intlv_invalid) { 1357 for (i = first_ctrl; i <= last_ctrl; i++) 1358 pinfo->memctl_opts[i].memctl_interleaving = 0; 1359 printf("Not all DIMMs are identical. " 1360 "Memory controller interleaving disabled.\n"); 1361 } else { 1362 switch (check_intlv) { 1363 case FSL_DDR_256B_INTERLEAVING: 1364 case FSL_DDR_CACHE_LINE_INTERLEAVING: 1365 case FSL_DDR_PAGE_INTERLEAVING: 1366 case FSL_DDR_BANK_INTERLEAVING: 1367 case FSL_DDR_SUPERBANK_INTERLEAVING: 1368 #if (3 == CONFIG_SYS_NUM_DDR_CTLRS) 1369 k = 2; 1370 #else 1371 k = CONFIG_SYS_NUM_DDR_CTLRS; 1372 #endif 1373 break; 1374 case FSL_DDR_3WAY_1KB_INTERLEAVING: 1375 case FSL_DDR_3WAY_4KB_INTERLEAVING: 1376 case FSL_DDR_3WAY_8KB_INTERLEAVING: 1377 case FSL_DDR_4WAY_1KB_INTERLEAVING: 1378 case FSL_DDR_4WAY_4KB_INTERLEAVING: 1379 case FSL_DDR_4WAY_8KB_INTERLEAVING: 1380 default: 1381 k = CONFIG_SYS_NUM_DDR_CTLRS; 1382 break; 1383 } 1384 debug("%d of %d controllers are interleaving.\n", j, k); 1385 if (j && (j != k)) { 1386 for (i = first_ctrl; i <= last_ctrl; i++) 1387 pinfo->memctl_opts[i].memctl_interleaving = 0; 1388 if ((last_ctrl - first_ctrl) > 1) 1389 puts("Not all controllers have compatible interleaving mode. All disabled.\n"); 1390 } 1391 } 1392 debug("Checking interleaving options completed\n"); 1393 } 1394 1395 int fsl_use_spd(void) 1396 { 1397 int use_spd = 0; 1398 1399 #ifdef CONFIG_DDR_SPD 1400 char buf[HWCONFIG_BUFFER_SIZE]; 1401 1402 /* 1403 * Extract hwconfig from environment since we have not properly setup 1404 * the environment but need it for ddr config params 1405 */ 1406 if (env_get_f("hwconfig", buf, sizeof(buf)) < 0) 1407 buf[0] = '\0'; 1408 1409 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ 1410 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) { 1411 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf)) 1412 use_spd = 1; 1413 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", 1414 "fixed", buf)) 1415 use_spd = 0; 1416 else 1417 use_spd = 1; 1418 } else 1419 use_spd = 1; 1420 #endif 1421 1422 return use_spd; 1423 } 1424