1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 11 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 12 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 13 #endif 14 15 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 16 unsigned int ctrl_num, int step) 17 { 18 unsigned int i; 19 struct ccsr_ddr __iomem *ddr; 20 21 switch (ctrl_num) { 22 case 0: 23 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 24 break; 25 case 1: 26 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 27 break; 28 default: 29 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 30 return; 31 } 32 33 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 34 if (i == 0) { 35 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); 36 out_be32(&ddr->cs0_config, regs->cs[i].config); 37 38 } else if (i == 1) { 39 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); 40 out_be32(&ddr->cs1_config, regs->cs[i].config); 41 42 } else if (i == 2) { 43 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); 44 out_be32(&ddr->cs2_config, regs->cs[i].config); 45 46 } else if (i == 3) { 47 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); 48 out_be32(&ddr->cs3_config, regs->cs[i].config); 49 } 50 } 51 52 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); 53 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); 54 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); 55 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); 56 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 57 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); 58 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 59 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 60 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); 61 out_be32(&ddr->sdram_data_init, regs->ddr_data_init); 62 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 63 out_be32(&ddr->init_addr, regs->ddr_init_addr); 64 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 65 66 debug("before go\n"); 67 68 /* 69 * 200 painful micro-seconds must elapse between 70 * the DDR clock setup and the DDR config enable. 71 */ 72 udelay(200); 73 asm volatile("sync;isync"); 74 75 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); 76 77 /* 78 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done 79 */ 80 while (in_be32(&ddr->sdram_cfg_2) & 0x10) { 81 udelay(10000); /* throttle polling rate */ 82 } 83 } 84