1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <fsl_ddr_sdram.h> 12 13 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 14 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 15 #endif 16 17 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 18 unsigned int ctrl_num, int step) 19 { 20 unsigned int i; 21 struct ccsr_ddr __iomem *ddr; 22 23 switch (ctrl_num) { 24 case 0: 25 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 26 break; 27 case 1: 28 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 29 break; 30 default: 31 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 32 return; 33 } 34 35 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 36 if (i == 0) { 37 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); 38 out_be32(&ddr->cs0_config, regs->cs[i].config); 39 40 } else if (i == 1) { 41 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); 42 out_be32(&ddr->cs1_config, regs->cs[i].config); 43 44 } else if (i == 2) { 45 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); 46 out_be32(&ddr->cs2_config, regs->cs[i].config); 47 48 } else if (i == 3) { 49 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); 50 out_be32(&ddr->cs3_config, regs->cs[i].config); 51 } 52 } 53 54 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); 55 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); 56 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); 57 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); 58 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 59 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); 60 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 61 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 62 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); 63 out_be32(&ddr->sdram_data_init, regs->ddr_data_init); 64 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 65 out_be32(&ddr->init_addr, regs->ddr_init_addr); 66 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 67 68 debug("before go\n"); 69 70 /* 71 * 200 painful micro-seconds must elapse between 72 * the DDR clock setup and the DDR config enable. 73 */ 74 udelay(200); 75 asm volatile("sync;isync"); 76 77 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); 78 79 /* 80 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done 81 */ 82 while (in_be32(&ddr->sdram_cfg_2) & 0x10) { 83 udelay(10000); /* throttle polling rate */ 84 } 85 } 86