1 /* 2 * Copyright 2008-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 12 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 13 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 14 #endif 15 16 /* 17 * regs has the to-be-set values for DDR controller registers 18 * ctrl_num is the DDR controller number 19 * step: 0 goes through the initialization in one pass 20 * 1 sets registers and returns before enabling controller 21 * 2 resumes from step 1 and continues to initialize 22 * Dividing the initialization to two steps to deassert DDR reset signal 23 * to comply with JEDEC specs for RDIMMs. 24 */ 25 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 26 unsigned int ctrl_num, int step) 27 { 28 unsigned int i, bus_width; 29 struct ccsr_ddr __iomem *ddr; 30 u32 temp_sdram_cfg; 31 u32 total_gb_size_per_controller; 32 int timeout; 33 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 34 int timeout_save; 35 volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; 36 unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; 37 int csn = -1; 38 #endif 39 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 40 u32 save1, save2; 41 #endif 42 43 switch (ctrl_num) { 44 case 0: 45 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 46 break; 47 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) 48 case 1: 49 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 50 break; 51 #endif 52 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) 53 case 2: 54 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 55 break; 56 #endif 57 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) 58 case 3: 59 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 60 break; 61 #endif 62 default: 63 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 64 return; 65 } 66 67 if (step == 2) 68 goto step2; 69 70 if (regs->ddr_eor) 71 out_be32(&ddr->eor, regs->ddr_eor); 72 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 73 debug("Workaround for ERRATUM_DDR111_DDR134\n"); 74 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 75 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; 76 cs_ea = regs->cs[i].bnds & 0xfff; 77 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) { 78 csn = i; 79 csn_bnds_backup = regs->cs[i].bnds; 80 csn_bnds_t = (unsigned int *) ®s->cs[i].bnds; 81 if (cs_ea > 0xeff) 82 *csn_bnds_t = regs->cs[i].bnds + 0x01000000; 83 else 84 *csn_bnds_t = regs->cs[i].bnds + 0x01000100; 85 debug("Found cs%d_bns (0x%08x) covering 0xff000000, " 86 "change it to 0x%x\n", 87 csn, csn_bnds_backup, regs->cs[i].bnds); 88 break; 89 } 90 } 91 #endif 92 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 93 if (i == 0) { 94 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); 95 out_be32(&ddr->cs0_config, regs->cs[i].config); 96 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); 97 98 } else if (i == 1) { 99 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); 100 out_be32(&ddr->cs1_config, regs->cs[i].config); 101 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); 102 103 } else if (i == 2) { 104 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); 105 out_be32(&ddr->cs2_config, regs->cs[i].config); 106 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); 107 108 } else if (i == 3) { 109 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); 110 out_be32(&ddr->cs3_config, regs->cs[i].config); 111 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); 112 } 113 } 114 115 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); 116 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); 117 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); 118 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); 119 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); 120 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 121 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 122 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 123 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 124 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 125 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 126 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 127 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 128 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); 129 out_be32(&ddr->sdram_data_init, regs->ddr_data_init); 130 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 131 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); 132 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); 133 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 134 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 135 #ifndef CONFIG_SYS_FSL_DDR_EMU 136 /* 137 * Skip these two registers if running on emulator 138 * because emulator doesn't have skew between bytes. 139 */ 140 141 if (regs->ddr_wrlvl_cntl_2) 142 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 143 if (regs->ddr_wrlvl_cntl_3) 144 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 145 #endif 146 147 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 148 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 149 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 150 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); 151 #ifdef CONFIG_DEEP_SLEEP 152 if (is_warm_boot()) { 153 out_be32(&ddr->sdram_cfg_2, 154 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 155 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 156 out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 157 158 /* DRAM VRef will not be trained */ 159 out_be32(&ddr->ddr_cdr2, 160 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 161 } else 162 #endif 163 { 164 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 165 out_be32(&ddr->init_addr, regs->ddr_init_addr); 166 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 167 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); 168 } 169 out_be32(&ddr->err_disable, regs->err_disable); 170 out_be32(&ddr->err_int_en, regs->err_int_en); 171 for (i = 0; i < 32; i++) { 172 if (regs->debug[i]) { 173 debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); 174 out_be32(&ddr->debug[i], regs->debug[i]); 175 } 176 } 177 178 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 179 out_be32(&ddr->debug[12], 0x00000015); 180 out_be32(&ddr->debug[21], 0x24000000); 181 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ 182 183 /* 184 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 185 * deasserted. Clocks start when any chip select is enabled and clock 186 * control register is set. Because all DDR components are connected to 187 * one reset signal, this needs to be done in two steps. Step 1 is to 188 * get the clocks started. Step 2 resumes after reset signal is 189 * deasserted. 190 */ 191 if (step == 1) { 192 udelay(200); 193 return; 194 } 195 196 step2: 197 /* Set, but do not enable the memory */ 198 temp_sdram_cfg = regs->ddr_sdram_cfg; 199 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 200 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); 201 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 202 debug("Workaround for ERRATUM_DDR_A003\n"); 203 if (regs->ddr_sdram_rcw_2 & 0x00f00000) { 204 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); 205 out_be32(&ddr->debug[2], 0x00000400); 206 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); 207 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); 208 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); 209 out_be32(&ddr->mtcr, 0); 210 save1 = in_be32(&ddr->debug[12]); 211 save2 = in_be32(&ddr->debug[21]); 212 out_be32(&ddr->debug[12], 0x00000015); 213 out_be32(&ddr->debug[21], 0x24000000); 214 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); 215 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); 216 217 asm volatile("sync;isync"); 218 while (!(in_be32(&ddr->debug[1]) & 0x2)) 219 ; 220 221 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { 222 case 0x00000000: 223 out_be32(&ddr->sdram_md_cntl, 224 MD_CNTL_MD_EN | 225 MD_CNTL_CS_SEL_CS0_CS1 | 226 0x04000000 | 227 MD_CNTL_WRCW | 228 MD_CNTL_MD_VALUE(0x02)); 229 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 230 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) 231 break; 232 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) 233 ; 234 out_be32(&ddr->sdram_md_cntl, 235 MD_CNTL_MD_EN | 236 MD_CNTL_CS_SEL_CS2_CS3 | 237 0x04000000 | 238 MD_CNTL_WRCW | 239 MD_CNTL_MD_VALUE(0x02)); 240 #endif 241 break; 242 case 0x00100000: 243 out_be32(&ddr->sdram_md_cntl, 244 MD_CNTL_MD_EN | 245 MD_CNTL_CS_SEL_CS0_CS1 | 246 0x04000000 | 247 MD_CNTL_WRCW | 248 MD_CNTL_MD_VALUE(0x0a)); 249 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 250 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) 251 break; 252 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) 253 ; 254 out_be32(&ddr->sdram_md_cntl, 255 MD_CNTL_MD_EN | 256 MD_CNTL_CS_SEL_CS2_CS3 | 257 0x04000000 | 258 MD_CNTL_WRCW | 259 MD_CNTL_MD_VALUE(0x0a)); 260 #endif 261 break; 262 case 0x00200000: 263 out_be32(&ddr->sdram_md_cntl, 264 MD_CNTL_MD_EN | 265 MD_CNTL_CS_SEL_CS0_CS1 | 266 0x04000000 | 267 MD_CNTL_WRCW | 268 MD_CNTL_MD_VALUE(0x12)); 269 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 270 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) 271 break; 272 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) 273 ; 274 out_be32(&ddr->sdram_md_cntl, 275 MD_CNTL_MD_EN | 276 MD_CNTL_CS_SEL_CS2_CS3 | 277 0x04000000 | 278 MD_CNTL_WRCW | 279 MD_CNTL_MD_VALUE(0x12)); 280 #endif 281 break; 282 case 0x00300000: 283 out_be32(&ddr->sdram_md_cntl, 284 MD_CNTL_MD_EN | 285 MD_CNTL_CS_SEL_CS0_CS1 | 286 0x04000000 | 287 MD_CNTL_WRCW | 288 MD_CNTL_MD_VALUE(0x1a)); 289 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 290 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) 291 break; 292 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) 293 ; 294 out_be32(&ddr->sdram_md_cntl, 295 MD_CNTL_MD_EN | 296 MD_CNTL_CS_SEL_CS2_CS3 | 297 0x04000000 | 298 MD_CNTL_WRCW | 299 MD_CNTL_MD_VALUE(0x1a)); 300 #endif 301 break; 302 default: 303 out_be32(&ddr->sdram_md_cntl, 304 MD_CNTL_MD_EN | 305 MD_CNTL_CS_SEL_CS0_CS1 | 306 0x04000000 | 307 MD_CNTL_WRCW | 308 MD_CNTL_MD_VALUE(0x02)); 309 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 310 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) 311 break; 312 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) 313 ; 314 out_be32(&ddr->sdram_md_cntl, 315 MD_CNTL_MD_EN | 316 MD_CNTL_CS_SEL_CS2_CS3 | 317 0x04000000 | 318 MD_CNTL_WRCW | 319 MD_CNTL_MD_VALUE(0x02)); 320 #endif 321 printf("Unsupported RC10\n"); 322 break; 323 } 324 325 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) 326 ; 327 udelay(6); 328 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); 329 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); 330 out_be32(&ddr->debug[2], 0x0); 331 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 332 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 333 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 334 out_be32(&ddr->debug[12], save1); 335 out_be32(&ddr->debug[21], save2); 336 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); 337 338 } 339 #endif 340 /* 341 * For 8572 DDR1 erratum - DDR controller may enter illegal state 342 * when operatiing in 32-bit bus mode with 4-beat bursts, 343 * This erratum does not affect DDR3 mode, only for DDR2 mode. 344 */ 345 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 346 debug("Workaround for ERRATUM_DDR_115\n"); 347 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) 348 && in_be32(&ddr->sdram_cfg) & 0x80000) { 349 /* set DEBUG_1[31] */ 350 setbits_be32(&ddr->debug[0], 1); 351 } 352 #endif 353 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 354 debug("Workaround for ERRATUM_DDR111_DDR134\n"); 355 /* 356 * This is the combined workaround for DDR111 and DDR134 357 * following the published errata for MPC8572 358 */ 359 360 /* 1. Set EEBACR[3] */ 361 setbits_be32(&ecm->eebacr, 0x10000000); 362 debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); 363 364 /* 2. Set DINIT in SDRAM_CFG_2*/ 365 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); 366 debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", 367 in_be32(&ddr->sdram_cfg_2)); 368 369 /* 3. Set DEBUG_3[21] */ 370 setbits_be32(&ddr->debug[2], 0x400); 371 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); 372 373 #endif /* part 1 of the workaound */ 374 375 /* 376 * 500 painful micro-seconds must elapse between 377 * the DDR clock setup and the DDR config enable. 378 * DDR2 need 200 us, and DDR3 need 500 us from spec, 379 * we choose the max, that is 500 us for all of case. 380 */ 381 udelay(500); 382 asm volatile("sync;isync"); 383 384 #ifdef CONFIG_DEEP_SLEEP 385 if (is_warm_boot()) { 386 /* enter self-refresh */ 387 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); 388 /* do board specific memory setup */ 389 board_mem_sleep_setup(); 390 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 391 } else 392 #endif 393 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI); 394 395 /* Let the controller go */ 396 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 397 asm volatile("sync;isync"); 398 399 total_gb_size_per_controller = 0; 400 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 401 if (!(regs->cs[i].config & 0x80000000)) 402 continue; 403 total_gb_size_per_controller += 1 << ( 404 ((regs->cs[i].config >> 14) & 0x3) + 2 + 405 ((regs->cs[i].config >> 8) & 0x7) + 12 + 406 ((regs->cs[i].config >> 0) & 0x7) + 8 + 407 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 408 26); /* minus 26 (count of 64M) */ 409 } 410 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 411 total_gb_size_per_controller *= 3; 412 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 413 total_gb_size_per_controller <<= 1; 414 /* 415 * total memory / bus width = transactions needed 416 * transactions needed / data rate = seconds 417 * to add plenty of buffer, double the time 418 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 419 * Let's wait for 800ms 420 */ 421 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) 422 >> SDRAM_CFG_DBW_SHIFT); 423 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 424 (get_ddr_freq(ctrl_num) >> 20)) << 1; 425 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 426 timeout_save = timeout; 427 #endif 428 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 429 debug("total %d GB\n", total_gb_size_per_controller); 430 debug("Need to wait up to %d * 10ms\n", timeout); 431 432 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 433 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 434 (timeout >= 0)) { 435 udelay(10000); /* throttle polling rate */ 436 timeout--; 437 } 438 439 if (timeout <= 0) 440 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 441 442 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 443 /* continue this workaround */ 444 445 /* 4. Clear DEBUG3[21] */ 446 clrbits_be32(&ddr->debug[2], 0x400); 447 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); 448 449 /* DDR134 workaround starts */ 450 /* A: Clear sdram_cfg_2[odt_cfg] */ 451 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); 452 debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", 453 in_be32(&ddr->sdram_cfg_2)); 454 455 /* B: Set DEBUG1[15] */ 456 setbits_be32(&ddr->debug[0], 0x10000); 457 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); 458 459 /* C: Set timing_cfg_2[cpo] to 0b11111 */ 460 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); 461 debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", 462 in_be32(&ddr->timing_cfg_2)); 463 464 /* D: Set D6 to 0x9f9f9f9f */ 465 out_be32(&ddr->debug[5], 0x9f9f9f9f); 466 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); 467 468 /* E: Set D7 to 0x9f9f9f9f */ 469 out_be32(&ddr->debug[6], 0x9f9f9f9f); 470 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); 471 472 /* F: Set D2[20] */ 473 setbits_be32(&ddr->debug[1], 0x800); 474 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); 475 476 /* G: Poll on D2[20] until cleared */ 477 while (in_be32(&ddr->debug[1]) & 0x800) 478 udelay(10000); /* throttle polling rate */ 479 480 /* H: Clear D1[15] */ 481 clrbits_be32(&ddr->debug[0], 0x10000); 482 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); 483 484 /* I: Set sdram_cfg_2[odt_cfg] */ 485 setbits_be32(&ddr->sdram_cfg_2, 486 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); 487 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); 488 489 /* Continuing with the DDR111 workaround */ 490 /* 5. Set D2[21] */ 491 setbits_be32(&ddr->debug[1], 0x400); 492 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); 493 494 /* 6. Poll D2[21] until its cleared */ 495 while (in_be32(&ddr->debug[1]) & 0x400) 496 udelay(10000); /* throttle polling rate */ 497 498 /* 7. Wait for state machine 2nd run, roughly 400ms/GB */ 499 debug("Wait for %d * 10ms\n", timeout_save); 500 udelay(timeout_save * 10000); 501 502 /* 8. Set sdram_cfg_2[dinit] if options requires */ 503 setbits_be32(&ddr->sdram_cfg_2, 504 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT); 505 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); 506 507 /* 9. Poll until dinit is cleared */ 508 timeout = timeout_save; 509 debug("Need to wait up to %d * 10ms\n", timeout); 510 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 511 (timeout >= 0)) { 512 udelay(10000); /* throttle polling rate */ 513 timeout--; 514 } 515 516 if (timeout <= 0) 517 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 518 519 /* 10. Clear EEBACR[3] */ 520 clrbits_be32(&ecm->eebacr, 10000000); 521 debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); 522 523 if (csn != -1) { 524 csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds; 525 *csn_bnds_t = csn_bnds_backup; 526 debug("Change cs%d_bnds back to 0x%08x\n", 527 csn, regs->cs[csn].bnds); 528 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ 529 switch (csn) { 530 case 0: 531 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); 532 break; 533 case 1: 534 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); 535 break; 536 #if CONFIG_CHIP_SELECTS_PER_CTRL > 2 537 case 2: 538 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); 539 break; 540 case 3: 541 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); 542 break; 543 #endif 544 } 545 clrbits_be32(&ddr->sdram_cfg, 0x2); 546 } 547 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ 548 #ifdef CONFIG_DEEP_SLEEP 549 if (is_warm_boot()) 550 /* exit self-refresh */ 551 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); 552 #endif 553 } 554