1 /* 2 * Copyright 2008-2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <fsl_ddr_sdram.h> 12 #include <asm/processor.h> 13 14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 16 #endif 17 18 19 /* 20 * regs has the to-be-set values for DDR controller registers 21 * ctrl_num is the DDR controller number 22 * step: 0 goes through the initialization in one pass 23 * 1 sets registers and returns before enabling controller 24 * 2 resumes from step 1 and continues to initialize 25 * Dividing the initialization to two steps to deassert DDR reset signal 26 * to comply with JEDEC specs for RDIMMs. 27 */ 28 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 29 unsigned int ctrl_num, int step) 30 { 31 unsigned int i, bus_width; 32 volatile ccsr_ddr_t *ddr; 33 u32 temp_sdram_cfg; 34 u32 total_gb_size_per_controller; 35 int timeout; 36 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 37 int timeout_save; 38 volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; 39 unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; 40 int csn = -1; 41 #endif 42 43 switch (ctrl_num) { 44 case 0: 45 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 46 break; 47 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 48 case 1: 49 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 50 break; 51 #endif 52 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 53 case 2: 54 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 55 break; 56 #endif 57 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 58 case 3: 59 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 60 break; 61 #endif 62 default: 63 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 64 return; 65 } 66 67 if (step == 2) 68 goto step2; 69 70 if (regs->ddr_eor) 71 out_be32(&ddr->eor, regs->ddr_eor); 72 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 73 debug("Workaround for ERRATUM_DDR111_DDR134\n"); 74 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 75 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; 76 cs_ea = regs->cs[i].bnds & 0xfff; 77 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) { 78 csn = i; 79 csn_bnds_backup = regs->cs[i].bnds; 80 csn_bnds_t = (unsigned int *) ®s->cs[i].bnds; 81 if (cs_ea > 0xeff) 82 *csn_bnds_t = regs->cs[i].bnds + 0x01000000; 83 else 84 *csn_bnds_t = regs->cs[i].bnds + 0x01000100; 85 debug("Found cs%d_bns (0x%08x) covering 0xff000000, " 86 "change it to 0x%x\n", 87 csn, csn_bnds_backup, regs->cs[i].bnds); 88 break; 89 } 90 } 91 #endif 92 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 93 if (i == 0) { 94 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); 95 out_be32(&ddr->cs0_config, regs->cs[i].config); 96 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); 97 98 } else if (i == 1) { 99 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); 100 out_be32(&ddr->cs1_config, regs->cs[i].config); 101 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); 102 103 } else if (i == 2) { 104 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); 105 out_be32(&ddr->cs2_config, regs->cs[i].config); 106 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); 107 108 } else if (i == 3) { 109 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); 110 out_be32(&ddr->cs3_config, regs->cs[i].config); 111 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); 112 } 113 } 114 115 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); 116 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); 117 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); 118 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); 119 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 120 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); 121 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 122 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 123 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 124 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 125 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 126 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 127 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 128 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 129 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); 130 out_be32(&ddr->sdram_data_init, regs->ddr_data_init); 131 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 132 out_be32(&ddr->init_addr, regs->ddr_init_addr); 133 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 134 135 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); 136 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); 137 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 138 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 139 #ifndef CONFIG_SYS_FSL_DDR_EMU 140 /* 141 * Skip these two registers if running on emulator 142 * because emulator doesn't have skew between bytes. 143 */ 144 145 if (regs->ddr_wrlvl_cntl_2) 146 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 147 if (regs->ddr_wrlvl_cntl_3) 148 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 149 #endif 150 151 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 152 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 153 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 154 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); 155 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); 156 out_be32(&ddr->err_disable, regs->err_disable); 157 out_be32(&ddr->err_int_en, regs->err_int_en); 158 for (i = 0; i < 32; i++) { 159 if (regs->debug[i]) { 160 debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); 161 out_be32(&ddr->debug[i], regs->debug[i]); 162 } 163 } 164 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 165 out_be32(&ddr->debug[28], 0x30003000); 166 #endif 167 168 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 169 out_be32(&ddr->debug[12], 0x00000015); 170 out_be32(&ddr->debug[21], 0x24000000); 171 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ 172 173 /* 174 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 175 * deasserted. Clocks start when any chip select is enabled and clock 176 * control register is set. Because all DDR components are connected to 177 * one reset signal, this needs to be done in two steps. Step 1 is to 178 * get the clocks started. Step 2 resumes after reset signal is 179 * deasserted. 180 */ 181 if (step == 1) { 182 udelay(200); 183 return; 184 } 185 186 step2: 187 /* Set, but do not enable the memory */ 188 temp_sdram_cfg = regs->ddr_sdram_cfg; 189 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 190 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); 191 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 192 debug("Workaround for ERRATUM_DDR_A003\n"); 193 if (regs->ddr_sdram_rcw_2 & 0x00f00000) { 194 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); 195 out_be32(&ddr->debug[2], 0x00000400); 196 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); 197 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); 198 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); 199 out_be32(&ddr->mtcr, 0); 200 out_be32(&ddr->debug[12], 0x00000015); 201 out_be32(&ddr->debug[21], 0x24000000); 202 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); 203 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); 204 205 asm volatile("sync;isync"); 206 while (!(in_be32(&ddr->debug[1]) & 0x2)) 207 ; 208 209 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { 210 case 0x00000000: 211 out_be32(&ddr->sdram_md_cntl, 212 MD_CNTL_MD_EN | 213 MD_CNTL_CS_SEL_CS0_CS1 | 214 0x04000000 | 215 MD_CNTL_WRCW | 216 MD_CNTL_MD_VALUE(0x02)); 217 break; 218 case 0x00100000: 219 out_be32(&ddr->sdram_md_cntl, 220 MD_CNTL_MD_EN | 221 MD_CNTL_CS_SEL_CS0_CS1 | 222 0x04000000 | 223 MD_CNTL_WRCW | 224 MD_CNTL_MD_VALUE(0x0a)); 225 break; 226 case 0x00200000: 227 out_be32(&ddr->sdram_md_cntl, 228 MD_CNTL_MD_EN | 229 MD_CNTL_CS_SEL_CS0_CS1 | 230 0x04000000 | 231 MD_CNTL_WRCW | 232 MD_CNTL_MD_VALUE(0x12)); 233 break; 234 case 0x00300000: 235 out_be32(&ddr->sdram_md_cntl, 236 MD_CNTL_MD_EN | 237 MD_CNTL_CS_SEL_CS0_CS1 | 238 0x04000000 | 239 MD_CNTL_WRCW | 240 MD_CNTL_MD_VALUE(0x1a)); 241 break; 242 default: 243 out_be32(&ddr->sdram_md_cntl, 244 MD_CNTL_MD_EN | 245 MD_CNTL_CS_SEL_CS0_CS1 | 246 0x04000000 | 247 MD_CNTL_WRCW | 248 MD_CNTL_MD_VALUE(0x02)); 249 printf("Unsupported RC10\n"); 250 break; 251 } 252 253 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) 254 ; 255 udelay(6); 256 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); 257 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); 258 out_be32(&ddr->debug[2], 0x0); 259 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 260 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 261 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 262 out_be32(&ddr->debug[12], 0x0); 263 out_be32(&ddr->debug[21], 0x0); 264 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); 265 266 } 267 #endif 268 /* 269 * For 8572 DDR1 erratum - DDR controller may enter illegal state 270 * when operatiing in 32-bit bus mode with 4-beat bursts, 271 * This erratum does not affect DDR3 mode, only for DDR2 mode. 272 */ 273 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 274 debug("Workaround for ERRATUM_DDR_115\n"); 275 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) 276 && in_be32(&ddr->sdram_cfg) & 0x80000) { 277 /* set DEBUG_1[31] */ 278 setbits_be32(&ddr->debug[0], 1); 279 } 280 #endif 281 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 282 debug("Workaround for ERRATUM_DDR111_DDR134\n"); 283 /* 284 * This is the combined workaround for DDR111 and DDR134 285 * following the published errata for MPC8572 286 */ 287 288 /* 1. Set EEBACR[3] */ 289 setbits_be32(&ecm->eebacr, 0x10000000); 290 debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); 291 292 /* 2. Set DINIT in SDRAM_CFG_2*/ 293 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); 294 debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", 295 in_be32(&ddr->sdram_cfg_2)); 296 297 /* 3. Set DEBUG_3[21] */ 298 setbits_be32(&ddr->debug[2], 0x400); 299 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); 300 301 #endif /* part 1 of the workaound */ 302 303 /* 304 * 500 painful micro-seconds must elapse between 305 * the DDR clock setup and the DDR config enable. 306 * DDR2 need 200 us, and DDR3 need 500 us from spec, 307 * we choose the max, that is 500 us for all of case. 308 */ 309 udelay(500); 310 asm volatile("sync;isync"); 311 312 /* Let the controller go */ 313 temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 314 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 315 asm volatile("sync;isync"); 316 317 total_gb_size_per_controller = 0; 318 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 319 if (!(regs->cs[i].config & 0x80000000)) 320 continue; 321 total_gb_size_per_controller += 1 << ( 322 ((regs->cs[i].config >> 14) & 0x3) + 2 + 323 ((regs->cs[i].config >> 8) & 0x7) + 12 + 324 ((regs->cs[i].config >> 0) & 0x7) + 8 + 325 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 326 26); /* minus 26 (count of 64M) */ 327 } 328 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 329 total_gb_size_per_controller *= 3; 330 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 331 total_gb_size_per_controller <<= 1; 332 /* 333 * total memory / bus width = transactions needed 334 * transactions needed / data rate = seconds 335 * to add plenty of buffer, double the time 336 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 337 * Let's wait for 800ms 338 */ 339 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) 340 >> SDRAM_CFG_DBW_SHIFT); 341 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 342 (get_ddr_freq(0) >> 20)) << 1; 343 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 344 timeout_save = timeout; 345 #endif 346 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 347 debug("total %d GB\n", total_gb_size_per_controller); 348 debug("Need to wait up to %d * 10ms\n", timeout); 349 350 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 351 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 352 (timeout >= 0)) { 353 udelay(10000); /* throttle polling rate */ 354 timeout--; 355 } 356 357 if (timeout <= 0) 358 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 359 360 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 361 /* continue this workaround */ 362 363 /* 4. Clear DEBUG3[21] */ 364 clrbits_be32(&ddr->debug[2], 0x400); 365 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); 366 367 /* DDR134 workaround starts */ 368 /* A: Clear sdram_cfg_2[odt_cfg] */ 369 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); 370 debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", 371 in_be32(&ddr->sdram_cfg_2)); 372 373 /* B: Set DEBUG1[15] */ 374 setbits_be32(&ddr->debug[0], 0x10000); 375 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); 376 377 /* C: Set timing_cfg_2[cpo] to 0b11111 */ 378 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); 379 debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", 380 in_be32(&ddr->timing_cfg_2)); 381 382 /* D: Set D6 to 0x9f9f9f9f */ 383 out_be32(&ddr->debug[5], 0x9f9f9f9f); 384 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); 385 386 /* E: Set D7 to 0x9f9f9f9f */ 387 out_be32(&ddr->debug[6], 0x9f9f9f9f); 388 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); 389 390 /* F: Set D2[20] */ 391 setbits_be32(&ddr->debug[1], 0x800); 392 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); 393 394 /* G: Poll on D2[20] until cleared */ 395 while (in_be32(&ddr->debug[1]) & 0x800) 396 udelay(10000); /* throttle polling rate */ 397 398 /* H: Clear D1[15] */ 399 clrbits_be32(&ddr->debug[0], 0x10000); 400 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); 401 402 /* I: Set sdram_cfg_2[odt_cfg] */ 403 setbits_be32(&ddr->sdram_cfg_2, 404 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); 405 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); 406 407 /* Continuing with the DDR111 workaround */ 408 /* 5. Set D2[21] */ 409 setbits_be32(&ddr->debug[1], 0x400); 410 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); 411 412 /* 6. Poll D2[21] until its cleared */ 413 while (in_be32(&ddr->debug[1]) & 0x400) 414 udelay(10000); /* throttle polling rate */ 415 416 /* 7. Wait for state machine 2nd run, roughly 400ms/GB */ 417 debug("Wait for %d * 10ms\n", timeout_save); 418 udelay(timeout_save * 10000); 419 420 /* 8. Set sdram_cfg_2[dinit] if options requires */ 421 setbits_be32(&ddr->sdram_cfg_2, 422 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT); 423 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); 424 425 /* 9. Poll until dinit is cleared */ 426 timeout = timeout_save; 427 debug("Need to wait up to %d * 10ms\n", timeout); 428 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 429 (timeout >= 0)) { 430 udelay(10000); /* throttle polling rate */ 431 timeout--; 432 } 433 434 if (timeout <= 0) 435 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 436 437 /* 10. Clear EEBACR[3] */ 438 clrbits_be32(&ecm->eebacr, 10000000); 439 debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); 440 441 if (csn != -1) { 442 csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds; 443 *csn_bnds_t = csn_bnds_backup; 444 debug("Change cs%d_bnds back to 0x%08x\n", 445 csn, regs->cs[csn].bnds); 446 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ 447 switch (csn) { 448 case 0: 449 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); 450 break; 451 case 1: 452 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); 453 break; 454 case 2: 455 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); 456 break; 457 case 3: 458 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); 459 break; 460 } 461 clrbits_be32(&ddr->sdram_cfg, 0x2); 462 } 463 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ 464 } 465