1 /*
2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8 
9 #include <common.h>
10 #include <asm/io.h>
11 #include <fsl_ddr_sdram.h>
12 #include <asm/processor.h>
13 
14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
16 #endif
17 
18 /*
19  * regs has the to-be-set values for DDR controller registers
20  * ctrl_num is the DDR controller number
21  * step: 0 goes through the initialization in one pass
22  *       1 sets registers and returns before enabling controller
23  *       2 resumes from step 1 and continues to initialize
24  * Dividing the initialization to two steps to deassert DDR reset signal
25  * to comply with JEDEC specs for RDIMMs.
26  */
27 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
28 			     unsigned int ctrl_num, int step)
29 {
30 	unsigned int i, bus_width;
31 	struct ccsr_ddr __iomem *ddr;
32 	u32 temp_sdram_cfg;
33 	u32 total_gb_size_per_controller;
34 	int timeout;
35 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
36 	int timeout_save;
37 	volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
38 	unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
39 	int csn = -1;
40 #endif
41 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
42 	u32 save1, save2;
43 #endif
44 
45 	switch (ctrl_num) {
46 	case 0:
47 		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
48 		break;
49 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
50 	case 1:
51 		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
52 		break;
53 #endif
54 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
55 	case 2:
56 		ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
57 		break;
58 #endif
59 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
60 	case 3:
61 		ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
62 		break;
63 #endif
64 	default:
65 		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
66 		return;
67 	}
68 
69 	if (step == 2)
70 		goto step2;
71 
72 	if (regs->ddr_eor)
73 		out_be32(&ddr->eor, regs->ddr_eor);
74 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
75 	debug("Workaround for ERRATUM_DDR111_DDR134\n");
76 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
77 		cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
78 		cs_ea = regs->cs[i].bnds & 0xfff;
79 		if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
80 			csn = i;
81 			csn_bnds_backup = regs->cs[i].bnds;
82 			csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
83 			if (cs_ea > 0xeff)
84 				*csn_bnds_t = regs->cs[i].bnds + 0x01000000;
85 			else
86 				*csn_bnds_t = regs->cs[i].bnds + 0x01000100;
87 			debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
88 				"change it to 0x%x\n",
89 				csn, csn_bnds_backup, regs->cs[i].bnds);
90 			break;
91 		}
92 	}
93 #endif
94 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
95 		if (i == 0) {
96 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
97 			out_be32(&ddr->cs0_config, regs->cs[i].config);
98 			out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
99 
100 		} else if (i == 1) {
101 			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
102 			out_be32(&ddr->cs1_config, regs->cs[i].config);
103 			out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
104 
105 		} else if (i == 2) {
106 			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
107 			out_be32(&ddr->cs2_config, regs->cs[i].config);
108 			out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
109 
110 		} else if (i == 3) {
111 			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
112 			out_be32(&ddr->cs3_config, regs->cs[i].config);
113 			out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
114 		}
115 	}
116 
117 	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
118 	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
119 	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
120 	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
121 	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
122 	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
123 	out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
124 	out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
125 	out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
126 	out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
127 	out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
128 	out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
129 	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
130 	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
131 	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
132 	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
133 	out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
134 	out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
135 	out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
136 	out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
137 #ifndef CONFIG_SYS_FSL_DDR_EMU
138 	/*
139 	 * Skip these two registers if running on emulator
140 	 * because emulator doesn't have skew between bytes.
141 	 */
142 
143 	if (regs->ddr_wrlvl_cntl_2)
144 		out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
145 	if (regs->ddr_wrlvl_cntl_3)
146 		out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
147 #endif
148 
149 	out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
150 	out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
151 	out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
152 	out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
153 #ifdef CONFIG_DEEP_SLEEP
154 	if (is_warm_boot()) {
155 		out_be32(&ddr->sdram_cfg_2,
156 			 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
157 		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
158 		out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
159 
160 		/* DRAM VRef will not be trained */
161 		out_be32(&ddr->ddr_cdr2,
162 			 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
163 	} else
164 #endif
165 	{
166 		out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
167 		out_be32(&ddr->init_addr, regs->ddr_init_addr);
168 		out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
169 		out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
170 	}
171 	out_be32(&ddr->err_disable, regs->err_disable);
172 	out_be32(&ddr->err_int_en, regs->err_int_en);
173 	for (i = 0; i < 32; i++) {
174 		if (regs->debug[i]) {
175 			debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
176 			out_be32(&ddr->debug[i], regs->debug[i]);
177 		}
178 	}
179 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
180 	out_be32(&ddr->debug[28], 0x30003000);
181 #endif
182 
183 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
184 	out_be32(&ddr->debug[12], 0x00000015);
185 	out_be32(&ddr->debug[21], 0x24000000);
186 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
187 
188 	/*
189 	 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
190 	 * deasserted. Clocks start when any chip select is enabled and clock
191 	 * control register is set. Because all DDR components are connected to
192 	 * one reset signal, this needs to be done in two steps. Step 1 is to
193 	 * get the clocks started. Step 2 resumes after reset signal is
194 	 * deasserted.
195 	 */
196 	if (step == 1) {
197 		udelay(200);
198 		return;
199 	}
200 
201 step2:
202 	/* Set, but do not enable the memory */
203 	temp_sdram_cfg = regs->ddr_sdram_cfg;
204 	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
205 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
206 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
207 	debug("Workaround for ERRATUM_DDR_A003\n");
208 	if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
209 		out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
210 		out_be32(&ddr->debug[2], 0x00000400);
211 		out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
212 		out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
213 		out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
214 		out_be32(&ddr->mtcr, 0);
215 		save1 = in_be32(&ddr->debug[12]);
216 		save2 = in_be32(&ddr->debug[21]);
217 		out_be32(&ddr->debug[12], 0x00000015);
218 		out_be32(&ddr->debug[21], 0x24000000);
219 		out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
220 		out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
221 
222 		asm volatile("sync;isync");
223 		while (!(in_be32(&ddr->debug[1]) & 0x2))
224 			;
225 
226 		switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
227 		case 0x00000000:
228 			out_be32(&ddr->sdram_md_cntl,
229 				MD_CNTL_MD_EN		|
230 				MD_CNTL_CS_SEL_CS0_CS1	|
231 				0x04000000		|
232 				MD_CNTL_WRCW		|
233 				MD_CNTL_MD_VALUE(0x02));
234 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
235 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
236 				break;
237 			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
238 				;
239 			out_be32(&ddr->sdram_md_cntl,
240 				 MD_CNTL_MD_EN		|
241 				 MD_CNTL_CS_SEL_CS2_CS3	|
242 				 0x04000000		|
243 				 MD_CNTL_WRCW		|
244 				 MD_CNTL_MD_VALUE(0x02));
245 #endif
246 			break;
247 		case 0x00100000:
248 			out_be32(&ddr->sdram_md_cntl,
249 				MD_CNTL_MD_EN		|
250 				MD_CNTL_CS_SEL_CS0_CS1	|
251 				0x04000000		|
252 				MD_CNTL_WRCW		|
253 				MD_CNTL_MD_VALUE(0x0a));
254 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
255 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
256 				break;
257 			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
258 				;
259 			out_be32(&ddr->sdram_md_cntl,
260 				 MD_CNTL_MD_EN		|
261 				 MD_CNTL_CS_SEL_CS2_CS3	|
262 				 0x04000000		|
263 				 MD_CNTL_WRCW		|
264 				 MD_CNTL_MD_VALUE(0x0a));
265 #endif
266 			break;
267 		case 0x00200000:
268 			out_be32(&ddr->sdram_md_cntl,
269 				MD_CNTL_MD_EN		|
270 				MD_CNTL_CS_SEL_CS0_CS1	|
271 				0x04000000		|
272 				MD_CNTL_WRCW		|
273 				MD_CNTL_MD_VALUE(0x12));
274 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
275 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
276 				break;
277 			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
278 				;
279 			out_be32(&ddr->sdram_md_cntl,
280 				 MD_CNTL_MD_EN		|
281 				 MD_CNTL_CS_SEL_CS2_CS3	|
282 				 0x04000000		|
283 				 MD_CNTL_WRCW		|
284 				 MD_CNTL_MD_VALUE(0x12));
285 #endif
286 			break;
287 		case 0x00300000:
288 			out_be32(&ddr->sdram_md_cntl,
289 				MD_CNTL_MD_EN		|
290 				MD_CNTL_CS_SEL_CS0_CS1	|
291 				0x04000000		|
292 				MD_CNTL_WRCW		|
293 				MD_CNTL_MD_VALUE(0x1a));
294 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
295 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
296 				break;
297 			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
298 				;
299 			out_be32(&ddr->sdram_md_cntl,
300 				 MD_CNTL_MD_EN		|
301 				 MD_CNTL_CS_SEL_CS2_CS3	|
302 				 0x04000000		|
303 				 MD_CNTL_WRCW		|
304 				 MD_CNTL_MD_VALUE(0x1a));
305 #endif
306 			break;
307 		default:
308 			out_be32(&ddr->sdram_md_cntl,
309 				MD_CNTL_MD_EN		|
310 				MD_CNTL_CS_SEL_CS0_CS1	|
311 				0x04000000		|
312 				MD_CNTL_WRCW		|
313 				MD_CNTL_MD_VALUE(0x02));
314 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
315 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
316 				break;
317 			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
318 				;
319 			out_be32(&ddr->sdram_md_cntl,
320 				 MD_CNTL_MD_EN		|
321 				 MD_CNTL_CS_SEL_CS2_CS3	|
322 				 0x04000000		|
323 				 MD_CNTL_WRCW		|
324 				 MD_CNTL_MD_VALUE(0x02));
325 #endif
326 			printf("Unsupported RC10\n");
327 			break;
328 		}
329 
330 		while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
331 			;
332 		udelay(6);
333 		out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
334 		out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
335 		out_be32(&ddr->debug[2], 0x0);
336 		out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
337 		out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
338 		out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
339 		out_be32(&ddr->debug[12], save1);
340 		out_be32(&ddr->debug[21], save2);
341 		out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
342 
343 	}
344 #endif
345 	/*
346 	 * For 8572 DDR1 erratum - DDR controller may enter illegal state
347 	 * when operatiing in 32-bit bus mode with 4-beat bursts,
348 	 * This erratum does not affect DDR3 mode, only for DDR2 mode.
349 	 */
350 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
351 	debug("Workaround for ERRATUM_DDR_115\n");
352 	if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
353 	    && in_be32(&ddr->sdram_cfg) & 0x80000) {
354 		/* set DEBUG_1[31] */
355 		setbits_be32(&ddr->debug[0], 1);
356 	}
357 #endif
358 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
359 	debug("Workaround for ERRATUM_DDR111_DDR134\n");
360 	/*
361 	 * This is the combined workaround for DDR111 and DDR134
362 	 * following the published errata for MPC8572
363 	 */
364 
365 	/* 1. Set EEBACR[3] */
366 	setbits_be32(&ecm->eebacr, 0x10000000);
367 	debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
368 
369 	/* 2. Set DINIT in SDRAM_CFG_2*/
370 	setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
371 	debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
372 		in_be32(&ddr->sdram_cfg_2));
373 
374 	/* 3. Set DEBUG_3[21] */
375 	setbits_be32(&ddr->debug[2], 0x400);
376 	debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
377 
378 #endif	/* part 1 of the workaound */
379 
380 	/*
381 	 * 500 painful micro-seconds must elapse between
382 	 * the DDR clock setup and the DDR config enable.
383 	 * DDR2 need 200 us, and DDR3 need 500 us from spec,
384 	 * we choose the max, that is 500 us for all of case.
385 	 */
386 	udelay(500);
387 	asm volatile("sync;isync");
388 
389 #ifdef CONFIG_DEEP_SLEEP
390 	if (is_warm_boot()) {
391 		/* enter self-refresh */
392 		setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
393 		/* do board specific memory setup */
394 		board_mem_sleep_setup();
395 		temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
396 	} else
397 #endif
398 		temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
399 
400 	/* Let the controller go */
401 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
402 	asm volatile("sync;isync");
403 
404 	total_gb_size_per_controller = 0;
405 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
406 		if (!(regs->cs[i].config & 0x80000000))
407 			continue;
408 		total_gb_size_per_controller += 1 << (
409 			((regs->cs[i].config >> 14) & 0x3) + 2 +
410 			((regs->cs[i].config >> 8) & 0x7) + 12 +
411 			((regs->cs[i].config >> 0) & 0x7) + 8 +
412 			3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
413 			26);			/* minus 26 (count of 64M) */
414 	}
415 	if (fsl_ddr_get_intl3r() & 0x80000000)	/* 3-way interleaving */
416 		total_gb_size_per_controller *= 3;
417 	else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
418 		total_gb_size_per_controller <<= 1;
419 	/*
420 	 * total memory / bus width = transactions needed
421 	 * transactions needed / data rate = seconds
422 	 * to add plenty of buffer, double the time
423 	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
424 	 * Let's wait for 800ms
425 	 */
426 	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
427 			>> SDRAM_CFG_DBW_SHIFT);
428 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
429 		(get_ddr_freq(0) >> 20)) << 1;
430 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
431 	timeout_save = timeout;
432 #endif
433 	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
434 	debug("total %d GB\n", total_gb_size_per_controller);
435 	debug("Need to wait up to %d * 10ms\n", timeout);
436 
437 	/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
438 	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
439 		(timeout >= 0)) {
440 		udelay(10000);		/* throttle polling rate */
441 		timeout--;
442 	}
443 
444 	if (timeout <= 0)
445 		printf("Waiting for D_INIT timeout. Memory may not work.\n");
446 
447 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
448 	/* continue this workaround */
449 
450 	/* 4. Clear DEBUG3[21] */
451 	clrbits_be32(&ddr->debug[2], 0x400);
452 	debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
453 
454 	/* DDR134 workaround starts */
455 	/* A: Clear sdram_cfg_2[odt_cfg] */
456 	clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
457 	debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
458 		in_be32(&ddr->sdram_cfg_2));
459 
460 	/* B: Set DEBUG1[15] */
461 	setbits_be32(&ddr->debug[0], 0x10000);
462 	debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
463 
464 	/* C: Set timing_cfg_2[cpo] to 0b11111 */
465 	setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
466 	debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
467 		in_be32(&ddr->timing_cfg_2));
468 
469 	/* D: Set D6 to 0x9f9f9f9f */
470 	out_be32(&ddr->debug[5], 0x9f9f9f9f);
471 	debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
472 
473 	/* E: Set D7 to 0x9f9f9f9f */
474 	out_be32(&ddr->debug[6], 0x9f9f9f9f);
475 	debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
476 
477 	/* F: Set D2[20] */
478 	setbits_be32(&ddr->debug[1], 0x800);
479 	debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
480 
481 	/* G: Poll on D2[20] until cleared */
482 	while (in_be32(&ddr->debug[1]) & 0x800)
483 		udelay(10000);          /* throttle polling rate */
484 
485 	/* H: Clear D1[15] */
486 	clrbits_be32(&ddr->debug[0], 0x10000);
487 	debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
488 
489 	/* I: Set sdram_cfg_2[odt_cfg] */
490 	setbits_be32(&ddr->sdram_cfg_2,
491 		regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
492 	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
493 
494 	/* Continuing with the DDR111 workaround */
495 	/* 5. Set D2[21] */
496 	setbits_be32(&ddr->debug[1], 0x400);
497 	debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
498 
499 	/* 6. Poll D2[21] until its cleared */
500 	while (in_be32(&ddr->debug[1]) & 0x400)
501 		udelay(10000);          /* throttle polling rate */
502 
503 	/* 7. Wait for state machine 2nd run, roughly 400ms/GB */
504 	debug("Wait for %d * 10ms\n", timeout_save);
505 	udelay(timeout_save * 10000);
506 
507 	/* 8. Set sdram_cfg_2[dinit] if options requires */
508 	setbits_be32(&ddr->sdram_cfg_2,
509 		regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
510 	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
511 
512 	/* 9. Poll until dinit is cleared */
513 	timeout = timeout_save;
514 	debug("Need to wait up to %d * 10ms\n", timeout);
515 	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
516 		(timeout >= 0)) {
517 		udelay(10000);		/* throttle polling rate */
518 		timeout--;
519 	}
520 
521 	if (timeout <= 0)
522 		printf("Waiting for D_INIT timeout. Memory may not work.\n");
523 
524 	/* 10. Clear EEBACR[3] */
525 	clrbits_be32(&ecm->eebacr, 10000000);
526 	debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
527 
528 	if (csn != -1) {
529 		csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
530 		*csn_bnds_t = csn_bnds_backup;
531 		debug("Change cs%d_bnds back to 0x%08x\n",
532 			csn, regs->cs[csn].bnds);
533 		setbits_be32(&ddr->sdram_cfg, 0x2);	/* MEM_HALT */
534 		switch (csn) {
535 		case 0:
536 			out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
537 			break;
538 		case 1:
539 			out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
540 			break;
541 		case 2:
542 			out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
543 			break;
544 		case 3:
545 			out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
546 			break;
547 		}
548 		clrbits_be32(&ddr->sdram_cfg, 0x2);
549 	}
550 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
551 #ifdef CONFIG_DEEP_SLEEP
552 	if (is_warm_boot())
553 		/* exit self-refresh */
554 		clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
555 #endif
556 }
557