1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2008 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <fsl_ddr_sdram.h> 9 10 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 11 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 12 #endif 13 14 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 15 unsigned int ctrl_num, int step) 16 { 17 unsigned int i; 18 struct ccsr_ddr __iomem *ddr = 19 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; 20 21 if (ctrl_num != 0) { 22 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 23 return; 24 } 25 26 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 27 if (i == 0) { 28 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); 29 out_be32(&ddr->cs0_config, regs->cs[i].config); 30 31 } else if (i == 1) { 32 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); 33 out_be32(&ddr->cs1_config, regs->cs[i].config); 34 35 } else if (i == 2) { 36 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); 37 out_be32(&ddr->cs2_config, regs->cs[i].config); 38 39 } else if (i == 3) { 40 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); 41 out_be32(&ddr->cs3_config, regs->cs[i].config); 42 } 43 } 44 45 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); 46 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); 47 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); 48 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); 49 #if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541) 50 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 51 #endif 52 53 /* 54 * 200 painful micro-seconds must elapse between 55 * the DDR clock setup and the DDR config enable. 56 */ 57 udelay(200); 58 asm volatile("sync;isync"); 59 60 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); 61 62 asm("sync;isync;msync"); 63 udelay(500); 64 } 65 66 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 67 /* 68 * Initialize all of memory for ECC, then enable errors. 69 */ 70 71 void 72 ddr_enable_ecc(unsigned int dram_size) 73 { 74 struct ccsr_ddr __iomem *ddr = 75 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 76 77 dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); 78 79 /* 80 * Enable errors for ECC. 81 */ 82 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); 83 ddr->err_disable = 0x00000000; 84 asm("sync;isync;msync"); 85 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); 86 } 87 88 #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ 89