1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. 11 * Based on code from spd_sdram.c 12 * Author: James Yang [at freescale.com] 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <fsl_ddr_sdram.h> 18 #include <fsl_ddr.h> 19 20 /* 21 * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view 22 * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for 23 * all Power SoCs. But it could be different for ARM SoCs. For example, 24 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of 25 * 0x00_8000_0000 ~ 0x00_ffff_ffff 26 * 0x80_8000_0000 ~ 0xff_ffff_ffff 27 */ 28 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE 30 #endif 31 32 #ifdef CONFIG_PPC 33 #include <asm/fsl_law.h> 34 35 void fsl_ddr_set_lawbar( 36 const common_timing_params_t *memctl_common_params, 37 unsigned int memctl_interleaved, 38 unsigned int ctrl_num); 39 #endif 40 41 void fsl_ddr_set_intl3r(const unsigned int granule_size); 42 #if defined(SPD_EEPROM_ADDRESS) || \ 43 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ 44 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) 45 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 46 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 47 [0][0] = SPD_EEPROM_ADDRESS, 48 }; 49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 51 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 52 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ 53 }; 54 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 55 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 56 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 57 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ 58 }; 59 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 60 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 61 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 62 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ 63 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ 64 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ 65 }; 66 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 67 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 68 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 69 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ 70 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ 71 }; 72 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 73 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 74 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 75 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ 76 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ 77 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ 78 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ 79 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ 80 }; 81 82 #endif 83 84 #define SPD_SPA0_ADDRESS 0x36 85 #define SPD_SPA1_ADDRESS 0x37 86 87 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) 88 { 89 int ret; 90 #ifdef CONFIG_SYS_FSL_DDR4 91 uint8_t dummy = 0; 92 #endif 93 94 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); 95 96 #ifdef CONFIG_SYS_FSL_DDR4 97 /* 98 * DDR4 SPD has 384 to 512 bytes 99 * To access the lower 256 bytes, we need to set EE page address to 0 100 * To access the upper 256 bytes, we need to set EE page address to 1 101 * See Jedec standar No. 21-C for detail 102 */ 103 i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1); 104 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256); 105 if (!ret) { 106 i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1); 107 ret = i2c_read(i2c_address, 0, 1, 108 (uchar *)((ulong)spd + 256), 109 min(256, sizeof(generic_spd_eeprom_t) - 256)); 110 } 111 #else 112 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 113 sizeof(generic_spd_eeprom_t)); 114 #endif 115 116 if (ret) { 117 if (i2c_address == 118 #ifdef SPD_EEPROM_ADDRESS 119 SPD_EEPROM_ADDRESS 120 #elif defined(SPD_EEPROM_ADDRESS1) 121 SPD_EEPROM_ADDRESS1 122 #endif 123 ) { 124 printf("DDR: failed to read SPD from address %u\n", 125 i2c_address); 126 } else { 127 debug("DDR: failed to read SPD from address %u\n", 128 i2c_address); 129 } 130 memset(spd, 0, sizeof(generic_spd_eeprom_t)); 131 } 132 } 133 134 __attribute__((weak, alias("__get_spd"))) 135 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); 136 137 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 138 unsigned int ctrl_num) 139 { 140 unsigned int i; 141 unsigned int i2c_address = 0; 142 143 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { 144 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 145 return; 146 } 147 148 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 149 i2c_address = spd_i2c_addr[ctrl_num][i]; 150 get_spd(&(ctrl_dimms_spd[i]), i2c_address); 151 } 152 } 153 #else 154 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 155 unsigned int ctrl_num) 156 { 157 } 158 #endif /* SPD_EEPROM_ADDRESSx */ 159 160 /* 161 * ASSUMPTIONS: 162 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller 163 * - Same memory data bus width on all controllers 164 * 165 * NOTES: 166 * 167 * The memory controller and associated documentation use confusing 168 * terminology when referring to the orgranization of DRAM. 169 * 170 * Here is a terminology translation table: 171 * 172 * memory controller/documention |industry |this code |signals 173 * -------------------------------|-----------|-----------|----------------- 174 * physical bank/bank |rank |rank |chip select (CS) 175 * logical bank/sub-bank |bank |bank |bank address (BA) 176 * page/row |row |page |row address 177 * ??? |column |column |column address 178 * 179 * The naming confusion is further exacerbated by the descriptions of the 180 * memory controller interleaving feature, where accesses are interleaved 181 * _BETWEEN_ two seperate memory controllers. This is configured only in 182 * CS0_CONFIG[INTLV_CTL] of each memory controller. 183 * 184 * memory controller documentation | number of chip selects 185 * | per memory controller supported 186 * --------------------------------|----------------------------------------- 187 * cache line interleaving | 1 (CS0 only) 188 * page interleaving | 1 (CS0 only) 189 * bank interleaving | 1 (CS0 only) 190 * superbank interleraving | depends on bank (chip select) 191 * | interleraving [rank interleaving] 192 * | mode used on every memory controller 193 * 194 * Even further confusing is the existence of the interleaving feature 195 * _WITHIN_ each memory controller. The feature is referred to in 196 * documentation as chip select interleaving or bank interleaving, 197 * although it is configured in the DDR_SDRAM_CFG field. 198 * 199 * Name of field | documentation name | this code 200 * -----------------------------|-----------------------|------------------ 201 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving 202 * | interleaving 203 */ 204 205 const char *step_string_tbl[] = { 206 "STEP_GET_SPD", 207 "STEP_COMPUTE_DIMM_PARMS", 208 "STEP_COMPUTE_COMMON_PARMS", 209 "STEP_GATHER_OPTS", 210 "STEP_ASSIGN_ADDRESSES", 211 "STEP_COMPUTE_REGS", 212 "STEP_PROGRAM_REGS", 213 "STEP_ALL" 214 }; 215 216 const char * step_to_string(unsigned int step) { 217 218 unsigned int s = __ilog2(step); 219 220 if ((1 << s) != step) 221 return step_string_tbl[7]; 222 223 if (s >= ARRAY_SIZE(step_string_tbl)) { 224 printf("Error for the step in %s\n", __func__); 225 s = 0; 226 } 227 228 return step_string_tbl[s]; 229 } 230 231 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, 232 unsigned int dbw_cap_adj[]) 233 { 234 int i, j; 235 unsigned long long total_mem, current_mem_base, total_ctlr_mem; 236 unsigned long long rank_density, ctlr_density = 0; 237 238 /* 239 * If a reduced data width is requested, but the SPD 240 * specifies a physically wider device, adjust the 241 * computed dimm capacities accordingly before 242 * assigning addresses. 243 */ 244 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 245 unsigned int found = 0; 246 247 switch (pinfo->memctl_opts[i].data_bus_width) { 248 case 2: 249 /* 16-bit */ 250 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 251 unsigned int dw; 252 if (!pinfo->dimm_params[i][j].n_ranks) 253 continue; 254 dw = pinfo->dimm_params[i][j].primary_sdram_width; 255 if ((dw == 72 || dw == 64)) { 256 dbw_cap_adj[i] = 2; 257 break; 258 } else if ((dw == 40 || dw == 32)) { 259 dbw_cap_adj[i] = 1; 260 break; 261 } 262 } 263 break; 264 265 case 1: 266 /* 32-bit */ 267 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 268 unsigned int dw; 269 dw = pinfo->dimm_params[i][j].data_width; 270 if (pinfo->dimm_params[i][j].n_ranks 271 && (dw == 72 || dw == 64)) { 272 /* 273 * FIXME: can't really do it 274 * like this because this just 275 * further reduces the memory 276 */ 277 found = 1; 278 break; 279 } 280 } 281 if (found) { 282 dbw_cap_adj[i] = 1; 283 } 284 break; 285 286 case 0: 287 /* 64-bit */ 288 break; 289 290 default: 291 printf("unexpected data bus width " 292 "specified controller %u\n", i); 293 return 1; 294 } 295 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); 296 } 297 298 current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; 299 total_mem = 0; 300 if (pinfo->memctl_opts[0].memctl_interleaving) { 301 rank_density = pinfo->dimm_params[0][0].rank_density >> 302 dbw_cap_adj[0]; 303 switch (pinfo->memctl_opts[0].ba_intlv_ctl & 304 FSL_DDR_CS0_CS1_CS2_CS3) { 305 case FSL_DDR_CS0_CS1_CS2_CS3: 306 ctlr_density = 4 * rank_density; 307 break; 308 case FSL_DDR_CS0_CS1: 309 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 310 ctlr_density = 2 * rank_density; 311 break; 312 case FSL_DDR_CS2_CS3: 313 default: 314 ctlr_density = rank_density; 315 break; 316 } 317 debug("rank density is 0x%llx, ctlr density is 0x%llx\n", 318 rank_density, ctlr_density); 319 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 320 if (pinfo->memctl_opts[i].memctl_interleaving) { 321 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { 322 case FSL_DDR_256B_INTERLEAVING: 323 case FSL_DDR_CACHE_LINE_INTERLEAVING: 324 case FSL_DDR_PAGE_INTERLEAVING: 325 case FSL_DDR_BANK_INTERLEAVING: 326 case FSL_DDR_SUPERBANK_INTERLEAVING: 327 total_ctlr_mem = 2 * ctlr_density; 328 break; 329 case FSL_DDR_3WAY_1KB_INTERLEAVING: 330 case FSL_DDR_3WAY_4KB_INTERLEAVING: 331 case FSL_DDR_3WAY_8KB_INTERLEAVING: 332 total_ctlr_mem = 3 * ctlr_density; 333 break; 334 case FSL_DDR_4WAY_1KB_INTERLEAVING: 335 case FSL_DDR_4WAY_4KB_INTERLEAVING: 336 case FSL_DDR_4WAY_8KB_INTERLEAVING: 337 total_ctlr_mem = 4 * ctlr_density; 338 break; 339 default: 340 panic("Unknown interleaving mode"); 341 } 342 pinfo->common_timing_params[i].base_address = 343 current_mem_base; 344 pinfo->common_timing_params[i].total_mem = 345 total_ctlr_mem; 346 total_mem = current_mem_base + total_ctlr_mem; 347 debug("ctrl %d base 0x%llx\n", i, current_mem_base); 348 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 349 } else { 350 /* when 3rd controller not interleaved */ 351 current_mem_base = total_mem; 352 total_ctlr_mem = 0; 353 pinfo->common_timing_params[i].base_address = 354 current_mem_base; 355 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 356 unsigned long long cap = 357 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; 358 pinfo->dimm_params[i][j].base_address = 359 current_mem_base; 360 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); 361 current_mem_base += cap; 362 total_ctlr_mem += cap; 363 } 364 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 365 pinfo->common_timing_params[i].total_mem = 366 total_ctlr_mem; 367 total_mem += total_ctlr_mem; 368 } 369 } 370 } else { 371 /* 372 * Simple linear assignment if memory 373 * controllers are not interleaved. 374 */ 375 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 376 total_ctlr_mem = 0; 377 pinfo->common_timing_params[i].base_address = 378 current_mem_base; 379 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 380 /* Compute DIMM base addresses. */ 381 unsigned long long cap = 382 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; 383 pinfo->dimm_params[i][j].base_address = 384 current_mem_base; 385 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); 386 current_mem_base += cap; 387 total_ctlr_mem += cap; 388 } 389 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 390 pinfo->common_timing_params[i].total_mem = 391 total_ctlr_mem; 392 total_mem += total_ctlr_mem; 393 } 394 } 395 debug("Total mem by %s is 0x%llx\n", __func__, total_mem); 396 397 return total_mem; 398 } 399 400 /* Use weak function to allow board file to override the address assignment */ 401 __attribute__((weak, alias("__step_assign_addresses"))) 402 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, 403 unsigned int dbw_cap_adj[]); 404 405 unsigned long long 406 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, 407 unsigned int size_only) 408 { 409 unsigned int i, j; 410 unsigned long long total_mem = 0; 411 int assert_reset; 412 413 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; 414 common_timing_params_t *timing_params = pinfo->common_timing_params; 415 assert_reset = board_need_mem_reset(); 416 417 /* data bus width capacity adjust shift amount */ 418 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; 419 420 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 421 dbw_capacity_adjust[i] = 0; 422 } 423 424 debug("starting at step %u (%s)\n", 425 start_step, step_to_string(start_step)); 426 427 switch (start_step) { 428 case STEP_GET_SPD: 429 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) 430 /* STEP 1: Gather all DIMM SPD data */ 431 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 432 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); 433 } 434 435 case STEP_COMPUTE_DIMM_PARMS: 436 /* STEP 2: Compute DIMM parameters from SPD data */ 437 438 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 439 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 440 unsigned int retval; 441 generic_spd_eeprom_t *spd = 442 &(pinfo->spd_installed_dimms[i][j]); 443 dimm_params_t *pdimm = 444 &(pinfo->dimm_params[i][j]); 445 446 retval = compute_dimm_parameters(spd, pdimm, i); 447 #ifdef CONFIG_SYS_DDR_RAW_TIMING 448 if (!i && !j && retval) { 449 printf("SPD error on controller %d! " 450 "Trying fallback to raw timing " 451 "calculation\n", i); 452 fsl_ddr_get_dimm_params(pdimm, i, j); 453 } 454 #else 455 if (retval == 2) { 456 printf("Error: compute_dimm_parameters" 457 " non-zero returned FATAL value " 458 "for memctl=%u dimm=%u\n", i, j); 459 return 0; 460 } 461 #endif 462 if (retval) { 463 debug("Warning: compute_dimm_parameters" 464 " non-zero return value for memctl=%u " 465 "dimm=%u\n", i, j); 466 } 467 } 468 } 469 470 #elif defined(CONFIG_SYS_DDR_RAW_TIMING) 471 case STEP_COMPUTE_DIMM_PARMS: 472 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 473 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 474 dimm_params_t *pdimm = 475 &(pinfo->dimm_params[i][j]); 476 fsl_ddr_get_dimm_params(pdimm, i, j); 477 } 478 } 479 debug("Filling dimm parameters from board specific file\n"); 480 #endif 481 case STEP_COMPUTE_COMMON_PARMS: 482 /* 483 * STEP 3: Compute a common set of timing parameters 484 * suitable for all of the DIMMs on each memory controller 485 */ 486 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 487 debug("Computing lowest common DIMM" 488 " parameters for memctl=%u\n", i); 489 compute_lowest_common_dimm_parameters( 490 pinfo->dimm_params[i], 491 &timing_params[i], 492 CONFIG_DIMM_SLOTS_PER_CTLR); 493 } 494 495 case STEP_GATHER_OPTS: 496 /* STEP 4: Gather configuration requirements from user */ 497 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 498 debug("Reloading memory controller " 499 "configuration options for memctl=%u\n", i); 500 /* 501 * This "reloads" the memory controller options 502 * to defaults. If the user "edits" an option, 503 * next_step points to the step after this, 504 * which is currently STEP_ASSIGN_ADDRESSES. 505 */ 506 populate_memctl_options( 507 timing_params[i].all_dimms_registered, 508 &pinfo->memctl_opts[i], 509 pinfo->dimm_params[i], i); 510 /* 511 * For RDIMMs, JEDEC spec requires clocks to be stable 512 * before reset signal is deasserted. For the boards 513 * using fixed parameters, this function should be 514 * be called from board init file. 515 */ 516 if (timing_params[i].all_dimms_registered) 517 assert_reset = 1; 518 } 519 if (assert_reset) { 520 debug("Asserting mem reset\n"); 521 board_assert_mem_reset(); 522 } 523 524 case STEP_ASSIGN_ADDRESSES: 525 /* STEP 5: Assign addresses to chip selects */ 526 check_interleaving_options(pinfo); 527 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); 528 debug("Total mem %llu assigned\n", total_mem); 529 530 case STEP_COMPUTE_REGS: 531 /* STEP 6: compute controller register values */ 532 debug("FSL Memory ctrl register computation\n"); 533 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 534 if (timing_params[i].ndimms_present == 0) { 535 memset(&ddr_reg[i], 0, 536 sizeof(fsl_ddr_cfg_regs_t)); 537 continue; 538 } 539 540 compute_fsl_memctl_config_regs( 541 &pinfo->memctl_opts[i], 542 &ddr_reg[i], &timing_params[i], 543 pinfo->dimm_params[i], 544 dbw_capacity_adjust[i], 545 size_only); 546 } 547 548 default: 549 break; 550 } 551 552 { 553 /* 554 * Compute the amount of memory available just by 555 * looking for the highest valid CSn_BNDS value. 556 * This allows us to also experiment with using 557 * only CS0 when using dual-rank DIMMs. 558 */ 559 unsigned int max_end = 0; 560 561 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 562 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { 563 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; 564 if (reg->cs[j].config & 0x80000000) { 565 unsigned int end; 566 /* 567 * 0xfffffff is a special value we put 568 * for unused bnds 569 */ 570 if (reg->cs[j].bnds == 0xffffffff) 571 continue; 572 end = reg->cs[j].bnds & 0xffff; 573 if (end > max_end) { 574 max_end = end; 575 } 576 } 577 } 578 } 579 580 total_mem = 1 + (((unsigned long long)max_end << 24ULL) | 581 0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; 582 } 583 584 return total_mem; 585 } 586 587 /* 588 * fsl_ddr_sdram() -- this is the main function to be called by 589 * initdram() in the board file. 590 * 591 * It returns amount of memory configured in bytes. 592 */ 593 phys_size_t fsl_ddr_sdram(void) 594 { 595 unsigned int i; 596 #ifdef CONFIG_PPC 597 unsigned int law_memctl = LAW_TRGT_IF_DDR_1; 598 #endif 599 unsigned long long total_memory; 600 fsl_ddr_info_t info; 601 int deassert_reset; 602 603 /* Reset info structure. */ 604 memset(&info, 0, sizeof(fsl_ddr_info_t)); 605 606 /* Compute it once normally. */ 607 #ifdef CONFIG_FSL_DDR_INTERACTIVE 608 if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */ 609 total_memory = fsl_ddr_interactive(&info, 0); 610 } else if (fsl_ddr_interactive_env_var_exists()) { 611 total_memory = fsl_ddr_interactive(&info, 1); 612 } else 613 #endif 614 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); 615 616 /* setup 3-way interleaving before enabling DDRC */ 617 if (info.memctl_opts[0].memctl_interleaving) { 618 switch (info.memctl_opts[0].memctl_interleaving_mode) { 619 case FSL_DDR_3WAY_1KB_INTERLEAVING: 620 case FSL_DDR_3WAY_4KB_INTERLEAVING: 621 case FSL_DDR_3WAY_8KB_INTERLEAVING: 622 fsl_ddr_set_intl3r( 623 info.memctl_opts[0].memctl_interleaving_mode); 624 break; 625 default: 626 break; 627 } 628 } 629 630 /* 631 * Program configuration registers. 632 * JEDEC specs requires clocks to be stable before deasserting reset 633 * for RDIMMs. Clocks start after chip select is enabled and clock 634 * control register is set. During step 1, all controllers have their 635 * registers set but not enabled. Step 2 proceeds after deasserting 636 * reset through board FPGA or GPIO. 637 * For non-registered DIMMs, initialization can go through but it is 638 * also OK to follow the same flow. 639 */ 640 deassert_reset = board_need_mem_reset(); 641 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 642 if (info.common_timing_params[i].all_dimms_registered) 643 deassert_reset = 1; 644 } 645 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 646 debug("Programming controller %u\n", i); 647 if (info.common_timing_params[i].ndimms_present == 0) { 648 debug("No dimms present on controller %u; " 649 "skipping programming\n", i); 650 continue; 651 } 652 /* 653 * The following call with step = 1 returns before enabling 654 * the controller. It has to finish with step = 2 later. 655 */ 656 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i, 657 deassert_reset ? 1 : 0); 658 } 659 if (deassert_reset) { 660 /* Use board FPGA or GPIO to deassert reset signal */ 661 debug("Deasserting mem reset\n"); 662 board_deassert_mem_reset(); 663 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 664 /* Call with step = 2 to continue initialization */ 665 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), 666 i, 2); 667 } 668 } 669 670 #ifdef CONFIG_PPC 671 /* program LAWs */ 672 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 673 if (info.memctl_opts[i].memctl_interleaving) { 674 switch (info.memctl_opts[i].memctl_interleaving_mode) { 675 case FSL_DDR_CACHE_LINE_INTERLEAVING: 676 case FSL_DDR_PAGE_INTERLEAVING: 677 case FSL_DDR_BANK_INTERLEAVING: 678 case FSL_DDR_SUPERBANK_INTERLEAVING: 679 if (i == 0) { 680 law_memctl = LAW_TRGT_IF_DDR_INTRLV; 681 fsl_ddr_set_lawbar(&info.common_timing_params[i], 682 law_memctl, i); 683 } else if (i == 2) { 684 law_memctl = LAW_TRGT_IF_DDR_INTLV_34; 685 fsl_ddr_set_lawbar(&info.common_timing_params[i], 686 law_memctl, i); 687 } 688 break; 689 case FSL_DDR_3WAY_1KB_INTERLEAVING: 690 case FSL_DDR_3WAY_4KB_INTERLEAVING: 691 case FSL_DDR_3WAY_8KB_INTERLEAVING: 692 law_memctl = LAW_TRGT_IF_DDR_INTLV_123; 693 if (i == 0) { 694 fsl_ddr_set_lawbar(&info.common_timing_params[i], 695 law_memctl, i); 696 } 697 break; 698 case FSL_DDR_4WAY_1KB_INTERLEAVING: 699 case FSL_DDR_4WAY_4KB_INTERLEAVING: 700 case FSL_DDR_4WAY_8KB_INTERLEAVING: 701 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; 702 if (i == 0) 703 fsl_ddr_set_lawbar(&info.common_timing_params[i], 704 law_memctl, i); 705 /* place holder for future 4-way interleaving */ 706 break; 707 default: 708 break; 709 } 710 } else { 711 switch (i) { 712 case 0: 713 law_memctl = LAW_TRGT_IF_DDR_1; 714 break; 715 case 1: 716 law_memctl = LAW_TRGT_IF_DDR_2; 717 break; 718 case 2: 719 law_memctl = LAW_TRGT_IF_DDR_3; 720 break; 721 case 3: 722 law_memctl = LAW_TRGT_IF_DDR_4; 723 break; 724 default: 725 break; 726 } 727 fsl_ddr_set_lawbar(&info.common_timing_params[i], 728 law_memctl, i); 729 } 730 } 731 #endif 732 733 debug("total_memory by %s = %llu\n", __func__, total_memory); 734 735 #if !defined(CONFIG_PHYS_64BIT) 736 /* Check for 4G or more. Bad. */ 737 if (total_memory >= (1ull << 32)) { 738 puts("Detected "); 739 print_size(total_memory, " of memory\n"); 740 printf(" This U-Boot only supports < 4G of DDR\n"); 741 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); 742 printf(" "); /* re-align to match init_func_ram print */ 743 total_memory = CONFIG_MAX_MEM_MAPPED; 744 } 745 #endif 746 747 return total_memory; 748 } 749 750 /* 751 * fsl_ddr_sdram_size() - This function only returns the size of the total 752 * memory without setting ddr control registers. 753 */ 754 phys_size_t 755 fsl_ddr_sdram_size(void) 756 { 757 fsl_ddr_info_t info; 758 unsigned long long total_memory = 0; 759 760 memset(&info, 0 , sizeof(fsl_ddr_info_t)); 761 762 /* Compute it once normally. */ 763 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); 764 765 return total_memory; 766 } 767