1 /* 2 * Copyright 2008-2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. 11 * Based on code from spd_sdram.c 12 * Author: James Yang [at freescale.com] 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <fsl_ddr_sdram.h> 18 #include <fsl_ddr.h> 19 20 /* 21 * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view 22 * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for 23 * all Power SoCs. But it could be different for ARM SoCs. For example, 24 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of 25 * 0x00_8000_0000 ~ 0x00_ffff_ffff 26 * 0x80_8000_0000 ~ 0xff_ffff_ffff 27 */ 28 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE 30 #endif 31 32 #ifdef CONFIG_PPC 33 #include <asm/fsl_law.h> 34 35 void fsl_ddr_set_lawbar( 36 const common_timing_params_t *memctl_common_params, 37 unsigned int memctl_interleaved, 38 unsigned int ctrl_num); 39 #endif 40 41 void fsl_ddr_set_intl3r(const unsigned int granule_size); 42 #if defined(SPD_EEPROM_ADDRESS) || \ 43 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ 44 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) 45 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 46 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 47 [0][0] = SPD_EEPROM_ADDRESS, 48 }; 49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 51 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 52 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ 53 }; 54 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 55 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 56 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 57 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ 58 }; 59 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 60 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 61 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 62 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ 63 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ 64 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ 65 }; 66 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 67 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 68 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 69 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ 70 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ 71 }; 72 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 73 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 74 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 75 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ 76 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ 77 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ 78 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ 79 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ 80 }; 81 82 #endif 83 84 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) 85 { 86 int ret; 87 88 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); 89 90 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 91 sizeof(generic_spd_eeprom_t)); 92 93 if (ret) { 94 if (i2c_address == 95 #ifdef SPD_EEPROM_ADDRESS 96 SPD_EEPROM_ADDRESS 97 #elif defined(SPD_EEPROM_ADDRESS1) 98 SPD_EEPROM_ADDRESS1 99 #endif 100 ) { 101 printf("DDR: failed to read SPD from address %u\n", 102 i2c_address); 103 } else { 104 debug("DDR: failed to read SPD from address %u\n", 105 i2c_address); 106 } 107 memset(spd, 0, sizeof(generic_spd_eeprom_t)); 108 } 109 } 110 111 __attribute__((weak, alias("__get_spd"))) 112 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); 113 114 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 115 unsigned int ctrl_num) 116 { 117 unsigned int i; 118 unsigned int i2c_address = 0; 119 120 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { 121 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 122 return; 123 } 124 125 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 126 i2c_address = spd_i2c_addr[ctrl_num][i]; 127 get_spd(&(ctrl_dimms_spd[i]), i2c_address); 128 } 129 } 130 #else 131 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 132 unsigned int ctrl_num) 133 { 134 } 135 #endif /* SPD_EEPROM_ADDRESSx */ 136 137 /* 138 * ASSUMPTIONS: 139 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller 140 * - Same memory data bus width on all controllers 141 * 142 * NOTES: 143 * 144 * The memory controller and associated documentation use confusing 145 * terminology when referring to the orgranization of DRAM. 146 * 147 * Here is a terminology translation table: 148 * 149 * memory controller/documention |industry |this code |signals 150 * -------------------------------|-----------|-----------|----------------- 151 * physical bank/bank |rank |rank |chip select (CS) 152 * logical bank/sub-bank |bank |bank |bank address (BA) 153 * page/row |row |page |row address 154 * ??? |column |column |column address 155 * 156 * The naming confusion is further exacerbated by the descriptions of the 157 * memory controller interleaving feature, where accesses are interleaved 158 * _BETWEEN_ two seperate memory controllers. This is configured only in 159 * CS0_CONFIG[INTLV_CTL] of each memory controller. 160 * 161 * memory controller documentation | number of chip selects 162 * | per memory controller supported 163 * --------------------------------|----------------------------------------- 164 * cache line interleaving | 1 (CS0 only) 165 * page interleaving | 1 (CS0 only) 166 * bank interleaving | 1 (CS0 only) 167 * superbank interleraving | depends on bank (chip select) 168 * | interleraving [rank interleaving] 169 * | mode used on every memory controller 170 * 171 * Even further confusing is the existence of the interleaving feature 172 * _WITHIN_ each memory controller. The feature is referred to in 173 * documentation as chip select interleaving or bank interleaving, 174 * although it is configured in the DDR_SDRAM_CFG field. 175 * 176 * Name of field | documentation name | this code 177 * -----------------------------|-----------------------|------------------ 178 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving 179 * | interleaving 180 */ 181 182 const char *step_string_tbl[] = { 183 "STEP_GET_SPD", 184 "STEP_COMPUTE_DIMM_PARMS", 185 "STEP_COMPUTE_COMMON_PARMS", 186 "STEP_GATHER_OPTS", 187 "STEP_ASSIGN_ADDRESSES", 188 "STEP_COMPUTE_REGS", 189 "STEP_PROGRAM_REGS", 190 "STEP_ALL" 191 }; 192 193 const char * step_to_string(unsigned int step) { 194 195 unsigned int s = __ilog2(step); 196 197 if ((1 << s) != step) 198 return step_string_tbl[7]; 199 200 return step_string_tbl[s]; 201 } 202 203 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, 204 unsigned int dbw_cap_adj[]) 205 { 206 int i, j; 207 unsigned long long total_mem, current_mem_base, total_ctlr_mem; 208 unsigned long long rank_density, ctlr_density = 0; 209 210 /* 211 * If a reduced data width is requested, but the SPD 212 * specifies a physically wider device, adjust the 213 * computed dimm capacities accordingly before 214 * assigning addresses. 215 */ 216 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 217 unsigned int found = 0; 218 219 switch (pinfo->memctl_opts[i].data_bus_width) { 220 case 2: 221 /* 16-bit */ 222 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 223 unsigned int dw; 224 if (!pinfo->dimm_params[i][j].n_ranks) 225 continue; 226 dw = pinfo->dimm_params[i][j].primary_sdram_width; 227 if ((dw == 72 || dw == 64)) { 228 dbw_cap_adj[i] = 2; 229 break; 230 } else if ((dw == 40 || dw == 32)) { 231 dbw_cap_adj[i] = 1; 232 break; 233 } 234 } 235 break; 236 237 case 1: 238 /* 32-bit */ 239 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 240 unsigned int dw; 241 dw = pinfo->dimm_params[i][j].data_width; 242 if (pinfo->dimm_params[i][j].n_ranks 243 && (dw == 72 || dw == 64)) { 244 /* 245 * FIXME: can't really do it 246 * like this because this just 247 * further reduces the memory 248 */ 249 found = 1; 250 break; 251 } 252 } 253 if (found) { 254 dbw_cap_adj[i] = 1; 255 } 256 break; 257 258 case 0: 259 /* 64-bit */ 260 break; 261 262 default: 263 printf("unexpected data bus width " 264 "specified controller %u\n", i); 265 return 1; 266 } 267 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); 268 } 269 270 current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; 271 total_mem = 0; 272 if (pinfo->memctl_opts[0].memctl_interleaving) { 273 rank_density = pinfo->dimm_params[0][0].rank_density >> 274 dbw_cap_adj[0]; 275 switch (pinfo->memctl_opts[0].ba_intlv_ctl & 276 FSL_DDR_CS0_CS1_CS2_CS3) { 277 case FSL_DDR_CS0_CS1_CS2_CS3: 278 ctlr_density = 4 * rank_density; 279 break; 280 case FSL_DDR_CS0_CS1: 281 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 282 ctlr_density = 2 * rank_density; 283 break; 284 case FSL_DDR_CS2_CS3: 285 default: 286 ctlr_density = rank_density; 287 break; 288 } 289 debug("rank density is 0x%llx, ctlr density is 0x%llx\n", 290 rank_density, ctlr_density); 291 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 292 if (pinfo->memctl_opts[i].memctl_interleaving) { 293 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { 294 case FSL_DDR_CACHE_LINE_INTERLEAVING: 295 case FSL_DDR_PAGE_INTERLEAVING: 296 case FSL_DDR_BANK_INTERLEAVING: 297 case FSL_DDR_SUPERBANK_INTERLEAVING: 298 total_ctlr_mem = 2 * ctlr_density; 299 break; 300 case FSL_DDR_3WAY_1KB_INTERLEAVING: 301 case FSL_DDR_3WAY_4KB_INTERLEAVING: 302 case FSL_DDR_3WAY_8KB_INTERLEAVING: 303 total_ctlr_mem = 3 * ctlr_density; 304 break; 305 case FSL_DDR_4WAY_1KB_INTERLEAVING: 306 case FSL_DDR_4WAY_4KB_INTERLEAVING: 307 case FSL_DDR_4WAY_8KB_INTERLEAVING: 308 total_ctlr_mem = 4 * ctlr_density; 309 break; 310 default: 311 panic("Unknown interleaving mode"); 312 } 313 pinfo->common_timing_params[i].base_address = 314 current_mem_base; 315 pinfo->common_timing_params[i].total_mem = 316 total_ctlr_mem; 317 total_mem = current_mem_base + total_ctlr_mem; 318 debug("ctrl %d base 0x%llx\n", i, current_mem_base); 319 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 320 } else { 321 /* when 3rd controller not interleaved */ 322 current_mem_base = total_mem; 323 total_ctlr_mem = 0; 324 pinfo->common_timing_params[i].base_address = 325 current_mem_base; 326 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 327 unsigned long long cap = 328 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; 329 pinfo->dimm_params[i][j].base_address = 330 current_mem_base; 331 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); 332 current_mem_base += cap; 333 total_ctlr_mem += cap; 334 } 335 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 336 pinfo->common_timing_params[i].total_mem = 337 total_ctlr_mem; 338 total_mem += total_ctlr_mem; 339 } 340 } 341 } else { 342 /* 343 * Simple linear assignment if memory 344 * controllers are not interleaved. 345 */ 346 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 347 total_ctlr_mem = 0; 348 pinfo->common_timing_params[i].base_address = 349 current_mem_base; 350 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 351 /* Compute DIMM base addresses. */ 352 unsigned long long cap = 353 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; 354 pinfo->dimm_params[i][j].base_address = 355 current_mem_base; 356 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); 357 current_mem_base += cap; 358 total_ctlr_mem += cap; 359 } 360 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 361 pinfo->common_timing_params[i].total_mem = 362 total_ctlr_mem; 363 total_mem += total_ctlr_mem; 364 } 365 } 366 debug("Total mem by %s is 0x%llx\n", __func__, total_mem); 367 368 return total_mem; 369 } 370 371 /* Use weak function to allow board file to override the address assignment */ 372 __attribute__((weak, alias("__step_assign_addresses"))) 373 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, 374 unsigned int dbw_cap_adj[]); 375 376 unsigned long long 377 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, 378 unsigned int size_only) 379 { 380 unsigned int i, j; 381 unsigned long long total_mem = 0; 382 int assert_reset; 383 384 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; 385 common_timing_params_t *timing_params = pinfo->common_timing_params; 386 assert_reset = board_need_mem_reset(); 387 388 /* data bus width capacity adjust shift amount */ 389 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; 390 391 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 392 dbw_capacity_adjust[i] = 0; 393 } 394 395 debug("starting at step %u (%s)\n", 396 start_step, step_to_string(start_step)); 397 398 switch (start_step) { 399 case STEP_GET_SPD: 400 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) 401 /* STEP 1: Gather all DIMM SPD data */ 402 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 403 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); 404 } 405 406 case STEP_COMPUTE_DIMM_PARMS: 407 /* STEP 2: Compute DIMM parameters from SPD data */ 408 409 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 410 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 411 unsigned int retval; 412 generic_spd_eeprom_t *spd = 413 &(pinfo->spd_installed_dimms[i][j]); 414 dimm_params_t *pdimm = 415 &(pinfo->dimm_params[i][j]); 416 417 retval = compute_dimm_parameters(spd, pdimm, i); 418 #ifdef CONFIG_SYS_DDR_RAW_TIMING 419 if (!i && !j && retval) { 420 printf("SPD error on controller %d! " 421 "Trying fallback to raw timing " 422 "calculation\n", i); 423 fsl_ddr_get_dimm_params(pdimm, i, j); 424 } 425 #else 426 if (retval == 2) { 427 printf("Error: compute_dimm_parameters" 428 " non-zero returned FATAL value " 429 "for memctl=%u dimm=%u\n", i, j); 430 return 0; 431 } 432 #endif 433 if (retval) { 434 debug("Warning: compute_dimm_parameters" 435 " non-zero return value for memctl=%u " 436 "dimm=%u\n", i, j); 437 } 438 } 439 } 440 441 #elif defined(CONFIG_SYS_DDR_RAW_TIMING) 442 case STEP_COMPUTE_DIMM_PARMS: 443 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 444 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 445 dimm_params_t *pdimm = 446 &(pinfo->dimm_params[i][j]); 447 fsl_ddr_get_dimm_params(pdimm, i, j); 448 } 449 } 450 debug("Filling dimm parameters from board specific file\n"); 451 #endif 452 case STEP_COMPUTE_COMMON_PARMS: 453 /* 454 * STEP 3: Compute a common set of timing parameters 455 * suitable for all of the DIMMs on each memory controller 456 */ 457 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 458 debug("Computing lowest common DIMM" 459 " parameters for memctl=%u\n", i); 460 compute_lowest_common_dimm_parameters( 461 pinfo->dimm_params[i], 462 &timing_params[i], 463 CONFIG_DIMM_SLOTS_PER_CTLR); 464 } 465 466 case STEP_GATHER_OPTS: 467 /* STEP 4: Gather configuration requirements from user */ 468 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 469 debug("Reloading memory controller " 470 "configuration options for memctl=%u\n", i); 471 /* 472 * This "reloads" the memory controller options 473 * to defaults. If the user "edits" an option, 474 * next_step points to the step after this, 475 * which is currently STEP_ASSIGN_ADDRESSES. 476 */ 477 populate_memctl_options( 478 timing_params[i].all_dimms_registered, 479 &pinfo->memctl_opts[i], 480 pinfo->dimm_params[i], i); 481 /* 482 * For RDIMMs, JEDEC spec requires clocks to be stable 483 * before reset signal is deasserted. For the boards 484 * using fixed parameters, this function should be 485 * be called from board init file. 486 */ 487 if (timing_params[i].all_dimms_registered) 488 assert_reset = 1; 489 } 490 if (assert_reset) { 491 debug("Asserting mem reset\n"); 492 board_assert_mem_reset(); 493 } 494 495 case STEP_ASSIGN_ADDRESSES: 496 /* STEP 5: Assign addresses to chip selects */ 497 check_interleaving_options(pinfo); 498 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); 499 500 case STEP_COMPUTE_REGS: 501 /* STEP 6: compute controller register values */ 502 debug("FSL Memory ctrl register computation\n"); 503 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 504 if (timing_params[i].ndimms_present == 0) { 505 memset(&ddr_reg[i], 0, 506 sizeof(fsl_ddr_cfg_regs_t)); 507 continue; 508 } 509 510 compute_fsl_memctl_config_regs( 511 &pinfo->memctl_opts[i], 512 &ddr_reg[i], &timing_params[i], 513 pinfo->dimm_params[i], 514 dbw_capacity_adjust[i], 515 size_only); 516 } 517 518 default: 519 break; 520 } 521 522 { 523 /* 524 * Compute the amount of memory available just by 525 * looking for the highest valid CSn_BNDS value. 526 * This allows us to also experiment with using 527 * only CS0 when using dual-rank DIMMs. 528 */ 529 unsigned int max_end = 0; 530 531 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 532 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { 533 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; 534 if (reg->cs[j].config & 0x80000000) { 535 unsigned int end; 536 /* 537 * 0xfffffff is a special value we put 538 * for unused bnds 539 */ 540 if (reg->cs[j].bnds == 0xffffffff) 541 continue; 542 end = reg->cs[j].bnds & 0xffff; 543 if (end > max_end) { 544 max_end = end; 545 } 546 } 547 } 548 } 549 550 total_mem = 1 + (((unsigned long long)max_end << 24ULL) | 551 0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; 552 } 553 554 return total_mem; 555 } 556 557 /* 558 * fsl_ddr_sdram() -- this is the main function to be called by 559 * initdram() in the board file. 560 * 561 * It returns amount of memory configured in bytes. 562 */ 563 phys_size_t fsl_ddr_sdram(void) 564 { 565 unsigned int i; 566 #ifdef CONFIG_PPC 567 unsigned int law_memctl = LAW_TRGT_IF_DDR_1; 568 #endif 569 unsigned long long total_memory; 570 fsl_ddr_info_t info; 571 int deassert_reset; 572 573 /* Reset info structure. */ 574 memset(&info, 0, sizeof(fsl_ddr_info_t)); 575 576 /* Compute it once normally. */ 577 #ifdef CONFIG_FSL_DDR_INTERACTIVE 578 if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */ 579 total_memory = fsl_ddr_interactive(&info, 0); 580 } else if (fsl_ddr_interactive_env_var_exists()) { 581 total_memory = fsl_ddr_interactive(&info, 1); 582 } else 583 #endif 584 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); 585 586 /* setup 3-way interleaving before enabling DDRC */ 587 if (info.memctl_opts[0].memctl_interleaving) { 588 switch (info.memctl_opts[0].memctl_interleaving_mode) { 589 case FSL_DDR_3WAY_1KB_INTERLEAVING: 590 case FSL_DDR_3WAY_4KB_INTERLEAVING: 591 case FSL_DDR_3WAY_8KB_INTERLEAVING: 592 fsl_ddr_set_intl3r( 593 info.memctl_opts[0].memctl_interleaving_mode); 594 break; 595 default: 596 break; 597 } 598 } 599 600 /* 601 * Program configuration registers. 602 * JEDEC specs requires clocks to be stable before deasserting reset 603 * for RDIMMs. Clocks start after chip select is enabled and clock 604 * control register is set. During step 1, all controllers have their 605 * registers set but not enabled. Step 2 proceeds after deasserting 606 * reset through board FPGA or GPIO. 607 * For non-registered DIMMs, initialization can go through but it is 608 * also OK to follow the same flow. 609 */ 610 deassert_reset = board_need_mem_reset(); 611 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 612 if (info.common_timing_params[i].all_dimms_registered) 613 deassert_reset = 1; 614 } 615 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 616 debug("Programming controller %u\n", i); 617 if (info.common_timing_params[i].ndimms_present == 0) { 618 debug("No dimms present on controller %u; " 619 "skipping programming\n", i); 620 continue; 621 } 622 /* 623 * The following call with step = 1 returns before enabling 624 * the controller. It has to finish with step = 2 later. 625 */ 626 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i, 627 deassert_reset ? 1 : 0); 628 } 629 if (deassert_reset) { 630 /* Use board FPGA or GPIO to deassert reset signal */ 631 debug("Deasserting mem reset\n"); 632 board_deassert_mem_reset(); 633 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 634 /* Call with step = 2 to continue initialization */ 635 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), 636 i, 2); 637 } 638 } 639 640 #ifdef CONFIG_PPC 641 /* program LAWs */ 642 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 643 if (info.memctl_opts[i].memctl_interleaving) { 644 switch (info.memctl_opts[i].memctl_interleaving_mode) { 645 case FSL_DDR_CACHE_LINE_INTERLEAVING: 646 case FSL_DDR_PAGE_INTERLEAVING: 647 case FSL_DDR_BANK_INTERLEAVING: 648 case FSL_DDR_SUPERBANK_INTERLEAVING: 649 if (i == 0) { 650 law_memctl = LAW_TRGT_IF_DDR_INTRLV; 651 fsl_ddr_set_lawbar(&info.common_timing_params[i], 652 law_memctl, i); 653 } else if (i == 2) { 654 law_memctl = LAW_TRGT_IF_DDR_INTLV_34; 655 fsl_ddr_set_lawbar(&info.common_timing_params[i], 656 law_memctl, i); 657 } 658 break; 659 case FSL_DDR_3WAY_1KB_INTERLEAVING: 660 case FSL_DDR_3WAY_4KB_INTERLEAVING: 661 case FSL_DDR_3WAY_8KB_INTERLEAVING: 662 law_memctl = LAW_TRGT_IF_DDR_INTLV_123; 663 if (i == 0) { 664 fsl_ddr_set_lawbar(&info.common_timing_params[i], 665 law_memctl, i); 666 } 667 break; 668 case FSL_DDR_4WAY_1KB_INTERLEAVING: 669 case FSL_DDR_4WAY_4KB_INTERLEAVING: 670 case FSL_DDR_4WAY_8KB_INTERLEAVING: 671 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; 672 if (i == 0) 673 fsl_ddr_set_lawbar(&info.common_timing_params[i], 674 law_memctl, i); 675 /* place holder for future 4-way interleaving */ 676 break; 677 default: 678 break; 679 } 680 } else { 681 switch (i) { 682 case 0: 683 law_memctl = LAW_TRGT_IF_DDR_1; 684 break; 685 case 1: 686 law_memctl = LAW_TRGT_IF_DDR_2; 687 break; 688 case 2: 689 law_memctl = LAW_TRGT_IF_DDR_3; 690 break; 691 case 3: 692 law_memctl = LAW_TRGT_IF_DDR_4; 693 break; 694 default: 695 break; 696 } 697 fsl_ddr_set_lawbar(&info.common_timing_params[i], 698 law_memctl, i); 699 } 700 } 701 #endif 702 703 debug("total_memory by %s = %llu\n", __func__, total_memory); 704 705 #if !defined(CONFIG_PHYS_64BIT) 706 /* Check for 4G or more. Bad. */ 707 if (total_memory >= (1ull << 32)) { 708 puts("Detected "); 709 print_size(total_memory, " of memory\n"); 710 printf(" This U-Boot only supports < 4G of DDR\n"); 711 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); 712 printf(" "); /* re-align to match init_func_ram print */ 713 total_memory = CONFIG_MAX_MEM_MAPPED; 714 } 715 #endif 716 717 return total_memory; 718 } 719 720 /* 721 * fsl_ddr_sdram_size() - This function only returns the size of the total 722 * memory without setting ddr control registers. 723 */ 724 phys_size_t 725 fsl_ddr_sdram_size(void) 726 { 727 fsl_ddr_info_t info; 728 unsigned long long total_memory = 0; 729 730 memset(&info, 0 , sizeof(fsl_ddr_info_t)); 731 732 /* Compute it once normally. */ 733 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); 734 735 return total_memory; 736 } 737