1 /* 2 * Copyright 2008-2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. 11 * Based on code from spd_sdram.c 12 * Author: James Yang [at freescale.com] 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <fsl_ddr_sdram.h> 18 #include <asm/fsl_law.h> 19 20 #include <fsl_ddr.h> 21 22 void fsl_ddr_set_lawbar( 23 const common_timing_params_t *memctl_common_params, 24 unsigned int memctl_interleaved, 25 unsigned int ctrl_num); 26 void fsl_ddr_set_intl3r(const unsigned int granule_size); 27 28 #if defined(SPD_EEPROM_ADDRESS) || \ 29 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ 30 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) 31 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 32 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 33 [0][0] = SPD_EEPROM_ADDRESS, 34 }; 35 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 36 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 37 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 38 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ 39 }; 40 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 41 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 42 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 43 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ 44 }; 45 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 46 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 47 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 48 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ 49 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ 50 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ 51 }; 52 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 53 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 54 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 55 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ 56 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ 57 }; 58 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 59 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { 60 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ 61 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ 62 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ 63 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ 64 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ 65 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ 66 }; 67 68 #endif 69 70 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) 71 { 72 int ret; 73 74 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); 75 76 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 77 sizeof(generic_spd_eeprom_t)); 78 79 if (ret) { 80 if (i2c_address == 81 #ifdef SPD_EEPROM_ADDRESS 82 SPD_EEPROM_ADDRESS 83 #elif defined(SPD_EEPROM_ADDRESS1) 84 SPD_EEPROM_ADDRESS1 85 #endif 86 ) { 87 printf("DDR: failed to read SPD from address %u\n", 88 i2c_address); 89 } else { 90 debug("DDR: failed to read SPD from address %u\n", 91 i2c_address); 92 } 93 memset(spd, 0, sizeof(generic_spd_eeprom_t)); 94 } 95 } 96 97 __attribute__((weak, alias("__get_spd"))) 98 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); 99 100 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 101 unsigned int ctrl_num) 102 { 103 unsigned int i; 104 unsigned int i2c_address = 0; 105 106 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { 107 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 108 return; 109 } 110 111 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 112 i2c_address = spd_i2c_addr[ctrl_num][i]; 113 get_spd(&(ctrl_dimms_spd[i]), i2c_address); 114 } 115 } 116 #else 117 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 118 unsigned int ctrl_num) 119 { 120 } 121 #endif /* SPD_EEPROM_ADDRESSx */ 122 123 /* 124 * ASSUMPTIONS: 125 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller 126 * - Same memory data bus width on all controllers 127 * 128 * NOTES: 129 * 130 * The memory controller and associated documentation use confusing 131 * terminology when referring to the orgranization of DRAM. 132 * 133 * Here is a terminology translation table: 134 * 135 * memory controller/documention |industry |this code |signals 136 * -------------------------------|-----------|-----------|----------------- 137 * physical bank/bank |rank |rank |chip select (CS) 138 * logical bank/sub-bank |bank |bank |bank address (BA) 139 * page/row |row |page |row address 140 * ??? |column |column |column address 141 * 142 * The naming confusion is further exacerbated by the descriptions of the 143 * memory controller interleaving feature, where accesses are interleaved 144 * _BETWEEN_ two seperate memory controllers. This is configured only in 145 * CS0_CONFIG[INTLV_CTL] of each memory controller. 146 * 147 * memory controller documentation | number of chip selects 148 * | per memory controller supported 149 * --------------------------------|----------------------------------------- 150 * cache line interleaving | 1 (CS0 only) 151 * page interleaving | 1 (CS0 only) 152 * bank interleaving | 1 (CS0 only) 153 * superbank interleraving | depends on bank (chip select) 154 * | interleraving [rank interleaving] 155 * | mode used on every memory controller 156 * 157 * Even further confusing is the existence of the interleaving feature 158 * _WITHIN_ each memory controller. The feature is referred to in 159 * documentation as chip select interleaving or bank interleaving, 160 * although it is configured in the DDR_SDRAM_CFG field. 161 * 162 * Name of field | documentation name | this code 163 * -----------------------------|-----------------------|------------------ 164 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving 165 * | interleaving 166 */ 167 168 const char *step_string_tbl[] = { 169 "STEP_GET_SPD", 170 "STEP_COMPUTE_DIMM_PARMS", 171 "STEP_COMPUTE_COMMON_PARMS", 172 "STEP_GATHER_OPTS", 173 "STEP_ASSIGN_ADDRESSES", 174 "STEP_COMPUTE_REGS", 175 "STEP_PROGRAM_REGS", 176 "STEP_ALL" 177 }; 178 179 const char * step_to_string(unsigned int step) { 180 181 unsigned int s = __ilog2(step); 182 183 if ((1 << s) != step) 184 return step_string_tbl[7]; 185 186 return step_string_tbl[s]; 187 } 188 189 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, 190 unsigned int dbw_cap_adj[]) 191 { 192 int i, j; 193 unsigned long long total_mem, current_mem_base, total_ctlr_mem; 194 unsigned long long rank_density, ctlr_density = 0; 195 196 /* 197 * If a reduced data width is requested, but the SPD 198 * specifies a physically wider device, adjust the 199 * computed dimm capacities accordingly before 200 * assigning addresses. 201 */ 202 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 203 unsigned int found = 0; 204 205 switch (pinfo->memctl_opts[i].data_bus_width) { 206 case 2: 207 /* 16-bit */ 208 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 209 unsigned int dw; 210 if (!pinfo->dimm_params[i][j].n_ranks) 211 continue; 212 dw = pinfo->dimm_params[i][j].primary_sdram_width; 213 if ((dw == 72 || dw == 64)) { 214 dbw_cap_adj[i] = 2; 215 break; 216 } else if ((dw == 40 || dw == 32)) { 217 dbw_cap_adj[i] = 1; 218 break; 219 } 220 } 221 break; 222 223 case 1: 224 /* 32-bit */ 225 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 226 unsigned int dw; 227 dw = pinfo->dimm_params[i][j].data_width; 228 if (pinfo->dimm_params[i][j].n_ranks 229 && (dw == 72 || dw == 64)) { 230 /* 231 * FIXME: can't really do it 232 * like this because this just 233 * further reduces the memory 234 */ 235 found = 1; 236 break; 237 } 238 } 239 if (found) { 240 dbw_cap_adj[i] = 1; 241 } 242 break; 243 244 case 0: 245 /* 64-bit */ 246 break; 247 248 default: 249 printf("unexpected data bus width " 250 "specified controller %u\n", i); 251 return 1; 252 } 253 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); 254 } 255 256 current_mem_base = 0ull; 257 total_mem = 0; 258 if (pinfo->memctl_opts[0].memctl_interleaving) { 259 rank_density = pinfo->dimm_params[0][0].rank_density >> 260 dbw_cap_adj[0]; 261 switch (pinfo->memctl_opts[0].ba_intlv_ctl & 262 FSL_DDR_CS0_CS1_CS2_CS3) { 263 case FSL_DDR_CS0_CS1_CS2_CS3: 264 ctlr_density = 4 * rank_density; 265 break; 266 case FSL_DDR_CS0_CS1: 267 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 268 ctlr_density = 2 * rank_density; 269 break; 270 case FSL_DDR_CS2_CS3: 271 default: 272 ctlr_density = rank_density; 273 break; 274 } 275 debug("rank density is 0x%llx, ctlr density is 0x%llx\n", 276 rank_density, ctlr_density); 277 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 278 if (pinfo->memctl_opts[i].memctl_interleaving) { 279 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { 280 case FSL_DDR_CACHE_LINE_INTERLEAVING: 281 case FSL_DDR_PAGE_INTERLEAVING: 282 case FSL_DDR_BANK_INTERLEAVING: 283 case FSL_DDR_SUPERBANK_INTERLEAVING: 284 total_ctlr_mem = 2 * ctlr_density; 285 break; 286 case FSL_DDR_3WAY_1KB_INTERLEAVING: 287 case FSL_DDR_3WAY_4KB_INTERLEAVING: 288 case FSL_DDR_3WAY_8KB_INTERLEAVING: 289 total_ctlr_mem = 3 * ctlr_density; 290 break; 291 case FSL_DDR_4WAY_1KB_INTERLEAVING: 292 case FSL_DDR_4WAY_4KB_INTERLEAVING: 293 case FSL_DDR_4WAY_8KB_INTERLEAVING: 294 total_ctlr_mem = 4 * ctlr_density; 295 break; 296 default: 297 panic("Unknown interleaving mode"); 298 } 299 pinfo->common_timing_params[i].base_address = 300 current_mem_base; 301 pinfo->common_timing_params[i].total_mem = 302 total_ctlr_mem; 303 total_mem = current_mem_base + total_ctlr_mem; 304 debug("ctrl %d base 0x%llx\n", i, current_mem_base); 305 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 306 } else { 307 /* when 3rd controller not interleaved */ 308 current_mem_base = total_mem; 309 total_ctlr_mem = 0; 310 pinfo->common_timing_params[i].base_address = 311 current_mem_base; 312 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 313 unsigned long long cap = 314 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; 315 pinfo->dimm_params[i][j].base_address = 316 current_mem_base; 317 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); 318 current_mem_base += cap; 319 total_ctlr_mem += cap; 320 } 321 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 322 pinfo->common_timing_params[i].total_mem = 323 total_ctlr_mem; 324 total_mem += total_ctlr_mem; 325 } 326 } 327 } else { 328 /* 329 * Simple linear assignment if memory 330 * controllers are not interleaved. 331 */ 332 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 333 total_ctlr_mem = 0; 334 pinfo->common_timing_params[i].base_address = 335 current_mem_base; 336 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 337 /* Compute DIMM base addresses. */ 338 unsigned long long cap = 339 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; 340 pinfo->dimm_params[i][j].base_address = 341 current_mem_base; 342 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); 343 current_mem_base += cap; 344 total_ctlr_mem += cap; 345 } 346 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 347 pinfo->common_timing_params[i].total_mem = 348 total_ctlr_mem; 349 total_mem += total_ctlr_mem; 350 } 351 } 352 debug("Total mem by %s is 0x%llx\n", __func__, total_mem); 353 354 return total_mem; 355 } 356 357 /* Use weak function to allow board file to override the address assignment */ 358 __attribute__((weak, alias("__step_assign_addresses"))) 359 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, 360 unsigned int dbw_cap_adj[]); 361 362 unsigned long long 363 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, 364 unsigned int size_only) 365 { 366 unsigned int i, j; 367 unsigned long long total_mem = 0; 368 int assert_reset; 369 370 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; 371 common_timing_params_t *timing_params = pinfo->common_timing_params; 372 assert_reset = board_need_mem_reset(); 373 374 /* data bus width capacity adjust shift amount */ 375 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; 376 377 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 378 dbw_capacity_adjust[i] = 0; 379 } 380 381 debug("starting at step %u (%s)\n", 382 start_step, step_to_string(start_step)); 383 384 switch (start_step) { 385 case STEP_GET_SPD: 386 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) 387 /* STEP 1: Gather all DIMM SPD data */ 388 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 389 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); 390 } 391 392 case STEP_COMPUTE_DIMM_PARMS: 393 /* STEP 2: Compute DIMM parameters from SPD data */ 394 395 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 396 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 397 unsigned int retval; 398 generic_spd_eeprom_t *spd = 399 &(pinfo->spd_installed_dimms[i][j]); 400 dimm_params_t *pdimm = 401 &(pinfo->dimm_params[i][j]); 402 403 retval = compute_dimm_parameters(spd, pdimm, i); 404 #ifdef CONFIG_SYS_DDR_RAW_TIMING 405 if (!i && !j && retval) { 406 printf("SPD error on controller %d! " 407 "Trying fallback to raw timing " 408 "calculation\n", i); 409 fsl_ddr_get_dimm_params(pdimm, i, j); 410 } 411 #else 412 if (retval == 2) { 413 printf("Error: compute_dimm_parameters" 414 " non-zero returned FATAL value " 415 "for memctl=%u dimm=%u\n", i, j); 416 return 0; 417 } 418 #endif 419 if (retval) { 420 debug("Warning: compute_dimm_parameters" 421 " non-zero return value for memctl=%u " 422 "dimm=%u\n", i, j); 423 } 424 } 425 } 426 427 #elif defined(CONFIG_SYS_DDR_RAW_TIMING) 428 case STEP_COMPUTE_DIMM_PARMS: 429 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 430 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 431 dimm_params_t *pdimm = 432 &(pinfo->dimm_params[i][j]); 433 fsl_ddr_get_dimm_params(pdimm, i, j); 434 } 435 } 436 debug("Filling dimm parameters from board specific file\n"); 437 #endif 438 case STEP_COMPUTE_COMMON_PARMS: 439 /* 440 * STEP 3: Compute a common set of timing parameters 441 * suitable for all of the DIMMs on each memory controller 442 */ 443 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 444 debug("Computing lowest common DIMM" 445 " parameters for memctl=%u\n", i); 446 compute_lowest_common_dimm_parameters( 447 pinfo->dimm_params[i], 448 &timing_params[i], 449 CONFIG_DIMM_SLOTS_PER_CTLR); 450 } 451 452 case STEP_GATHER_OPTS: 453 /* STEP 4: Gather configuration requirements from user */ 454 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 455 debug("Reloading memory controller " 456 "configuration options for memctl=%u\n", i); 457 /* 458 * This "reloads" the memory controller options 459 * to defaults. If the user "edits" an option, 460 * next_step points to the step after this, 461 * which is currently STEP_ASSIGN_ADDRESSES. 462 */ 463 populate_memctl_options( 464 timing_params[i].all_dimms_registered, 465 &pinfo->memctl_opts[i], 466 pinfo->dimm_params[i], i); 467 /* 468 * For RDIMMs, JEDEC spec requires clocks to be stable 469 * before reset signal is deasserted. For the boards 470 * using fixed parameters, this function should be 471 * be called from board init file. 472 */ 473 if (timing_params[i].all_dimms_registered) 474 assert_reset = 1; 475 } 476 if (assert_reset) { 477 debug("Asserting mem reset\n"); 478 board_assert_mem_reset(); 479 } 480 481 case STEP_ASSIGN_ADDRESSES: 482 /* STEP 5: Assign addresses to chip selects */ 483 check_interleaving_options(pinfo); 484 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); 485 486 case STEP_COMPUTE_REGS: 487 /* STEP 6: compute controller register values */ 488 debug("FSL Memory ctrl register computation\n"); 489 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 490 if (timing_params[i].ndimms_present == 0) { 491 memset(&ddr_reg[i], 0, 492 sizeof(fsl_ddr_cfg_regs_t)); 493 continue; 494 } 495 496 compute_fsl_memctl_config_regs( 497 &pinfo->memctl_opts[i], 498 &ddr_reg[i], &timing_params[i], 499 pinfo->dimm_params[i], 500 dbw_capacity_adjust[i], 501 size_only); 502 } 503 504 default: 505 break; 506 } 507 508 { 509 /* 510 * Compute the amount of memory available just by 511 * looking for the highest valid CSn_BNDS value. 512 * This allows us to also experiment with using 513 * only CS0 when using dual-rank DIMMs. 514 */ 515 unsigned int max_end = 0; 516 517 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 518 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { 519 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; 520 if (reg->cs[j].config & 0x80000000) { 521 unsigned int end; 522 /* 523 * 0xfffffff is a special value we put 524 * for unused bnds 525 */ 526 if (reg->cs[j].bnds == 0xffffffff) 527 continue; 528 end = reg->cs[j].bnds & 0xffff; 529 if (end > max_end) { 530 max_end = end; 531 } 532 } 533 } 534 } 535 536 total_mem = 1 + (((unsigned long long)max_end << 24ULL) 537 | 0xFFFFFFULL); 538 } 539 540 return total_mem; 541 } 542 543 /* 544 * fsl_ddr_sdram() -- this is the main function to be called by 545 * initdram() in the board file. 546 * 547 * It returns amount of memory configured in bytes. 548 */ 549 phys_size_t fsl_ddr_sdram(void) 550 { 551 unsigned int i; 552 unsigned int law_memctl = LAW_TRGT_IF_DDR_1; 553 unsigned long long total_memory; 554 fsl_ddr_info_t info; 555 int deassert_reset; 556 557 /* Reset info structure. */ 558 memset(&info, 0, sizeof(fsl_ddr_info_t)); 559 560 /* Compute it once normally. */ 561 #ifdef CONFIG_FSL_DDR_INTERACTIVE 562 if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */ 563 total_memory = fsl_ddr_interactive(&info, 0); 564 } else if (fsl_ddr_interactive_env_var_exists()) { 565 total_memory = fsl_ddr_interactive(&info, 1); 566 } else 567 #endif 568 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); 569 570 /* setup 3-way interleaving before enabling DDRC */ 571 if (info.memctl_opts[0].memctl_interleaving) { 572 switch (info.memctl_opts[0].memctl_interleaving_mode) { 573 case FSL_DDR_3WAY_1KB_INTERLEAVING: 574 case FSL_DDR_3WAY_4KB_INTERLEAVING: 575 case FSL_DDR_3WAY_8KB_INTERLEAVING: 576 fsl_ddr_set_intl3r( 577 info.memctl_opts[0].memctl_interleaving_mode); 578 break; 579 default: 580 break; 581 } 582 } 583 584 /* 585 * Program configuration registers. 586 * JEDEC specs requires clocks to be stable before deasserting reset 587 * for RDIMMs. Clocks start after chip select is enabled and clock 588 * control register is set. During step 1, all controllers have their 589 * registers set but not enabled. Step 2 proceeds after deasserting 590 * reset through board FPGA or GPIO. 591 * For non-registered DIMMs, initialization can go through but it is 592 * also OK to follow the same flow. 593 */ 594 deassert_reset = board_need_mem_reset(); 595 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 596 if (info.common_timing_params[i].all_dimms_registered) 597 deassert_reset = 1; 598 } 599 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 600 debug("Programming controller %u\n", i); 601 if (info.common_timing_params[i].ndimms_present == 0) { 602 debug("No dimms present on controller %u; " 603 "skipping programming\n", i); 604 continue; 605 } 606 /* 607 * The following call with step = 1 returns before enabling 608 * the controller. It has to finish with step = 2 later. 609 */ 610 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i, 611 deassert_reset ? 1 : 0); 612 } 613 if (deassert_reset) { 614 /* Use board FPGA or GPIO to deassert reset signal */ 615 debug("Deasserting mem reset\n"); 616 board_deassert_mem_reset(); 617 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 618 /* Call with step = 2 to continue initialization */ 619 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), 620 i, 2); 621 } 622 } 623 624 /* program LAWs */ 625 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 626 if (info.memctl_opts[i].memctl_interleaving) { 627 switch (info.memctl_opts[i].memctl_interleaving_mode) { 628 case FSL_DDR_CACHE_LINE_INTERLEAVING: 629 case FSL_DDR_PAGE_INTERLEAVING: 630 case FSL_DDR_BANK_INTERLEAVING: 631 case FSL_DDR_SUPERBANK_INTERLEAVING: 632 if (i == 0) { 633 law_memctl = LAW_TRGT_IF_DDR_INTRLV; 634 fsl_ddr_set_lawbar(&info.common_timing_params[i], 635 law_memctl, i); 636 } else if (i == 2) { 637 law_memctl = LAW_TRGT_IF_DDR_INTLV_34; 638 fsl_ddr_set_lawbar(&info.common_timing_params[i], 639 law_memctl, i); 640 } 641 break; 642 case FSL_DDR_3WAY_1KB_INTERLEAVING: 643 case FSL_DDR_3WAY_4KB_INTERLEAVING: 644 case FSL_DDR_3WAY_8KB_INTERLEAVING: 645 law_memctl = LAW_TRGT_IF_DDR_INTLV_123; 646 if (i == 0) { 647 fsl_ddr_set_lawbar(&info.common_timing_params[i], 648 law_memctl, i); 649 } 650 break; 651 case FSL_DDR_4WAY_1KB_INTERLEAVING: 652 case FSL_DDR_4WAY_4KB_INTERLEAVING: 653 case FSL_DDR_4WAY_8KB_INTERLEAVING: 654 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; 655 if (i == 0) 656 fsl_ddr_set_lawbar(&info.common_timing_params[i], 657 law_memctl, i); 658 /* place holder for future 4-way interleaving */ 659 break; 660 default: 661 break; 662 } 663 } else { 664 switch (i) { 665 case 0: 666 law_memctl = LAW_TRGT_IF_DDR_1; 667 break; 668 case 1: 669 law_memctl = LAW_TRGT_IF_DDR_2; 670 break; 671 case 2: 672 law_memctl = LAW_TRGT_IF_DDR_3; 673 break; 674 case 3: 675 law_memctl = LAW_TRGT_IF_DDR_4; 676 break; 677 default: 678 break; 679 } 680 fsl_ddr_set_lawbar(&info.common_timing_params[i], 681 law_memctl, i); 682 } 683 } 684 685 debug("total_memory by %s = %llu\n", __func__, total_memory); 686 687 #if !defined(CONFIG_PHYS_64BIT) 688 /* Check for 4G or more. Bad. */ 689 if (total_memory >= (1ull << 32)) { 690 puts("Detected "); 691 print_size(total_memory, " of memory\n"); 692 printf(" This U-Boot only supports < 4G of DDR\n"); 693 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); 694 printf(" "); /* re-align to match init_func_ram print */ 695 total_memory = CONFIG_MAX_MEM_MAPPED; 696 } 697 #endif 698 699 return total_memory; 700 } 701 702 /* 703 * fsl_ddr_sdram_size() - This function only returns the size of the total 704 * memory without setting ddr control registers. 705 */ 706 phys_size_t 707 fsl_ddr_sdram_size(void) 708 { 709 fsl_ddr_info_t info; 710 unsigned long long total_memory = 0; 711 712 memset(&info, 0 , sizeof(fsl_ddr_info_t)); 713 714 /* Compute it once normally. */ 715 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); 716 717 return total_memory; 718 } 719