1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <fsl_ddr_sdram.h> 11 12 #include <fsl_ddr.h> 13 14 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 15 static unsigned int 16 compute_cas_latency(const unsigned int ctrl_num, 17 const dimm_params_t *dimm_params, 18 common_timing_params_t *outpdimm, 19 unsigned int number_of_dimms) 20 { 21 unsigned int i; 22 unsigned int common_caslat; 23 unsigned int caslat_actual; 24 unsigned int retry = 16; 25 unsigned int tmp = ~0; 26 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); 27 #ifdef CONFIG_SYS_FSL_DDR3 28 const unsigned int taamax = 20000; 29 #else 30 const unsigned int taamax = 18000; 31 #endif 32 33 /* compute the common CAS latency supported between slots */ 34 for (i = 0; i < number_of_dimms; i++) { 35 if (dimm_params[i].n_ranks) 36 tmp &= dimm_params[i].caslat_x; 37 } 38 common_caslat = tmp; 39 40 /* validate if the memory clk is in the range of dimms */ 41 if (mclk_ps < outpdimm->tckmin_x_ps) { 42 printf("DDR clock (MCLK cycle %u ps) is faster than " 43 "the slowest DIMM(s) (tCKmin %u ps) can support.\n", 44 mclk_ps, outpdimm->tckmin_x_ps); 45 } 46 #ifdef CONFIG_SYS_FSL_DDR4 47 if (mclk_ps > outpdimm->tckmax_ps) { 48 printf("DDR clock (MCLK cycle %u ps) is slower than DIMM(s) (tCKmax %u ps) can support.\n", 49 mclk_ps, outpdimm->tckmax_ps); 50 } 51 #endif 52 /* determine the acutal cas latency */ 53 caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps; 54 /* check if the dimms support the CAS latency */ 55 while (!(common_caslat & (1 << caslat_actual)) && retry > 0) { 56 caslat_actual++; 57 retry--; 58 } 59 /* once the caculation of caslat_actual is completed 60 * we must verify that this CAS latency value does not 61 * exceed tAAmax, which is 20 ns for all DDR3 speed grades, 62 * 18ns for all DDR4 speed grades. 63 */ 64 if (caslat_actual * mclk_ps > taamax) { 65 printf("The choosen cas latency %d is too large\n", 66 caslat_actual); 67 } 68 outpdimm->lowest_common_spd_caslat = caslat_actual; 69 debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual); 70 71 return 0; 72 } 73 #else /* for DDR1 and DDR2 */ 74 static unsigned int 75 compute_cas_latency(const unsigned int ctrl_num, 76 const dimm_params_t *dimm_params, 77 common_timing_params_t *outpdimm, 78 unsigned int number_of_dimms) 79 { 80 int i; 81 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); 82 unsigned int lowest_good_caslat; 83 unsigned int not_ok; 84 unsigned int temp1, temp2; 85 86 debug("using mclk_ps = %u\n", mclk_ps); 87 if (mclk_ps > outpdimm->tckmax_ps) { 88 printf("Warning: DDR clock (%u ps) is slower than DIMM(s) (tCKmax %u ps)\n", 89 mclk_ps, outpdimm->tckmax_ps); 90 } 91 92 /* 93 * Compute a CAS latency suitable for all DIMMs 94 * 95 * Strategy for SPD-defined latencies: compute only 96 * CAS latency defined by all DIMMs. 97 */ 98 99 /* 100 * Step 1: find CAS latency common to all DIMMs using bitwise 101 * operation. 102 */ 103 temp1 = 0xFF; 104 for (i = 0; i < number_of_dimms; i++) { 105 if (dimm_params[i].n_ranks) { 106 temp2 = 0; 107 temp2 |= 1 << dimm_params[i].caslat_x; 108 temp2 |= 1 << dimm_params[i].caslat_x_minus_1; 109 temp2 |= 1 << dimm_params[i].caslat_x_minus_2; 110 /* 111 * If there was no entry for X-2 (X-1) in 112 * the SPD, then caslat_x_minus_2 113 * (caslat_x_minus_1) contains either 255 or 114 * 0xFFFFFFFF because that's what the glorious 115 * __ilog2 function returns for an input of 0. 116 * On 32-bit PowerPC, left shift counts with bit 117 * 26 set (that the value of 255 or 0xFFFFFFFF 118 * will have), cause the destination register to 119 * be 0. That is why this works. 120 */ 121 temp1 &= temp2; 122 } 123 } 124 125 /* 126 * Step 2: check each common CAS latency against tCK of each 127 * DIMM's SPD. 128 */ 129 lowest_good_caslat = 0; 130 temp2 = 0; 131 while (temp1) { 132 not_ok = 0; 133 temp2 = __ilog2(temp1); 134 debug("checking common caslat = %u\n", temp2); 135 136 /* Check if this CAS latency will work on all DIMMs at tCK. */ 137 for (i = 0; i < number_of_dimms; i++) { 138 if (!dimm_params[i].n_ranks) 139 continue; 140 141 if (dimm_params[i].caslat_x == temp2) { 142 if (mclk_ps >= dimm_params[i].tckmin_x_ps) { 143 debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n", 144 temp2, i, mclk_ps, 145 dimm_params[i].tckmin_x_ps); 146 continue; 147 } else { 148 not_ok++; 149 } 150 } 151 152 if (dimm_params[i].caslat_x_minus_1 == temp2) { 153 unsigned int tckmin_x_minus_1_ps 154 = dimm_params[i].tckmin_x_minus_1_ps; 155 if (mclk_ps >= tckmin_x_minus_1_ps) { 156 debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n", 157 temp2, i, mclk_ps, 158 tckmin_x_minus_1_ps); 159 continue; 160 } else { 161 not_ok++; 162 } 163 } 164 165 if (dimm_params[i].caslat_x_minus_2 == temp2) { 166 unsigned int tckmin_x_minus_2_ps 167 = dimm_params[i].tckmin_x_minus_2_ps; 168 if (mclk_ps >= tckmin_x_minus_2_ps) { 169 debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n", 170 temp2, i, mclk_ps, 171 tckmin_x_minus_2_ps); 172 continue; 173 } else { 174 not_ok++; 175 } 176 } 177 } 178 179 if (!not_ok) 180 lowest_good_caslat = temp2; 181 182 temp1 &= ~(1 << temp2); 183 } 184 185 debug("lowest common SPD-defined CAS latency = %u\n", 186 lowest_good_caslat); 187 outpdimm->lowest_common_spd_caslat = lowest_good_caslat; 188 189 190 /* 191 * Compute a common 'de-rated' CAS latency. 192 * 193 * The strategy here is to find the *highest* dereated cas latency 194 * with the assumption that all of the DIMMs will support a dereated 195 * CAS latency higher than or equal to their lowest dereated value. 196 */ 197 temp1 = 0; 198 for (i = 0; i < number_of_dimms; i++) 199 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated); 200 201 outpdimm->highest_common_derated_caslat = temp1; 202 debug("highest common dereated CAS latency = %u\n", temp1); 203 204 return 0; 205 } 206 #endif 207 208 /* 209 * compute_lowest_common_dimm_parameters() 210 * 211 * Determine the worst-case DIMM timing parameters from the set of DIMMs 212 * whose parameters have been computed into the array pointed to 213 * by dimm_params. 214 */ 215 unsigned int 216 compute_lowest_common_dimm_parameters(const unsigned int ctrl_num, 217 const dimm_params_t *dimm_params, 218 common_timing_params_t *outpdimm, 219 const unsigned int number_of_dimms) 220 { 221 unsigned int i, j; 222 223 unsigned int tckmin_x_ps = 0; 224 unsigned int tckmax_ps = 0xFFFFFFFF; 225 unsigned int trcd_ps = 0; 226 unsigned int trp_ps = 0; 227 unsigned int tras_ps = 0; 228 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 229 unsigned int taamin_ps = 0; 230 #endif 231 #ifdef CONFIG_SYS_FSL_DDR4 232 unsigned int twr_ps = 15000; 233 unsigned int trfc1_ps = 0; 234 unsigned int trfc2_ps = 0; 235 unsigned int trfc4_ps = 0; 236 unsigned int trrds_ps = 0; 237 unsigned int trrdl_ps = 0; 238 unsigned int tccdl_ps = 0; 239 #else 240 unsigned int twr_ps = 0; 241 unsigned int twtr_ps = 0; 242 unsigned int trfc_ps = 0; 243 unsigned int trrd_ps = 0; 244 unsigned int trtp_ps = 0; 245 #endif 246 unsigned int trc_ps = 0; 247 unsigned int refresh_rate_ps = 0; 248 unsigned int extended_op_srt = 1; 249 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 250 unsigned int tis_ps = 0; 251 unsigned int tih_ps = 0; 252 unsigned int tds_ps = 0; 253 unsigned int tdh_ps = 0; 254 unsigned int tdqsq_max_ps = 0; 255 unsigned int tqhs_ps = 0; 256 #endif 257 unsigned int temp1, temp2; 258 unsigned int additive_latency = 0; 259 260 temp1 = 0; 261 for (i = 0; i < number_of_dimms; i++) { 262 /* 263 * If there are no ranks on this DIMM, 264 * it probably doesn't exist, so skip it. 265 */ 266 if (dimm_params[i].n_ranks == 0) { 267 temp1++; 268 continue; 269 } 270 if (dimm_params[i].n_ranks == 4 && i != 0) { 271 printf("Found Quad-rank DIMM in wrong bank, ignored." 272 " Software may not run as expected.\n"); 273 temp1++; 274 continue; 275 } 276 277 /* 278 * check if quad-rank DIMM is plugged if 279 * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined 280 * Only the board with proper design is capable 281 */ 282 #ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 283 if (dimm_params[i].n_ranks == 4 && \ 284 CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) { 285 printf("Found Quad-rank DIMM, not able to support."); 286 temp1++; 287 continue; 288 } 289 #endif 290 /* 291 * Find minimum tckmax_ps to find fastest slow speed, 292 * i.e., this is the slowest the whole system can go. 293 */ 294 tckmax_ps = min(tckmax_ps, 295 (unsigned int)dimm_params[i].tckmax_ps); 296 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 297 taamin_ps = max(taamin_ps, 298 (unsigned int)dimm_params[i].taa_ps); 299 #endif 300 tckmin_x_ps = max(tckmin_x_ps, 301 (unsigned int)dimm_params[i].tckmin_x_ps); 302 trcd_ps = max(trcd_ps, (unsigned int)dimm_params[i].trcd_ps); 303 trp_ps = max(trp_ps, (unsigned int)dimm_params[i].trp_ps); 304 tras_ps = max(tras_ps, (unsigned int)dimm_params[i].tras_ps); 305 #ifdef CONFIG_SYS_FSL_DDR4 306 trfc1_ps = max(trfc1_ps, 307 (unsigned int)dimm_params[i].trfc1_ps); 308 trfc2_ps = max(trfc2_ps, 309 (unsigned int)dimm_params[i].trfc2_ps); 310 trfc4_ps = max(trfc4_ps, 311 (unsigned int)dimm_params[i].trfc4_ps); 312 trrds_ps = max(trrds_ps, 313 (unsigned int)dimm_params[i].trrds_ps); 314 trrdl_ps = max(trrdl_ps, 315 (unsigned int)dimm_params[i].trrdl_ps); 316 tccdl_ps = max(tccdl_ps, 317 (unsigned int)dimm_params[i].tccdl_ps); 318 #else 319 twr_ps = max(twr_ps, (unsigned int)dimm_params[i].twr_ps); 320 twtr_ps = max(twtr_ps, (unsigned int)dimm_params[i].twtr_ps); 321 trfc_ps = max(trfc_ps, (unsigned int)dimm_params[i].trfc_ps); 322 trrd_ps = max(trrd_ps, (unsigned int)dimm_params[i].trrd_ps); 323 trtp_ps = max(trtp_ps, (unsigned int)dimm_params[i].trtp_ps); 324 #endif 325 trc_ps = max(trc_ps, (unsigned int)dimm_params[i].trc_ps); 326 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 327 tis_ps = max(tis_ps, (unsigned int)dimm_params[i].tis_ps); 328 tih_ps = max(tih_ps, (unsigned int)dimm_params[i].tih_ps); 329 tds_ps = max(tds_ps, (unsigned int)dimm_params[i].tds_ps); 330 tdh_ps = max(tdh_ps, (unsigned int)dimm_params[i].tdh_ps); 331 tqhs_ps = max(tqhs_ps, (unsigned int)dimm_params[i].tqhs_ps); 332 /* 333 * Find maximum tdqsq_max_ps to find slowest. 334 * 335 * FIXME: is finding the slowest value the correct 336 * strategy for this parameter? 337 */ 338 tdqsq_max_ps = max(tdqsq_max_ps, 339 (unsigned int)dimm_params[i].tdqsq_max_ps); 340 #endif 341 refresh_rate_ps = max(refresh_rate_ps, 342 (unsigned int)dimm_params[i].refresh_rate_ps); 343 /* extended_op_srt is either 0 or 1, 0 having priority */ 344 extended_op_srt = min(extended_op_srt, 345 (unsigned int)dimm_params[i].extended_op_srt); 346 } 347 348 outpdimm->ndimms_present = number_of_dimms - temp1; 349 350 if (temp1 == number_of_dimms) { 351 debug("no dimms this memory controller\n"); 352 return 0; 353 } 354 355 outpdimm->tckmin_x_ps = tckmin_x_ps; 356 outpdimm->tckmax_ps = tckmax_ps; 357 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 358 outpdimm->taamin_ps = taamin_ps; 359 #endif 360 outpdimm->trcd_ps = trcd_ps; 361 outpdimm->trp_ps = trp_ps; 362 outpdimm->tras_ps = tras_ps; 363 #ifdef CONFIG_SYS_FSL_DDR4 364 outpdimm->trfc1_ps = trfc1_ps; 365 outpdimm->trfc2_ps = trfc2_ps; 366 outpdimm->trfc4_ps = trfc4_ps; 367 outpdimm->trrds_ps = trrds_ps; 368 outpdimm->trrdl_ps = trrdl_ps; 369 outpdimm->tccdl_ps = tccdl_ps; 370 #else 371 outpdimm->twtr_ps = twtr_ps; 372 outpdimm->trfc_ps = trfc_ps; 373 outpdimm->trrd_ps = trrd_ps; 374 outpdimm->trtp_ps = trtp_ps; 375 #endif 376 outpdimm->twr_ps = twr_ps; 377 outpdimm->trc_ps = trc_ps; 378 outpdimm->refresh_rate_ps = refresh_rate_ps; 379 outpdimm->extended_op_srt = extended_op_srt; 380 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 381 outpdimm->tis_ps = tis_ps; 382 outpdimm->tih_ps = tih_ps; 383 outpdimm->tds_ps = tds_ps; 384 outpdimm->tdh_ps = tdh_ps; 385 outpdimm->tdqsq_max_ps = tdqsq_max_ps; 386 outpdimm->tqhs_ps = tqhs_ps; 387 #endif 388 389 /* Determine common burst length for all DIMMs. */ 390 temp1 = 0xff; 391 for (i = 0; i < number_of_dimms; i++) { 392 if (dimm_params[i].n_ranks) { 393 temp1 &= dimm_params[i].burst_lengths_bitmask; 394 } 395 } 396 outpdimm->all_dimms_burst_lengths_bitmask = temp1; 397 398 /* Determine if all DIMMs registered buffered. */ 399 temp1 = temp2 = 0; 400 for (i = 0; i < number_of_dimms; i++) { 401 if (dimm_params[i].n_ranks) { 402 if (dimm_params[i].registered_dimm) { 403 temp1 = 1; 404 #ifndef CONFIG_SPL_BUILD 405 printf("Detected RDIMM %s\n", 406 dimm_params[i].mpart); 407 #endif 408 } else { 409 temp2 = 1; 410 #ifndef CONFIG_SPL_BUILD 411 printf("Detected UDIMM %s\n", 412 dimm_params[i].mpart); 413 #endif 414 } 415 } 416 } 417 418 outpdimm->all_dimms_registered = 0; 419 outpdimm->all_dimms_unbuffered = 0; 420 if (temp1 && !temp2) { 421 outpdimm->all_dimms_registered = 1; 422 } else if (!temp1 && temp2) { 423 outpdimm->all_dimms_unbuffered = 1; 424 } else { 425 printf("ERROR: Mix of registered buffered and unbuffered " 426 "DIMMs detected!\n"); 427 } 428 429 temp1 = 0; 430 if (outpdimm->all_dimms_registered) 431 for (j = 0; j < 16; j++) { 432 outpdimm->rcw[j] = dimm_params[0].rcw[j]; 433 for (i = 1; i < number_of_dimms; i++) { 434 if (!dimm_params[i].n_ranks) 435 continue; 436 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) { 437 temp1 = 1; 438 break; 439 } 440 } 441 } 442 443 if (temp1 != 0) 444 printf("ERROR: Mix different RDIMM detected!\n"); 445 446 /* calculate cas latency for all DDR types */ 447 if (compute_cas_latency(ctrl_num, dimm_params, 448 outpdimm, number_of_dimms)) 449 return 1; 450 451 /* Determine if all DIMMs ECC capable. */ 452 temp1 = 1; 453 for (i = 0; i < number_of_dimms; i++) { 454 if (dimm_params[i].n_ranks && 455 !(dimm_params[i].edc_config & EDC_ECC)) { 456 temp1 = 0; 457 break; 458 } 459 } 460 if (temp1) { 461 debug("all DIMMs ECC capable\n"); 462 } else { 463 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n"); 464 } 465 outpdimm->all_dimms_ecc_capable = temp1; 466 467 /* 468 * Compute additive latency. 469 * 470 * For DDR1, additive latency should be 0. 471 * 472 * For DDR2, with ODT enabled, use "a value" less than ACTTORW, 473 * which comes from Trcd, and also note that: 474 * add_lat + caslat must be >= 4 475 * 476 * For DDR3, we use the AL=0 477 * 478 * When to use additive latency for DDR2: 479 * 480 * I. Because you are using CL=3 and need to do ODT on writes and 481 * want functionality. 482 * 1. Are you going to use ODT? (Does your board not have 483 * additional termination circuitry for DQ, DQS, DQS_, 484 * DM, RDQS, RDQS_ for x4/x8 configs?) 485 * 2. If so, is your lowest supported CL going to be 3? 486 * 3. If so, then you must set AL=1 because 487 * 488 * WL >= 3 for ODT on writes 489 * RL = AL + CL 490 * WL = RL - 1 491 * -> 492 * WL = AL + CL - 1 493 * AL + CL - 1 >= 3 494 * AL + CL >= 4 495 * QED 496 * 497 * RL >= 3 for ODT on reads 498 * RL = AL + CL 499 * 500 * Since CL aren't usually less than 2, AL=0 is a minimum, 501 * so the WL-derived AL should be the -- FIXME? 502 * 503 * II. Because you are using auto-precharge globally and want to 504 * use additive latency (posted CAS) to get more bandwidth. 505 * 1. Are you going to use auto-precharge mode globally? 506 * 507 * Use addtivie latency and compute AL to be 1 cycle less than 508 * tRCD, i.e. the READ or WRITE command is in the cycle 509 * immediately following the ACTIVATE command.. 510 * 511 * III. Because you feel like it or want to do some sort of 512 * degraded-performance experiment. 513 * 1. Do you just want to use additive latency because you feel 514 * like it? 515 * 516 * Validation: AL is less than tRCD, and within the other 517 * read-to-precharge constraints. 518 */ 519 520 additive_latency = 0; 521 522 #if defined(CONFIG_SYS_FSL_DDR2) 523 if ((outpdimm->lowest_common_spd_caslat < 4) && 524 (picos_to_mclk(ctrl_num, trcd_ps) > 525 outpdimm->lowest_common_spd_caslat)) { 526 additive_latency = picos_to_mclk(ctrl_num, trcd_ps) - 527 outpdimm->lowest_common_spd_caslat; 528 if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) { 529 additive_latency = picos_to_mclk(ctrl_num, trcd_ps); 530 debug("setting additive_latency to %u because it was " 531 " greater than tRCD_ps\n", additive_latency); 532 } 533 } 534 #endif 535 536 /* 537 * Validate additive latency 538 * 539 * AL <= tRCD(min) 540 */ 541 if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) { 542 printf("Error: invalid additive latency exceeds tRCD(min).\n"); 543 return 1; 544 } 545 546 /* 547 * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled 548 * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled 549 * ADD_LAT (the register) must be set to a value less 550 * than ACTTORW if WL = 1, then AL must be set to 1 551 * RD_TO_PRE (the register) must be set to a minimum 552 * tRTP + AL if AL is nonzero 553 */ 554 555 /* 556 * Additive latency will be applied only if the memctl option to 557 * use it. 558 */ 559 outpdimm->additive_latency = additive_latency; 560 561 debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps); 562 debug("trcd_ps = %u\n", outpdimm->trcd_ps); 563 debug("trp_ps = %u\n", outpdimm->trp_ps); 564 debug("tras_ps = %u\n", outpdimm->tras_ps); 565 #ifdef CONFIG_SYS_FSL_DDR4 566 debug("trfc1_ps = %u\n", trfc1_ps); 567 debug("trfc2_ps = %u\n", trfc2_ps); 568 debug("trfc4_ps = %u\n", trfc4_ps); 569 debug("trrds_ps = %u\n", trrds_ps); 570 debug("trrdl_ps = %u\n", trrdl_ps); 571 debug("tccdl_ps = %u\n", tccdl_ps); 572 #else 573 debug("twtr_ps = %u\n", outpdimm->twtr_ps); 574 debug("trfc_ps = %u\n", outpdimm->trfc_ps); 575 debug("trrd_ps = %u\n", outpdimm->trrd_ps); 576 #endif 577 debug("twr_ps = %u\n", outpdimm->twr_ps); 578 debug("trc_ps = %u\n", outpdimm->trc_ps); 579 580 return 0; 581 } 582