1 /* 2 * Copyright 2010-2016 Freescale Semiconductor, Inc. 3 * Copyright 2017-2018 NXP Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. 10 * Based on code from spd_sdram.c 11 * Author: James Yang [at freescale.com] 12 * York Sun [at freescale.com] 13 */ 14 15 #include <common.h> 16 #include <cli.h> 17 #include <linux/ctype.h> 18 #include <asm/types.h> 19 #include <asm/io.h> 20 21 #include <fsl_ddr_sdram.h> 22 #include <fsl_ddr.h> 23 24 /* Option parameter Structures */ 25 struct options_string { 26 const char *option_name; 27 size_t offset; 28 unsigned int size; 29 const char printhex; 30 }; 31 32 static unsigned int picos_to_mhz(unsigned int picos) 33 { 34 return 1000000 / picos; 35 } 36 37 static void print_option_table(const struct options_string *table, 38 int table_size, 39 const void *base) 40 { 41 unsigned int i; 42 unsigned int *ptr; 43 unsigned long long *ptr_l; 44 45 for (i = 0; i < table_size; i++) { 46 switch (table[i].size) { 47 case 4: 48 ptr = (unsigned int *) (base + table[i].offset); 49 if (table[i].printhex) { 50 printf("%s = 0x%08X\n", 51 table[i].option_name, *ptr); 52 } else { 53 printf("%s = %u\n", 54 table[i].option_name, *ptr); 55 } 56 break; 57 case 8: 58 ptr_l = (unsigned long long *) (base + table[i].offset); 59 printf("%s = %llu\n", 60 table[i].option_name, *ptr_l); 61 break; 62 default: 63 printf("Unrecognized size!\n"); 64 break; 65 } 66 } 67 } 68 69 static int handle_option_table(const struct options_string *table, 70 int table_size, 71 void *base, 72 const char *opt, 73 const char *val) 74 { 75 unsigned int i; 76 unsigned int value, *ptr; 77 unsigned long long value_l, *ptr_l; 78 79 for (i = 0; i < table_size; i++) { 80 if (strcmp(table[i].option_name, opt) != 0) 81 continue; 82 switch (table[i].size) { 83 case 4: 84 value = simple_strtoul(val, NULL, 0); 85 ptr = base + table[i].offset; 86 *ptr = value; 87 break; 88 case 8: 89 value_l = simple_strtoull(val, NULL, 0); 90 ptr_l = base + table[i].offset; 91 *ptr_l = value_l; 92 break; 93 default: 94 printf("Unrecognized size!\n"); 95 break; 96 } 97 return 1; 98 } 99 100 return 0; 101 } 102 103 static void fsl_ddr_generic_edit(void *pdata, 104 void *pend, 105 unsigned int element_size, 106 unsigned int element_num, 107 unsigned int value) 108 { 109 char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */ 110 111 pcdata += element_num * element_size; 112 if ((pcdata + element_size) > (char *) pend) { 113 printf("trying to write past end of data\n"); 114 return; 115 } 116 117 switch (element_size) { 118 case 1: 119 __raw_writeb(value, pcdata); 120 break; 121 case 2: 122 __raw_writew(value, pcdata); 123 break; 124 case 4: 125 __raw_writel(value, pcdata); 126 break; 127 default: 128 printf("unexpected element size %u\n", element_size); 129 break; 130 } 131 } 132 133 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo, 134 unsigned int ctrl_num, 135 unsigned int dimm_num, 136 unsigned int element_num, 137 unsigned int value) 138 { 139 generic_spd_eeprom_t *pspd; 140 141 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); 142 fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value); 143 } 144 145 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \ 146 sizeof((common_timing_params_t *)0)->x, 0} 147 148 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, 149 unsigned int ctrl_num, 150 const char *optname_str, 151 const char *value_str) 152 { 153 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; 154 155 static const struct options_string options[] = { 156 COMMON_TIMING(tckmin_x_ps), 157 COMMON_TIMING(tckmax_ps), 158 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 159 COMMON_TIMING(taamin_ps), 160 #endif 161 COMMON_TIMING(trcd_ps), 162 COMMON_TIMING(trp_ps), 163 COMMON_TIMING(tras_ps), 164 165 #ifdef CONFIG_SYS_FSL_DDR4 166 COMMON_TIMING(trfc1_ps), 167 COMMON_TIMING(trfc2_ps), 168 COMMON_TIMING(trfc4_ps), 169 COMMON_TIMING(trrds_ps), 170 COMMON_TIMING(trrdl_ps), 171 COMMON_TIMING(tccdl_ps), 172 COMMON_TIMING(trfc_slr_ps), 173 #else 174 COMMON_TIMING(twtr_ps), 175 COMMON_TIMING(trfc_ps), 176 COMMON_TIMING(trrd_ps), 177 COMMON_TIMING(trtp_ps), 178 #endif 179 COMMON_TIMING(twr_ps), 180 COMMON_TIMING(trc_ps), 181 COMMON_TIMING(refresh_rate_ps), 182 COMMON_TIMING(extended_op_srt), 183 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 184 COMMON_TIMING(tis_ps), 185 COMMON_TIMING(tih_ps), 186 COMMON_TIMING(tds_ps), 187 COMMON_TIMING(tdh_ps), 188 COMMON_TIMING(tdqsq_max_ps), 189 COMMON_TIMING(tqhs_ps), 190 #endif 191 COMMON_TIMING(ndimms_present), 192 COMMON_TIMING(lowest_common_spd_caslat), 193 COMMON_TIMING(highest_common_derated_caslat), 194 COMMON_TIMING(additive_latency), 195 COMMON_TIMING(all_dimms_burst_lengths_bitmask), 196 COMMON_TIMING(all_dimms_registered), 197 COMMON_TIMING(all_dimms_unbuffered), 198 COMMON_TIMING(all_dimms_ecc_capable), 199 COMMON_TIMING(total_mem), 200 COMMON_TIMING(base_address), 201 }; 202 static const unsigned int n_opts = ARRAY_SIZE(options); 203 204 if (handle_option_table(options, n_opts, p, optname_str, value_str)) 205 return; 206 207 printf("Error: couldn't find option string %s\n", optname_str); 208 } 209 210 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \ 211 sizeof((dimm_params_t *)0)->x, 0} 212 #define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \ 213 sizeof((dimm_params_t *)0)->x, 1} 214 215 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, 216 unsigned int ctrl_num, 217 unsigned int dimm_num, 218 const char *optname_str, 219 const char *value_str) 220 { 221 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); 222 223 static const struct options_string options[] = { 224 DIMM_PARM(n_ranks), 225 DIMM_PARM(data_width), 226 DIMM_PARM(primary_sdram_width), 227 DIMM_PARM(ec_sdram_width), 228 DIMM_PARM(package_3ds), 229 DIMM_PARM(registered_dimm), 230 DIMM_PARM(mirrored_dimm), 231 DIMM_PARM(device_width), 232 233 DIMM_PARM(n_row_addr), 234 DIMM_PARM(n_col_addr), 235 DIMM_PARM(edc_config), 236 #ifdef CONFIG_SYS_FSL_DDR4 237 DIMM_PARM(bank_addr_bits), 238 DIMM_PARM(bank_group_bits), 239 DIMM_PARM_HEX(die_density), 240 #else 241 DIMM_PARM(n_banks_per_sdram_device), 242 #endif 243 DIMM_PARM(burst_lengths_bitmask), 244 245 DIMM_PARM(tckmin_x_ps), 246 DIMM_PARM(tckmin_x_minus_1_ps), 247 DIMM_PARM(tckmin_x_minus_2_ps), 248 DIMM_PARM(tckmax_ps), 249 250 DIMM_PARM(caslat_x), 251 DIMM_PARM(caslat_x_minus_1), 252 DIMM_PARM(caslat_x_minus_2), 253 254 DIMM_PARM(caslat_lowest_derated), 255 256 DIMM_PARM(trcd_ps), 257 DIMM_PARM(trp_ps), 258 DIMM_PARM(tras_ps), 259 #ifdef CONFIG_SYS_FSL_DDR4 260 DIMM_PARM(trfc1_ps), 261 DIMM_PARM(trfc2_ps), 262 DIMM_PARM(trfc4_ps), 263 DIMM_PARM(trrds_ps), 264 DIMM_PARM(trrdl_ps), 265 DIMM_PARM(tccdl_ps), 266 DIMM_PARM(trfc_slr_ps), 267 #else 268 DIMM_PARM(twr_ps), 269 DIMM_PARM(twtr_ps), 270 DIMM_PARM(trfc_ps), 271 DIMM_PARM(trrd_ps), 272 DIMM_PARM(trtp_ps), 273 #endif 274 DIMM_PARM(trc_ps), 275 DIMM_PARM(refresh_rate_ps), 276 DIMM_PARM(extended_op_srt), 277 278 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 279 DIMM_PARM(tis_ps), 280 DIMM_PARM(tih_ps), 281 DIMM_PARM(tds_ps), 282 DIMM_PARM(tdh_ps), 283 DIMM_PARM(tdqsq_max_ps), 284 DIMM_PARM(tqhs_ps), 285 #endif 286 #ifdef CONFIG_SYS_FSL_DDR4 287 DIMM_PARM_HEX(dq_mapping[0]), 288 DIMM_PARM_HEX(dq_mapping[1]), 289 DIMM_PARM_HEX(dq_mapping[2]), 290 DIMM_PARM_HEX(dq_mapping[3]), 291 DIMM_PARM_HEX(dq_mapping[4]), 292 DIMM_PARM_HEX(dq_mapping[5]), 293 DIMM_PARM_HEX(dq_mapping[6]), 294 DIMM_PARM_HEX(dq_mapping[7]), 295 DIMM_PARM_HEX(dq_mapping[8]), 296 DIMM_PARM_HEX(dq_mapping[9]), 297 DIMM_PARM_HEX(dq_mapping[10]), 298 DIMM_PARM_HEX(dq_mapping[11]), 299 DIMM_PARM_HEX(dq_mapping[12]), 300 DIMM_PARM_HEX(dq_mapping[13]), 301 DIMM_PARM_HEX(dq_mapping[14]), 302 DIMM_PARM_HEX(dq_mapping[15]), 303 DIMM_PARM_HEX(dq_mapping[16]), 304 DIMM_PARM_HEX(dq_mapping[17]), 305 DIMM_PARM(dq_mapping_ors), 306 #endif 307 DIMM_PARM(rank_density), 308 DIMM_PARM(capacity), 309 DIMM_PARM(base_address), 310 }; 311 312 static const unsigned int n_opts = ARRAY_SIZE(options); 313 314 if (handle_option_table(options, n_opts, p, optname_str, value_str)) 315 return; 316 317 printf("couldn't find option string %s\n", optname_str); 318 } 319 320 static void print_dimm_parameters(const dimm_params_t *pdimm) 321 { 322 static const struct options_string options[] = { 323 DIMM_PARM(n_ranks), 324 DIMM_PARM(data_width), 325 DIMM_PARM(primary_sdram_width), 326 DIMM_PARM(ec_sdram_width), 327 DIMM_PARM(package_3ds), 328 DIMM_PARM(registered_dimm), 329 DIMM_PARM(mirrored_dimm), 330 DIMM_PARM(device_width), 331 332 DIMM_PARM(n_row_addr), 333 DIMM_PARM(n_col_addr), 334 DIMM_PARM(edc_config), 335 #ifdef CONFIG_SYS_FSL_DDR4 336 DIMM_PARM(bank_addr_bits), 337 DIMM_PARM(bank_group_bits), 338 DIMM_PARM_HEX(die_density), 339 #else 340 DIMM_PARM(n_banks_per_sdram_device), 341 #endif 342 343 DIMM_PARM(tckmin_x_ps), 344 DIMM_PARM(tckmin_x_minus_1_ps), 345 DIMM_PARM(tckmin_x_minus_2_ps), 346 DIMM_PARM(tckmax_ps), 347 348 DIMM_PARM(caslat_x), 349 DIMM_PARM_HEX(caslat_x), 350 DIMM_PARM(taa_ps), 351 DIMM_PARM(caslat_x_minus_1), 352 DIMM_PARM(caslat_x_minus_2), 353 DIMM_PARM(caslat_lowest_derated), 354 355 DIMM_PARM(trcd_ps), 356 DIMM_PARM(trp_ps), 357 DIMM_PARM(tras_ps), 358 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3) 359 DIMM_PARM(tfaw_ps), 360 #endif 361 #ifdef CONFIG_SYS_FSL_DDR4 362 DIMM_PARM(trfc1_ps), 363 DIMM_PARM(trfc2_ps), 364 DIMM_PARM(trfc4_ps), 365 DIMM_PARM(trrds_ps), 366 DIMM_PARM(trrdl_ps), 367 DIMM_PARM(tccdl_ps), 368 DIMM_PARM(trfc_slr_ps), 369 #else 370 DIMM_PARM(twr_ps), 371 DIMM_PARM(twtr_ps), 372 DIMM_PARM(trfc_ps), 373 DIMM_PARM(trrd_ps), 374 DIMM_PARM(trtp_ps), 375 #endif 376 DIMM_PARM(trc_ps), 377 DIMM_PARM(refresh_rate_ps), 378 379 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 380 DIMM_PARM(tis_ps), 381 DIMM_PARM(tih_ps), 382 DIMM_PARM(tds_ps), 383 DIMM_PARM(tdh_ps), 384 DIMM_PARM(tdqsq_max_ps), 385 DIMM_PARM(tqhs_ps), 386 #endif 387 #ifdef CONFIG_SYS_FSL_DDR4 388 DIMM_PARM_HEX(dq_mapping[0]), 389 DIMM_PARM_HEX(dq_mapping[1]), 390 DIMM_PARM_HEX(dq_mapping[2]), 391 DIMM_PARM_HEX(dq_mapping[3]), 392 DIMM_PARM_HEX(dq_mapping[4]), 393 DIMM_PARM_HEX(dq_mapping[5]), 394 DIMM_PARM_HEX(dq_mapping[6]), 395 DIMM_PARM_HEX(dq_mapping[7]), 396 DIMM_PARM_HEX(dq_mapping[8]), 397 DIMM_PARM_HEX(dq_mapping[9]), 398 DIMM_PARM_HEX(dq_mapping[10]), 399 DIMM_PARM_HEX(dq_mapping[11]), 400 DIMM_PARM_HEX(dq_mapping[12]), 401 DIMM_PARM_HEX(dq_mapping[13]), 402 DIMM_PARM_HEX(dq_mapping[14]), 403 DIMM_PARM_HEX(dq_mapping[15]), 404 DIMM_PARM_HEX(dq_mapping[16]), 405 DIMM_PARM_HEX(dq_mapping[17]), 406 DIMM_PARM(dq_mapping_ors), 407 #endif 408 }; 409 static const unsigned int n_opts = ARRAY_SIZE(options); 410 411 if (pdimm->n_ranks == 0) { 412 printf("DIMM not present\n"); 413 return; 414 } 415 printf("DIMM organization parameters:\n"); 416 printf("module part name = %s\n", pdimm->mpart); 417 printf("rank_density = %llu bytes (%llu megabytes)\n", 418 pdimm->rank_density, pdimm->rank_density / 0x100000); 419 printf("capacity = %llu bytes (%llu megabytes)\n", 420 pdimm->capacity, pdimm->capacity / 0x100000); 421 printf("burst_lengths_bitmask = %02X\n", 422 pdimm->burst_lengths_bitmask); 423 printf("base_addresss = %llu (%08llX %08llX)\n", 424 pdimm->base_address, 425 (pdimm->base_address >> 32), 426 pdimm->base_address & 0xFFFFFFFF); 427 print_option_table(options, n_opts, pdimm); 428 } 429 430 static void print_lowest_common_dimm_parameters( 431 const common_timing_params_t *plcd_dimm_params) 432 { 433 static const struct options_string options[] = { 434 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 435 COMMON_TIMING(taamin_ps), 436 #endif 437 COMMON_TIMING(trcd_ps), 438 COMMON_TIMING(trp_ps), 439 COMMON_TIMING(tras_ps), 440 #ifdef CONFIG_SYS_FSL_DDR4 441 COMMON_TIMING(trfc1_ps), 442 COMMON_TIMING(trfc2_ps), 443 COMMON_TIMING(trfc4_ps), 444 COMMON_TIMING(trrds_ps), 445 COMMON_TIMING(trrdl_ps), 446 COMMON_TIMING(tccdl_ps), 447 COMMON_TIMING(trfc_slr_ps), 448 #else 449 COMMON_TIMING(twtr_ps), 450 COMMON_TIMING(trfc_ps), 451 COMMON_TIMING(trrd_ps), 452 COMMON_TIMING(trtp_ps), 453 #endif 454 COMMON_TIMING(twr_ps), 455 COMMON_TIMING(trc_ps), 456 COMMON_TIMING(refresh_rate_ps), 457 COMMON_TIMING(extended_op_srt), 458 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 459 COMMON_TIMING(tis_ps), 460 COMMON_TIMING(tih_ps), 461 COMMON_TIMING(tds_ps), 462 COMMON_TIMING(tdh_ps), 463 COMMON_TIMING(tdqsq_max_ps), 464 COMMON_TIMING(tqhs_ps), 465 #endif 466 COMMON_TIMING(lowest_common_spd_caslat), 467 COMMON_TIMING(highest_common_derated_caslat), 468 COMMON_TIMING(additive_latency), 469 COMMON_TIMING(ndimms_present), 470 COMMON_TIMING(all_dimms_registered), 471 COMMON_TIMING(all_dimms_unbuffered), 472 COMMON_TIMING(all_dimms_ecc_capable), 473 }; 474 static const unsigned int n_opts = ARRAY_SIZE(options); 475 476 /* Clock frequencies */ 477 printf("tckmin_x_ps = %u (%u MHz)\n", 478 plcd_dimm_params->tckmin_x_ps, 479 picos_to_mhz(plcd_dimm_params->tckmin_x_ps)); 480 printf("tckmax_ps = %u (%u MHz)\n", 481 plcd_dimm_params->tckmax_ps, 482 picos_to_mhz(plcd_dimm_params->tckmax_ps)); 483 printf("all_dimms_burst_lengths_bitmask = %02X\n", 484 plcd_dimm_params->all_dimms_burst_lengths_bitmask); 485 486 print_option_table(options, n_opts, plcd_dimm_params); 487 488 printf("total_mem = %llu (%llu megabytes)\n", 489 plcd_dimm_params->total_mem, 490 plcd_dimm_params->total_mem / 0x100000); 491 printf("base_address = %llu (%llu megabytes)\n", 492 plcd_dimm_params->base_address, 493 plcd_dimm_params->base_address / 0x100000); 494 } 495 496 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \ 497 sizeof((memctl_options_t *)0)->x, 0} 498 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \ 499 offsetof(memctl_options_t, cs_local_opts[x].y), \ 500 sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0} 501 502 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, 503 unsigned int ctl_num, 504 const char *optname_str, 505 const char *value_str) 506 { 507 memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]); 508 /* 509 * This array all on the stack and *computed* each time this 510 * function is rung. 511 */ 512 static const struct options_string options[] = { 513 CTRL_OPTIONS_CS(0, odt_rd_cfg), 514 CTRL_OPTIONS_CS(0, odt_wr_cfg), 515 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) 516 CTRL_OPTIONS_CS(1, odt_rd_cfg), 517 CTRL_OPTIONS_CS(1, odt_wr_cfg), 518 #endif 519 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) 520 CTRL_OPTIONS_CS(2, odt_rd_cfg), 521 CTRL_OPTIONS_CS(2, odt_wr_cfg), 522 #endif 523 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) 524 CTRL_OPTIONS_CS(3, odt_rd_cfg), 525 CTRL_OPTIONS_CS(3, odt_wr_cfg), 526 #endif 527 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 528 CTRL_OPTIONS_CS(0, odt_rtt_norm), 529 CTRL_OPTIONS_CS(0, odt_rtt_wr), 530 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) 531 CTRL_OPTIONS_CS(1, odt_rtt_norm), 532 CTRL_OPTIONS_CS(1, odt_rtt_wr), 533 #endif 534 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) 535 CTRL_OPTIONS_CS(2, odt_rtt_norm), 536 CTRL_OPTIONS_CS(2, odt_rtt_wr), 537 #endif 538 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) 539 CTRL_OPTIONS_CS(3, odt_rtt_norm), 540 CTRL_OPTIONS_CS(3, odt_rtt_wr), 541 #endif 542 #endif 543 CTRL_OPTIONS(memctl_interleaving), 544 CTRL_OPTIONS(memctl_interleaving_mode), 545 CTRL_OPTIONS(ba_intlv_ctl), 546 CTRL_OPTIONS(ecc_mode), 547 CTRL_OPTIONS(ecc_init_using_memctl), 548 CTRL_OPTIONS(dqs_config), 549 CTRL_OPTIONS(self_refresh_in_sleep), 550 CTRL_OPTIONS(dynamic_power), 551 CTRL_OPTIONS(data_bus_width), 552 CTRL_OPTIONS(burst_length), 553 CTRL_OPTIONS(cas_latency_override), 554 CTRL_OPTIONS(cas_latency_override_value), 555 CTRL_OPTIONS(use_derated_caslat), 556 CTRL_OPTIONS(additive_latency_override), 557 CTRL_OPTIONS(additive_latency_override_value), 558 CTRL_OPTIONS(clk_adjust), 559 CTRL_OPTIONS(cpo_override), 560 CTRL_OPTIONS(write_data_delay), 561 CTRL_OPTIONS(half_strength_driver_enable), 562 563 /* 564 * These can probably be changed to 2T_EN and 3T_EN 565 * (using a leading numerical character) without problem 566 */ 567 CTRL_OPTIONS(twot_en), 568 CTRL_OPTIONS(threet_en), 569 CTRL_OPTIONS(mirrored_dimm), 570 CTRL_OPTIONS(ap_en), 571 CTRL_OPTIONS(x4_en), 572 CTRL_OPTIONS(package_3ds), 573 CTRL_OPTIONS(bstopre), 574 CTRL_OPTIONS(wrlvl_override), 575 CTRL_OPTIONS(wrlvl_sample), 576 CTRL_OPTIONS(wrlvl_start), 577 CTRL_OPTIONS(cswl_override), 578 CTRL_OPTIONS(rcw_override), 579 CTRL_OPTIONS(rcw_1), 580 CTRL_OPTIONS(rcw_2), 581 CTRL_OPTIONS(rcw_3), 582 CTRL_OPTIONS(ddr_cdr1), 583 CTRL_OPTIONS(ddr_cdr2), 584 CTRL_OPTIONS(tfaw_window_four_activates_ps), 585 CTRL_OPTIONS(trwt_override), 586 CTRL_OPTIONS(trwt), 587 CTRL_OPTIONS(rtt_override), 588 CTRL_OPTIONS(rtt_override_value), 589 CTRL_OPTIONS(rtt_wr_override_value), 590 }; 591 592 static const unsigned int n_opts = ARRAY_SIZE(options); 593 594 if (handle_option_table(options, n_opts, p, 595 optname_str, value_str)) 596 return; 597 598 printf("couldn't find option string %s\n", optname_str); 599 } 600 601 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \ 602 sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1} 603 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \ 604 offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \ 605 sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1} 606 607 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) 608 { 609 unsigned int i; 610 static const struct options_string options[] = { 611 CFG_REGS_CS(0, bnds), 612 CFG_REGS_CS(0, config), 613 CFG_REGS_CS(0, config_2), 614 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) 615 CFG_REGS_CS(1, bnds), 616 CFG_REGS_CS(1, config), 617 CFG_REGS_CS(1, config_2), 618 #endif 619 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) 620 CFG_REGS_CS(2, bnds), 621 CFG_REGS_CS(2, config), 622 CFG_REGS_CS(2, config_2), 623 #endif 624 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) 625 CFG_REGS_CS(3, bnds), 626 CFG_REGS_CS(3, config), 627 CFG_REGS_CS(3, config_2), 628 #endif 629 CFG_REGS(timing_cfg_3), 630 CFG_REGS(timing_cfg_0), 631 CFG_REGS(timing_cfg_1), 632 CFG_REGS(timing_cfg_2), 633 CFG_REGS(ddr_sdram_cfg), 634 CFG_REGS(ddr_sdram_cfg_2), 635 CFG_REGS(ddr_sdram_cfg_3), 636 CFG_REGS(ddr_sdram_mode), 637 CFG_REGS(ddr_sdram_mode_2), 638 CFG_REGS(ddr_sdram_mode_3), 639 CFG_REGS(ddr_sdram_mode_4), 640 CFG_REGS(ddr_sdram_mode_5), 641 CFG_REGS(ddr_sdram_mode_6), 642 CFG_REGS(ddr_sdram_mode_7), 643 CFG_REGS(ddr_sdram_mode_8), 644 #ifdef CONFIG_SYS_FSL_DDR4 645 CFG_REGS(ddr_sdram_mode_9), 646 CFG_REGS(ddr_sdram_mode_10), 647 CFG_REGS(ddr_sdram_mode_11), 648 CFG_REGS(ddr_sdram_mode_12), 649 CFG_REGS(ddr_sdram_mode_13), 650 CFG_REGS(ddr_sdram_mode_14), 651 CFG_REGS(ddr_sdram_mode_15), 652 CFG_REGS(ddr_sdram_mode_16), 653 #endif 654 CFG_REGS(ddr_sdram_interval), 655 CFG_REGS(ddr_data_init), 656 CFG_REGS(ddr_sdram_clk_cntl), 657 CFG_REGS(ddr_init_addr), 658 CFG_REGS(ddr_init_ext_addr), 659 CFG_REGS(timing_cfg_4), 660 CFG_REGS(timing_cfg_5), 661 #ifdef CONFIG_SYS_FSL_DDR4 662 CFG_REGS(timing_cfg_6), 663 CFG_REGS(timing_cfg_7), 664 CFG_REGS(timing_cfg_8), 665 CFG_REGS(timing_cfg_9), 666 #endif 667 CFG_REGS(ddr_zq_cntl), 668 CFG_REGS(ddr_wrlvl_cntl), 669 CFG_REGS(ddr_wrlvl_cntl_2), 670 CFG_REGS(ddr_wrlvl_cntl_3), 671 CFG_REGS(ddr_sr_cntr), 672 CFG_REGS(ddr_sdram_rcw_1), 673 CFG_REGS(ddr_sdram_rcw_2), 674 CFG_REGS(ddr_sdram_rcw_3), 675 CFG_REGS(ddr_cdr1), 676 CFG_REGS(ddr_cdr2), 677 CFG_REGS(dq_map_0), 678 CFG_REGS(dq_map_1), 679 CFG_REGS(dq_map_2), 680 CFG_REGS(dq_map_3), 681 CFG_REGS(err_disable), 682 CFG_REGS(err_int_en), 683 CFG_REGS(ddr_eor), 684 }; 685 static const unsigned int n_opts = ARRAY_SIZE(options); 686 687 print_option_table(options, n_opts, ddr); 688 689 for (i = 0; i < 64; i++) 690 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]); 691 } 692 693 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, 694 unsigned int ctrl_num, 695 const char *regname, 696 const char *value_str) 697 { 698 unsigned int i; 699 fsl_ddr_cfg_regs_t *ddr; 700 char buf[20]; 701 static const struct options_string options[] = { 702 CFG_REGS_CS(0, bnds), 703 CFG_REGS_CS(0, config), 704 CFG_REGS_CS(0, config_2), 705 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) 706 CFG_REGS_CS(1, bnds), 707 CFG_REGS_CS(1, config), 708 CFG_REGS_CS(1, config_2), 709 #endif 710 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) 711 CFG_REGS_CS(2, bnds), 712 CFG_REGS_CS(2, config), 713 CFG_REGS_CS(2, config_2), 714 #endif 715 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) 716 CFG_REGS_CS(3, bnds), 717 CFG_REGS_CS(3, config), 718 CFG_REGS_CS(3, config_2), 719 #endif 720 CFG_REGS(timing_cfg_3), 721 CFG_REGS(timing_cfg_0), 722 CFG_REGS(timing_cfg_1), 723 CFG_REGS(timing_cfg_2), 724 CFG_REGS(ddr_sdram_cfg), 725 CFG_REGS(ddr_sdram_cfg_2), 726 CFG_REGS(ddr_sdram_cfg_3), 727 CFG_REGS(ddr_sdram_mode), 728 CFG_REGS(ddr_sdram_mode_2), 729 CFG_REGS(ddr_sdram_mode_3), 730 CFG_REGS(ddr_sdram_mode_4), 731 CFG_REGS(ddr_sdram_mode_5), 732 CFG_REGS(ddr_sdram_mode_6), 733 CFG_REGS(ddr_sdram_mode_7), 734 CFG_REGS(ddr_sdram_mode_8), 735 #ifdef CONFIG_SYS_FSL_DDR4 736 CFG_REGS(ddr_sdram_mode_9), 737 CFG_REGS(ddr_sdram_mode_10), 738 CFG_REGS(ddr_sdram_mode_11), 739 CFG_REGS(ddr_sdram_mode_12), 740 CFG_REGS(ddr_sdram_mode_13), 741 CFG_REGS(ddr_sdram_mode_14), 742 CFG_REGS(ddr_sdram_mode_15), 743 CFG_REGS(ddr_sdram_mode_16), 744 #endif 745 CFG_REGS(ddr_sdram_interval), 746 CFG_REGS(ddr_data_init), 747 CFG_REGS(ddr_sdram_clk_cntl), 748 CFG_REGS(ddr_init_addr), 749 CFG_REGS(ddr_init_ext_addr), 750 CFG_REGS(timing_cfg_4), 751 CFG_REGS(timing_cfg_5), 752 #ifdef CONFIG_SYS_FSL_DDR4 753 CFG_REGS(timing_cfg_6), 754 CFG_REGS(timing_cfg_7), 755 CFG_REGS(timing_cfg_8), 756 CFG_REGS(timing_cfg_9), 757 #endif 758 CFG_REGS(ddr_zq_cntl), 759 CFG_REGS(ddr_wrlvl_cntl), 760 CFG_REGS(ddr_wrlvl_cntl_2), 761 CFG_REGS(ddr_wrlvl_cntl_3), 762 CFG_REGS(ddr_sr_cntr), 763 CFG_REGS(ddr_sdram_rcw_1), 764 CFG_REGS(ddr_sdram_rcw_2), 765 CFG_REGS(ddr_sdram_rcw_3), 766 CFG_REGS(ddr_cdr1), 767 CFG_REGS(ddr_cdr2), 768 CFG_REGS(dq_map_0), 769 CFG_REGS(dq_map_1), 770 CFG_REGS(dq_map_2), 771 CFG_REGS(dq_map_3), 772 CFG_REGS(err_disable), 773 CFG_REGS(err_int_en), 774 CFG_REGS(ddr_sdram_rcw_2), 775 CFG_REGS(ddr_sdram_rcw_2), 776 CFG_REGS(ddr_eor), 777 }; 778 static const unsigned int n_opts = ARRAY_SIZE(options); 779 780 debug("fsl_ddr_regs_edit: ctrl_num = %u, " 781 "regname = %s, value = %s\n", 782 ctrl_num, regname, value_str); 783 if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS) 784 return; 785 786 ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]); 787 788 if (handle_option_table(options, n_opts, ddr, regname, value_str)) 789 return; 790 791 for (i = 0; i < 64; i++) { 792 unsigned int value = simple_strtoul(value_str, NULL, 0); 793 sprintf(buf, "debug_%u", i + 1); 794 if (strcmp(buf, regname) == 0) { 795 ddr->debug[i] = value; 796 return; 797 } 798 } 799 printf("Error: couldn't find register string %s\n", regname); 800 } 801 802 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \ 803 sizeof((memctl_options_t *)0)->x, 1} 804 805 static void print_memctl_options(const memctl_options_t *popts) 806 { 807 static const struct options_string options[] = { 808 CTRL_OPTIONS_CS(0, odt_rd_cfg), 809 CTRL_OPTIONS_CS(0, odt_wr_cfg), 810 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) 811 CTRL_OPTIONS_CS(1, odt_rd_cfg), 812 CTRL_OPTIONS_CS(1, odt_wr_cfg), 813 #endif 814 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) 815 CTRL_OPTIONS_CS(2, odt_rd_cfg), 816 CTRL_OPTIONS_CS(2, odt_wr_cfg), 817 #endif 818 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) 819 CTRL_OPTIONS_CS(3, odt_rd_cfg), 820 CTRL_OPTIONS_CS(3, odt_wr_cfg), 821 #endif 822 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 823 CTRL_OPTIONS_CS(0, odt_rtt_norm), 824 CTRL_OPTIONS_CS(0, odt_rtt_wr), 825 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) 826 CTRL_OPTIONS_CS(1, odt_rtt_norm), 827 CTRL_OPTIONS_CS(1, odt_rtt_wr), 828 #endif 829 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) 830 CTRL_OPTIONS_CS(2, odt_rtt_norm), 831 CTRL_OPTIONS_CS(2, odt_rtt_wr), 832 #endif 833 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) 834 CTRL_OPTIONS_CS(3, odt_rtt_norm), 835 CTRL_OPTIONS_CS(3, odt_rtt_wr), 836 #endif 837 #endif 838 CTRL_OPTIONS(memctl_interleaving), 839 CTRL_OPTIONS(memctl_interleaving_mode), 840 CTRL_OPTIONS_HEX(ba_intlv_ctl), 841 CTRL_OPTIONS(ecc_mode), 842 CTRL_OPTIONS(ecc_init_using_memctl), 843 CTRL_OPTIONS(dqs_config), 844 CTRL_OPTIONS(self_refresh_in_sleep), 845 CTRL_OPTIONS(dynamic_power), 846 CTRL_OPTIONS(data_bus_width), 847 CTRL_OPTIONS(burst_length), 848 CTRL_OPTIONS(cas_latency_override), 849 CTRL_OPTIONS(cas_latency_override_value), 850 CTRL_OPTIONS(use_derated_caslat), 851 CTRL_OPTIONS(additive_latency_override), 852 CTRL_OPTIONS(additive_latency_override_value), 853 CTRL_OPTIONS(clk_adjust), 854 CTRL_OPTIONS(cpo_override), 855 CTRL_OPTIONS(write_data_delay), 856 CTRL_OPTIONS(half_strength_driver_enable), 857 /* 858 * These can probably be changed to 2T_EN and 3T_EN 859 * (using a leading numerical character) without problem 860 */ 861 CTRL_OPTIONS(twot_en), 862 CTRL_OPTIONS(threet_en), 863 CTRL_OPTIONS(registered_dimm_en), 864 CTRL_OPTIONS(mirrored_dimm), 865 CTRL_OPTIONS(ap_en), 866 CTRL_OPTIONS(x4_en), 867 CTRL_OPTIONS(package_3ds), 868 CTRL_OPTIONS(bstopre), 869 CTRL_OPTIONS(wrlvl_override), 870 CTRL_OPTIONS(wrlvl_sample), 871 CTRL_OPTIONS(wrlvl_start), 872 CTRL_OPTIONS_HEX(cswl_override), 873 CTRL_OPTIONS(rcw_override), 874 CTRL_OPTIONS_HEX(rcw_1), 875 CTRL_OPTIONS_HEX(rcw_2), 876 CTRL_OPTIONS_HEX(rcw_3), 877 CTRL_OPTIONS_HEX(ddr_cdr1), 878 CTRL_OPTIONS_HEX(ddr_cdr2), 879 CTRL_OPTIONS(tfaw_window_four_activates_ps), 880 CTRL_OPTIONS(trwt_override), 881 CTRL_OPTIONS(trwt), 882 CTRL_OPTIONS(rtt_override), 883 CTRL_OPTIONS(rtt_override_value), 884 CTRL_OPTIONS(rtt_wr_override_value), 885 }; 886 static const unsigned int n_opts = ARRAY_SIZE(options); 887 888 print_option_table(options, n_opts, popts); 889 } 890 891 #ifdef CONFIG_SYS_FSL_DDR1 892 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd) 893 { 894 unsigned int i; 895 896 printf("%-3d : %02x %s\n", 0, spd->info_size, 897 " spd->info_size, * 0 # bytes written into serial memory *"); 898 printf("%-3d : %02x %s\n", 1, spd->chip_size, 899 " spd->chip_size, * 1 Total # bytes of SPD memory device *"); 900 printf("%-3d : %02x %s\n", 2, spd->mem_type, 901 " spd->mem_type, * 2 Fundamental memory type *"); 902 printf("%-3d : %02x %s\n", 3, spd->nrow_addr, 903 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); 904 printf("%-3d : %02x %s\n", 4, spd->ncol_addr, 905 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); 906 printf("%-3d : %02x %s\n", 5, spd->nrows, 907 " spd->nrows * 5 # of DIMM Banks *"); 908 printf("%-3d : %02x %s\n", 6, spd->dataw_lsb, 909 " spd->dataw_lsb, * 6 Data Width lsb of this assembly *"); 910 printf("%-3d : %02x %s\n", 7, spd->dataw_msb, 911 " spd->dataw_msb, * 7 Data Width msb of this assembly *"); 912 printf("%-3d : %02x %s\n", 8, spd->voltage, 913 " spd->voltage, * 8 Voltage intf std of this assembly *"); 914 printf("%-3d : %02x %s\n", 9, spd->clk_cycle, 915 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); 916 printf("%-3d : %02x %s\n", 10, spd->clk_access, 917 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); 918 printf("%-3d : %02x %s\n", 11, spd->config, 919 " spd->config, * 11 DIMM Configuration type *"); 920 printf("%-3d : %02x %s\n", 12, spd->refresh, 921 " spd->refresh, * 12 Refresh Rate/Type *"); 922 printf("%-3d : %02x %s\n", 13, spd->primw, 923 " spd->primw, * 13 Primary SDRAM Width *"); 924 printf("%-3d : %02x %s\n", 14, spd->ecw, 925 " spd->ecw, * 14 Error Checking SDRAM width *"); 926 printf("%-3d : %02x %s\n", 15, spd->min_delay, 927 " spd->min_delay, * 15 Back to Back Random Access *"); 928 printf("%-3d : %02x %s\n", 16, spd->burstl, 929 " spd->burstl, * 16 Burst Lengths Supported *"); 930 printf("%-3d : %02x %s\n", 17, spd->nbanks, 931 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); 932 printf("%-3d : %02x %s\n", 18, spd->cas_lat, 933 " spd->cas_lat, * 18 CAS# Latencies Supported *"); 934 printf("%-3d : %02x %s\n", 19, spd->cs_lat, 935 " spd->cs_lat, * 19 Chip Select Latency *"); 936 printf("%-3d : %02x %s\n", 20, spd->write_lat, 937 " spd->write_lat, * 20 Write Latency/Recovery *"); 938 printf("%-3d : %02x %s\n", 21, spd->mod_attr, 939 " spd->mod_attr, * 21 SDRAM Module Attributes *"); 940 printf("%-3d : %02x %s\n", 22, spd->dev_attr, 941 " spd->dev_attr, * 22 SDRAM Device Attributes *"); 942 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, 943 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); 944 printf("%-3d : %02x %s\n", 24, spd->clk_access2, 945 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); 946 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, 947 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); 948 printf("%-3d : %02x %s\n", 26, spd->clk_access3, 949 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); 950 printf("%-3d : %02x %s\n", 27, spd->trp, 951 " spd->trp, * 27 Min Row Precharge Time (tRP)*"); 952 printf("%-3d : %02x %s\n", 28, spd->trrd, 953 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); 954 printf("%-3d : %02x %s\n", 29, spd->trcd, 955 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); 956 printf("%-3d : %02x %s\n", 30, spd->tras, 957 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); 958 printf("%-3d : %02x %s\n", 31, spd->bank_dens, 959 " spd->bank_dens, * 31 Density of each bank on module *"); 960 printf("%-3d : %02x %s\n", 32, spd->ca_setup, 961 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); 962 printf("%-3d : %02x %s\n", 33, spd->ca_hold, 963 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); 964 printf("%-3d : %02x %s\n", 34, spd->data_setup, 965 " spd->data_setup, * 34 Data signal input setup time *"); 966 printf("%-3d : %02x %s\n", 35, spd->data_hold, 967 " spd->data_hold, * 35 Data signal input hold time *"); 968 printf("%-3d : %02x %s\n", 36, spd->res_36_40[0], 969 " spd->res_36_40[0], * 36 Reserved / tWR *"); 970 printf("%-3d : %02x %s\n", 37, spd->res_36_40[1], 971 " spd->res_36_40[1], * 37 Reserved / tWTR *"); 972 printf("%-3d : %02x %s\n", 38, spd->res_36_40[2], 973 " spd->res_36_40[2], * 38 Reserved / tRTP *"); 974 printf("%-3d : %02x %s\n", 39, spd->res_36_40[3], 975 " spd->res_36_40[3], * 39 Reserved / mem_probe *"); 976 printf("%-3d : %02x %s\n", 40, spd->res_36_40[4], 977 " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *"); 978 printf("%-3d : %02x %s\n", 41, spd->trc, 979 " spd->trc, * 41 Min Active to Auto refresh time tRC *"); 980 printf("%-3d : %02x %s\n", 42, spd->trfc, 981 " spd->trfc, * 42 Min Auto to Active period tRFC *"); 982 printf("%-3d : %02x %s\n", 43, spd->tckmax, 983 " spd->tckmax, * 43 Max device cycle time tCKmax *"); 984 printf("%-3d : %02x %s\n", 44, spd->tdqsq, 985 " spd->tdqsq, * 44 Max DQS to DQ skew *"); 986 printf("%-3d : %02x %s\n", 45, spd->tqhs, 987 " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); 988 printf("%-3d : %02x %s\n", 46, spd->res_46, 989 " spd->res_46, * 46 Reserved/ PLL Relock time *"); 990 printf("%-3d : %02x %s\n", 47, spd->dimm_height, 991 " spd->dimm_height * 47 SDRAM DIMM Height *"); 992 993 printf("%-3d-%3d: ", 48, 61); 994 995 for (i = 0; i < 14; i++) 996 printf("%02x", spd->res_48_61[i]); 997 998 printf(" * 48-61 IDD in SPD and Reserved space *\n"); 999 1000 printf("%-3d : %02x %s\n", 62, spd->spd_rev, 1001 " spd->spd_rev, * 62 SPD Data Revision Code *"); 1002 printf("%-3d : %02x %s\n", 63, spd->cksum, 1003 " spd->cksum, * 63 Checksum for bytes 0-62 *"); 1004 printf("%-3d-%3d: ", 64, 71); 1005 1006 for (i = 0; i < 8; i++) 1007 printf("%02x", spd->mid[i]); 1008 1009 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); 1010 printf("%-3d : %02x %s\n", 72, spd->mloc, 1011 " spd->mloc, * 72 Manufacturing Location *"); 1012 1013 printf("%-3d-%3d: >>", 73, 90); 1014 1015 for (i = 0; i < 18; i++) 1016 printf("%c", spd->mpart[i]); 1017 1018 printf("<<* 73 Manufacturer's Part Number *\n"); 1019 1020 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], 1021 "* 91 Revision Code *"); 1022 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], 1023 "* 93 Manufacturing Date *"); 1024 printf("%-3d-%3d: ", 95, 98); 1025 1026 for (i = 0; i < 4; i++) 1027 printf("%02x", spd->sernum[i]); 1028 1029 printf("* 95 Assembly Serial Number *\n"); 1030 1031 printf("%-3d-%3d: ", 99, 127); 1032 1033 for (i = 0; i < 27; i++) 1034 printf("%02x", spd->mspec[i]); 1035 1036 printf("* 99 Manufacturer Specific Data *\n"); 1037 } 1038 #endif 1039 1040 #ifdef CONFIG_SYS_FSL_DDR2 1041 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd) 1042 { 1043 unsigned int i; 1044 1045 printf("%-3d : %02x %s\n", 0, spd->info_size, 1046 " spd->info_size, * 0 # bytes written into serial memory *"); 1047 printf("%-3d : %02x %s\n", 1, spd->chip_size, 1048 " spd->chip_size, * 1 Total # bytes of SPD memory device *"); 1049 printf("%-3d : %02x %s\n", 2, spd->mem_type, 1050 " spd->mem_type, * 2 Fundamental memory type *"); 1051 printf("%-3d : %02x %s\n", 3, spd->nrow_addr, 1052 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); 1053 printf("%-3d : %02x %s\n", 4, spd->ncol_addr, 1054 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); 1055 printf("%-3d : %02x %s\n", 5, spd->mod_ranks, 1056 " spd->mod_ranks * 5 # of Module Rows on this assembly *"); 1057 printf("%-3d : %02x %s\n", 6, spd->dataw, 1058 " spd->dataw, * 6 Data Width of this assembly *"); 1059 printf("%-3d : %02x %s\n", 7, spd->res_7, 1060 " spd->res_7, * 7 Reserved *"); 1061 printf("%-3d : %02x %s\n", 8, spd->voltage, 1062 " spd->voltage, * 8 Voltage intf std of this assembly *"); 1063 printf("%-3d : %02x %s\n", 9, spd->clk_cycle, 1064 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); 1065 printf("%-3d : %02x %s\n", 10, spd->clk_access, 1066 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); 1067 printf("%-3d : %02x %s\n", 11, spd->config, 1068 " spd->config, * 11 DIMM Configuration type *"); 1069 printf("%-3d : %02x %s\n", 12, spd->refresh, 1070 " spd->refresh, * 12 Refresh Rate/Type *"); 1071 printf("%-3d : %02x %s\n", 13, spd->primw, 1072 " spd->primw, * 13 Primary SDRAM Width *"); 1073 printf("%-3d : %02x %s\n", 14, spd->ecw, 1074 " spd->ecw, * 14 Error Checking SDRAM width *"); 1075 printf("%-3d : %02x %s\n", 15, spd->res_15, 1076 " spd->res_15, * 15 Reserved *"); 1077 printf("%-3d : %02x %s\n", 16, spd->burstl, 1078 " spd->burstl, * 16 Burst Lengths Supported *"); 1079 printf("%-3d : %02x %s\n", 17, spd->nbanks, 1080 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); 1081 printf("%-3d : %02x %s\n", 18, spd->cas_lat, 1082 " spd->cas_lat, * 18 CAS# Latencies Supported *"); 1083 printf("%-3d : %02x %s\n", 19, spd->mech_char, 1084 " spd->mech_char, * 19 Mechanical Characteristics *"); 1085 printf("%-3d : %02x %s\n", 20, spd->dimm_type, 1086 " spd->dimm_type, * 20 DIMM type *"); 1087 printf("%-3d : %02x %s\n", 21, spd->mod_attr, 1088 " spd->mod_attr, * 21 SDRAM Module Attributes *"); 1089 printf("%-3d : %02x %s\n", 22, spd->dev_attr, 1090 " spd->dev_attr, * 22 SDRAM Device Attributes *"); 1091 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, 1092 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); 1093 printf("%-3d : %02x %s\n", 24, spd->clk_access2, 1094 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); 1095 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, 1096 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); 1097 printf("%-3d : %02x %s\n", 26, spd->clk_access3, 1098 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); 1099 printf("%-3d : %02x %s\n", 27, spd->trp, 1100 " spd->trp, * 27 Min Row Precharge Time (tRP)*"); 1101 printf("%-3d : %02x %s\n", 28, spd->trrd, 1102 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); 1103 printf("%-3d : %02x %s\n", 29, spd->trcd, 1104 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); 1105 printf("%-3d : %02x %s\n", 30, spd->tras, 1106 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); 1107 printf("%-3d : %02x %s\n", 31, spd->rank_dens, 1108 " spd->rank_dens, * 31 Density of each rank on module *"); 1109 printf("%-3d : %02x %s\n", 32, spd->ca_setup, 1110 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); 1111 printf("%-3d : %02x %s\n", 33, spd->ca_hold, 1112 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); 1113 printf("%-3d : %02x %s\n", 34, spd->data_setup, 1114 " spd->data_setup, * 34 Data signal input setup time *"); 1115 printf("%-3d : %02x %s\n", 35, spd->data_hold, 1116 " spd->data_hold, * 35 Data signal input hold time *"); 1117 printf("%-3d : %02x %s\n", 36, spd->twr, 1118 " spd->twr, * 36 Write Recovery time tWR *"); 1119 printf("%-3d : %02x %s\n", 37, spd->twtr, 1120 " spd->twtr, * 37 Int write to read delay tWTR *"); 1121 printf("%-3d : %02x %s\n", 38, spd->trtp, 1122 " spd->trtp, * 38 Int read to precharge delay tRTP *"); 1123 printf("%-3d : %02x %s\n", 39, spd->mem_probe, 1124 " spd->mem_probe, * 39 Mem analysis probe characteristics *"); 1125 printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext, 1126 " spd->trctrfc_ext, * 40 Extensions to trc and trfc *"); 1127 printf("%-3d : %02x %s\n", 41, spd->trc, 1128 " spd->trc, * 41 Min Active to Auto refresh time tRC *"); 1129 printf("%-3d : %02x %s\n", 42, spd->trfc, 1130 " spd->trfc, * 42 Min Auto to Active period tRFC *"); 1131 printf("%-3d : %02x %s\n", 43, spd->tckmax, 1132 " spd->tckmax, * 43 Max device cycle time tCKmax *"); 1133 printf("%-3d : %02x %s\n", 44, spd->tdqsq, 1134 " spd->tdqsq, * 44 Max DQS to DQ skew *"); 1135 printf("%-3d : %02x %s\n", 45, spd->tqhs, 1136 " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); 1137 printf("%-3d : %02x %s\n", 46, spd->pll_relock, 1138 " spd->pll_relock, * 46 PLL Relock time *"); 1139 printf("%-3d : %02x %s\n", 47, spd->t_casemax, 1140 " spd->t_casemax, * 47 t_casemax *"); 1141 printf("%-3d : %02x %s\n", 48, spd->psi_ta_dram, 1142 " spd->psi_ta_dram, * 48 Thermal Resistance of DRAM Package " 1143 "from Top (Case) to Ambient (Psi T-A DRAM) *"); 1144 printf("%-3d : %02x %s\n", 49, spd->dt0_mode, 1145 " spd->dt0_mode, * 49 DRAM Case Temperature Rise from " 1146 "Ambient due to Activate-Precharge/Mode Bits " 1147 "(DT0/Mode Bits) *)"); 1148 printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q, 1149 " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from " 1150 "Ambient due to Precharge/Quiet Standby " 1151 "(DT2N/DT2Q) *"); 1152 printf("%-3d : %02x %s\n", 51, spd->dt2p, 1153 " spd->dt2p, * 51 DRAM Case Temperature Rise from " 1154 "Ambient due to Precharge Power-Down (DT2P) *"); 1155 printf("%-3d : %02x %s\n", 52, spd->dt3n, 1156 " spd->dt3n, * 52 DRAM Case Temperature Rise from " 1157 "Ambient due to Active Standby (DT3N) *"); 1158 printf("%-3d : %02x %s\n", 53, spd->dt3pfast, 1159 " spd->dt3pfast, * 53 DRAM Case Temperature Rise from " 1160 "Ambient due to Active Power-Down with Fast PDN Exit " 1161 "(DT3Pfast) *"); 1162 printf("%-3d : %02x %s\n", 54, spd->dt3pslow, 1163 " spd->dt3pslow, * 54 DRAM Case Temperature Rise from " 1164 "Ambient due to Active Power-Down with Slow PDN Exit " 1165 "(DT3Pslow) *"); 1166 printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w, 1167 " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from " 1168 "Ambient due to Page Open Burst Read/DT4R4W Mode Bit " 1169 "(DT4R/DT4R4W Mode Bit) *"); 1170 printf("%-3d : %02x %s\n", 56, spd->dt5b, 1171 " spd->dt5b, * 56 DRAM Case Temperature Rise from " 1172 "Ambient due to Burst Refresh (DT5B) *"); 1173 printf("%-3d : %02x %s\n", 57, spd->dt7, 1174 " spd->dt7, * 57 DRAM Case Temperature Rise from " 1175 "Ambient due to Bank Interleave Reads with " 1176 "Auto-Precharge (DT7) *"); 1177 printf("%-3d : %02x %s\n", 58, spd->psi_ta_pll, 1178 " spd->psi_ta_pll, * 58 Thermal Resistance of PLL Package form" 1179 " Top (Case) to Ambient (Psi T-A PLL) *"); 1180 printf("%-3d : %02x %s\n", 59, spd->psi_ta_reg, 1181 " spd->psi_ta_reg, * 59 Thermal Reisitance of Register Package" 1182 " from Top (Case) to Ambient (Psi T-A Register) *"); 1183 printf("%-3d : %02x %s\n", 60, spd->dtpllactive, 1184 " spd->dtpllactive, * 60 PLL Case Temperature Rise from " 1185 "Ambient due to PLL Active (DT PLL Active) *"); 1186 printf("%-3d : %02x %s\n", 61, spd->dtregact, 1187 " spd->dtregact, " 1188 "* 61 Register Case Temperature Rise from Ambient due to " 1189 "Register Active/Mode Bit (DT Register Active/Mode Bit) *"); 1190 printf("%-3d : %02x %s\n", 62, spd->spd_rev, 1191 " spd->spd_rev, * 62 SPD Data Revision Code *"); 1192 printf("%-3d : %02x %s\n", 63, spd->cksum, 1193 " spd->cksum, * 63 Checksum for bytes 0-62 *"); 1194 1195 printf("%-3d-%3d: ", 64, 71); 1196 1197 for (i = 0; i < 8; i++) 1198 printf("%02x", spd->mid[i]); 1199 1200 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); 1201 1202 printf("%-3d : %02x %s\n", 72, spd->mloc, 1203 " spd->mloc, * 72 Manufacturing Location *"); 1204 1205 printf("%-3d-%3d: >>", 73, 90); 1206 for (i = 0; i < 18; i++) 1207 printf("%c", spd->mpart[i]); 1208 1209 1210 printf("<<* 73 Manufacturer's Part Number *\n"); 1211 1212 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], 1213 "* 91 Revision Code *"); 1214 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], 1215 "* 93 Manufacturing Date *"); 1216 printf("%-3d-%3d: ", 95, 98); 1217 1218 for (i = 0; i < 4; i++) 1219 printf("%02x", spd->sernum[i]); 1220 1221 printf("* 95 Assembly Serial Number *\n"); 1222 1223 printf("%-3d-%3d: ", 99, 127); 1224 for (i = 0; i < 27; i++) 1225 printf("%02x", spd->mspec[i]); 1226 1227 1228 printf("* 99 Manufacturer Specific Data *\n"); 1229 } 1230 #endif 1231 1232 #ifdef CONFIG_SYS_FSL_DDR3 1233 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) 1234 { 1235 unsigned int i; 1236 1237 /* General Section: Bytes 0-59 */ 1238 1239 #define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); 1240 #define PRINT_NNXXS(n0, n1, x0, x1, s) \ 1241 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); 1242 1243 PRINT_NXS(0, spd->info_size_crc, 1244 "info_size_crc bytes written into serial memory, " 1245 "CRC coverage"); 1246 PRINT_NXS(1, spd->spd_rev, 1247 "spd_rev SPD Revision"); 1248 PRINT_NXS(2, spd->mem_type, 1249 "mem_type Key Byte / DRAM Device Type"); 1250 PRINT_NXS(3, spd->module_type, 1251 "module_type Key Byte / Module Type"); 1252 PRINT_NXS(4, spd->density_banks, 1253 "density_banks SDRAM Density and Banks"); 1254 PRINT_NXS(5, spd->addressing, 1255 "addressing SDRAM Addressing"); 1256 PRINT_NXS(6, spd->module_vdd, 1257 "module_vdd Module Nominal Voltage, VDD"); 1258 PRINT_NXS(7, spd->organization, 1259 "organization Module Organization"); 1260 PRINT_NXS(8, spd->bus_width, 1261 "bus_width Module Memory Bus Width"); 1262 PRINT_NXS(9, spd->ftb_div, 1263 "ftb_div Fine Timebase (FTB) Dividend / Divisor"); 1264 PRINT_NXS(10, spd->mtb_dividend, 1265 "mtb_dividend Medium Timebase (MTB) Dividend"); 1266 PRINT_NXS(11, spd->mtb_divisor, 1267 "mtb_divisor Medium Timebase (MTB) Divisor"); 1268 PRINT_NXS(12, spd->tck_min, 1269 "tck_min SDRAM Minimum Cycle Time"); 1270 PRINT_NXS(13, spd->res_13, 1271 "res_13 Reserved"); 1272 PRINT_NXS(14, spd->caslat_lsb, 1273 "caslat_lsb CAS Latencies Supported, LSB"); 1274 PRINT_NXS(15, spd->caslat_msb, 1275 "caslat_msb CAS Latencies Supported, MSB"); 1276 PRINT_NXS(16, spd->taa_min, 1277 "taa_min Min CAS Latency Time"); 1278 PRINT_NXS(17, spd->twr_min, 1279 "twr_min Min Write REcovery Time"); 1280 PRINT_NXS(18, spd->trcd_min, 1281 "trcd_min Min RAS# to CAS# Delay Time"); 1282 PRINT_NXS(19, spd->trrd_min, 1283 "trrd_min Min Row Active to Row Active Delay Time"); 1284 PRINT_NXS(20, spd->trp_min, 1285 "trp_min Min Row Precharge Delay Time"); 1286 PRINT_NXS(21, spd->tras_trc_ext, 1287 "tras_trc_ext Upper Nibbles for tRAS and tRC"); 1288 PRINT_NXS(22, spd->tras_min_lsb, 1289 "tras_min_lsb Min Active to Precharge Delay Time, LSB"); 1290 PRINT_NXS(23, spd->trc_min_lsb, 1291 "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB"); 1292 PRINT_NXS(24, spd->trfc_min_lsb, 1293 "trfc_min_lsb Min Refresh Recovery Delay Time LSB"); 1294 PRINT_NXS(25, spd->trfc_min_msb, 1295 "trfc_min_msb Min Refresh Recovery Delay Time MSB"); 1296 PRINT_NXS(26, spd->twtr_min, 1297 "twtr_min Min Internal Write to Read Command Delay Time"); 1298 PRINT_NXS(27, spd->trtp_min, 1299 "trtp_min " 1300 "Min Internal Read to Precharge Command Delay Time"); 1301 PRINT_NXS(28, spd->tfaw_msb, 1302 "tfaw_msb Upper Nibble for tFAW"); 1303 PRINT_NXS(29, spd->tfaw_min, 1304 "tfaw_min Min Four Activate Window Delay Time"); 1305 PRINT_NXS(30, spd->opt_features, 1306 "opt_features SDRAM Optional Features"); 1307 PRINT_NXS(31, spd->therm_ref_opt, 1308 "therm_ref_opt SDRAM Thermal and Refresh Opts"); 1309 PRINT_NXS(32, spd->therm_sensor, 1310 "therm_sensor SDRAM Thermal Sensor"); 1311 PRINT_NXS(33, spd->device_type, 1312 "device_type SDRAM Device Type"); 1313 PRINT_NXS(34, spd->fine_tck_min, 1314 "fine_tck_min Fine offset for tCKmin"); 1315 PRINT_NXS(35, spd->fine_taa_min, 1316 "fine_taa_min Fine offset for tAAmin"); 1317 PRINT_NXS(36, spd->fine_trcd_min, 1318 "fine_trcd_min Fine offset for tRCDmin"); 1319 PRINT_NXS(37, spd->fine_trp_min, 1320 "fine_trp_min Fine offset for tRPmin"); 1321 PRINT_NXS(38, spd->fine_trc_min, 1322 "fine_trc_min Fine offset for tRCmin"); 1323 1324 printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */ 1325 1326 for (i = 39; i <= 59; i++) 1327 printf("%02x ", spd->res_39_59[i - 39]); 1328 1329 puts("\n"); 1330 1331 switch (spd->module_type) { 1332 case 0x02: /* UDIMM */ 1333 case 0x03: /* SO-DIMM */ 1334 case 0x04: /* Micro-DIMM */ 1335 case 0x06: /* Mini-UDIMM */ 1336 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height, 1337 "mod_height (Unbuffered) Module Nominal Height"); 1338 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness, 1339 "mod_thickness (Unbuffered) Module Maximum Thickness"); 1340 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card, 1341 "ref_raw_card (Unbuffered) Reference Raw Card Used"); 1342 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping, 1343 "addr_mapping (Unbuffered) Address mapping from " 1344 "Edge Connector to DRAM"); 1345 break; 1346 case 0x01: /* RDIMM */ 1347 case 0x05: /* Mini-RDIMM */ 1348 PRINT_NXS(60, spd->mod_section.registered.mod_height, 1349 "mod_height (Registered) Module Nominal Height"); 1350 PRINT_NXS(61, spd->mod_section.registered.mod_thickness, 1351 "mod_thickness (Registered) Module Maximum Thickness"); 1352 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card, 1353 "ref_raw_card (Registered) Reference Raw Card Used"); 1354 PRINT_NXS(63, spd->mod_section.registered.modu_attr, 1355 "modu_attr (Registered) DIMM Module Attributes"); 1356 PRINT_NXS(64, spd->mod_section.registered.thermal, 1357 "thermal (Registered) Thermal Heat " 1358 "Spreader Solution"); 1359 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo, 1360 "reg_id_lo (Registered) Register Manufacturer ID " 1361 "Code, LSB"); 1362 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi, 1363 "reg_id_hi (Registered) Register Manufacturer ID " 1364 "Code, MSB"); 1365 PRINT_NXS(67, spd->mod_section.registered.reg_rev, 1366 "reg_rev (Registered) Register " 1367 "Revision Number"); 1368 PRINT_NXS(68, spd->mod_section.registered.reg_type, 1369 "reg_type (Registered) Register Type"); 1370 for (i = 69; i <= 76; i++) { 1371 printf("%-3d : %02x rcw[%d]\n", i, 1372 spd->mod_section.registered.rcw[i-69], i-69); 1373 } 1374 break; 1375 default: 1376 /* Module-specific Section, Unsupported Module Type */ 1377 printf("%-3d-%3d: ", 60, 116); 1378 1379 for (i = 60; i <= 116; i++) 1380 printf("%02x", spd->mod_section.uc[i - 60]); 1381 1382 break; 1383 } 1384 1385 /* Unique Module ID: Bytes 117-125 */ 1386 PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); 1387 PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); 1388 PRINT_NXS(119, spd->mloc, "Mfg Location"); 1389 PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date"); 1390 1391 printf("%-3d-%3d: ", 122, 125); 1392 1393 for (i = 122; i <= 125; i++) 1394 printf("%02x ", spd->sernum[i - 122]); 1395 printf(" Module Serial Number\n"); 1396 1397 /* CRC: Bytes 126-127 */ 1398 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); 1399 1400 /* Other Manufacturer Fields and User Space: Bytes 128-255 */ 1401 printf("%-3d-%3d: ", 128, 145); 1402 for (i = 128; i <= 145; i++) 1403 printf("%02x ", spd->mpart[i - 128]); 1404 printf(" Mfg's Module Part Number\n"); 1405 1406 PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1], 1407 "Module Revision code"); 1408 1409 PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); 1410 PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); 1411 1412 printf("%-3d-%3d: ", 150, 175); 1413 for (i = 150; i <= 175; i++) 1414 printf("%02x ", spd->msd[i - 150]); 1415 printf(" Mfg's Specific Data\n"); 1416 1417 printf("%-3d-%3d: ", 176, 255); 1418 for (i = 176; i <= 255; i++) 1419 printf("%02x", spd->cust[i - 176]); 1420 printf(" Mfg's Specific Data\n"); 1421 1422 } 1423 #endif 1424 1425 #ifdef CONFIG_SYS_FSL_DDR4 1426 void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd) 1427 { 1428 unsigned int i; 1429 1430 /* General Section: Bytes 0-127 */ 1431 1432 #define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); 1433 #define PRINT_NNXXS(n0, n1, x0, x1, s) \ 1434 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); 1435 1436 PRINT_NXS(0, spd->info_size_crc, 1437 "info_size_crc bytes written into serial memory, CRC coverage"); 1438 PRINT_NXS(1, spd->spd_rev, 1439 "spd_rev SPD Revision"); 1440 PRINT_NXS(2, spd->mem_type, 1441 "mem_type Key Byte / DRAM Device Type"); 1442 PRINT_NXS(3, spd->module_type, 1443 "module_type Key Byte / Module Type"); 1444 PRINT_NXS(4, spd->density_banks, 1445 "density_banks SDRAM Density and Banks"); 1446 PRINT_NXS(5, spd->addressing, 1447 "addressing SDRAM Addressing"); 1448 PRINT_NXS(6, spd->package_type, 1449 "package_type Package type"); 1450 PRINT_NXS(7, spd->opt_feature, 1451 "opt_feature Optional features"); 1452 PRINT_NXS(8, spd->thermal_ref, 1453 "thermal_ref Thermal and Refresh options"); 1454 PRINT_NXS(9, spd->oth_opt_features, 1455 "oth_opt_features Other SDRAM optional features"); 1456 PRINT_NXS(10, spd->res_10, 1457 "res_10 Reserved"); 1458 PRINT_NXS(11, spd->module_vdd, 1459 "module_vdd Module Nominal Voltage, VDD"); 1460 PRINT_NXS(12, spd->organization, 1461 "organization Module Organization"); 1462 PRINT_NXS(13, spd->bus_width, 1463 "bus_width Module Memory Bus Width"); 1464 PRINT_NXS(14, spd->therm_sensor, 1465 "therm_sensor Module Thermal Sensor"); 1466 PRINT_NXS(15, spd->ext_type, 1467 "ext_type Extended module type"); 1468 PRINT_NXS(16, spd->res_16, 1469 "res_16 Reserved"); 1470 PRINT_NXS(17, spd->timebases, 1471 "timebases MTb and FTB"); 1472 PRINT_NXS(18, spd->tck_min, 1473 "tck_min tCKAVGmin"); 1474 PRINT_NXS(19, spd->tck_max, 1475 "tck_max TCKAVGmax"); 1476 PRINT_NXS(20, spd->caslat_b1, 1477 "caslat_b1 CAS latencies, 1st byte"); 1478 PRINT_NXS(21, spd->caslat_b2, 1479 "caslat_b2 CAS latencies, 2nd byte"); 1480 PRINT_NXS(22, spd->caslat_b3, 1481 "caslat_b3 CAS latencies, 3rd byte "); 1482 PRINT_NXS(23, spd->caslat_b4, 1483 "caslat_b4 CAS latencies, 4th byte"); 1484 PRINT_NXS(24, spd->taa_min, 1485 "taa_min Min CAS Latency Time"); 1486 PRINT_NXS(25, spd->trcd_min, 1487 "trcd_min Min RAS# to CAS# Delay Time"); 1488 PRINT_NXS(26, spd->trp_min, 1489 "trp_min Min Row Precharge Delay Time"); 1490 PRINT_NXS(27, spd->tras_trc_ext, 1491 "tras_trc_ext Upper Nibbles for tRAS and tRC"); 1492 PRINT_NXS(28, spd->tras_min_lsb, 1493 "tras_min_lsb tRASmin, lsb"); 1494 PRINT_NXS(29, spd->trc_min_lsb, 1495 "trc_min_lsb tRCmin, lsb"); 1496 PRINT_NXS(30, spd->trfc1_min_lsb, 1497 "trfc1_min_lsb Min Refresh Recovery Delay Time, LSB"); 1498 PRINT_NXS(31, spd->trfc1_min_msb, 1499 "trfc1_min_msb Min Refresh Recovery Delay Time, MSB "); 1500 PRINT_NXS(32, spd->trfc2_min_lsb, 1501 "trfc2_min_lsb Min Refresh Recovery Delay Time, LSB"); 1502 PRINT_NXS(33, spd->trfc2_min_msb, 1503 "trfc2_min_msb Min Refresh Recovery Delay Time, MSB"); 1504 PRINT_NXS(34, spd->trfc4_min_lsb, 1505 "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB"); 1506 PRINT_NXS(35, spd->trfc4_min_msb, 1507 "trfc4_min_msb Min Refresh Recovery Delay Time, MSB"); 1508 PRINT_NXS(36, spd->tfaw_msb, 1509 "tfaw_msb Upper Nibble for tFAW"); 1510 PRINT_NXS(37, spd->tfaw_min, 1511 "tfaw_min tFAW, lsb"); 1512 PRINT_NXS(38, spd->trrds_min, 1513 "trrds_min tRRD_Smin, MTB"); 1514 PRINT_NXS(39, spd->trrdl_min, 1515 "trrdl_min tRRD_Lmin, MTB"); 1516 PRINT_NXS(40, spd->tccdl_min, 1517 "tccdl_min tCCS_Lmin, MTB"); 1518 1519 printf("%-3d-%3d: ", 41, 59); /* Reserved, General Section */ 1520 for (i = 41; i <= 59; i++) 1521 printf("%02x ", spd->res_41[i - 41]); 1522 1523 puts("\n"); 1524 printf("%-3d-%3d: ", 60, 77); 1525 for (i = 60; i <= 77; i++) 1526 printf("%02x ", spd->mapping[i - 60]); 1527 puts(" mapping[] Connector to SDRAM bit map\n"); 1528 1529 PRINT_NXS(117, spd->fine_tccdl_min, 1530 "fine_tccdl_min Fine offset for tCCD_Lmin"); 1531 PRINT_NXS(118, spd->fine_trrdl_min, 1532 "fine_trrdl_min Fine offset for tRRD_Lmin"); 1533 PRINT_NXS(119, spd->fine_trrds_min, 1534 "fine_trrds_min Fine offset for tRRD_Smin"); 1535 PRINT_NXS(120, spd->fine_trc_min, 1536 "fine_trc_min Fine offset for tRCmin"); 1537 PRINT_NXS(121, spd->fine_trp_min, 1538 "fine_trp_min Fine offset for tRPmin"); 1539 PRINT_NXS(122, spd->fine_trcd_min, 1540 "fine_trcd_min Fine offset for tRCDmin"); 1541 PRINT_NXS(123, spd->fine_taa_min, 1542 "fine_taa_min Fine offset for tAAmin"); 1543 PRINT_NXS(124, spd->fine_tck_max, 1544 "fine_tck_max Fine offset for tCKAVGmax"); 1545 PRINT_NXS(125, spd->fine_tck_min, 1546 "fine_tck_min Fine offset for tCKAVGmin"); 1547 1548 /* CRC: Bytes 126-127 */ 1549 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); 1550 1551 switch (spd->module_type) { 1552 case 0x02: /* UDIMM */ 1553 case 0x03: /* SO-DIMM */ 1554 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height, 1555 "mod_height (Unbuffered) Module Nominal Height"); 1556 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness, 1557 "mod_thickness (Unbuffered) Module Maximum Thickness"); 1558 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card, 1559 "ref_raw_card (Unbuffered) Reference Raw Card Used"); 1560 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping, 1561 "addr_mapping (Unbuffered) Address mapping from Edge Connector to DRAM"); 1562 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0], 1563 spd->mod_section.unbuffered.crc[1], " Module CRC"); 1564 break; 1565 case 0x01: /* RDIMM */ 1566 PRINT_NXS(128, spd->mod_section.registered.mod_height, 1567 "mod_height (Registered) Module Nominal Height"); 1568 PRINT_NXS(129, spd->mod_section.registered.mod_thickness, 1569 "mod_thickness (Registered) Module Maximum Thickness"); 1570 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card, 1571 "ref_raw_card (Registered) Reference Raw Card Used"); 1572 PRINT_NXS(131, spd->mod_section.registered.modu_attr, 1573 "modu_attr (Registered) DIMM Module Attributes"); 1574 PRINT_NXS(132, spd->mod_section.registered.thermal, 1575 "thermal (Registered) Thermal Heat Spreader Solution"); 1576 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo, 1577 "reg_id_lo (Registered) Register Manufacturer ID Code, LSB"); 1578 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi, 1579 "reg_id_hi (Registered) Register Manufacturer ID Code, MSB"); 1580 PRINT_NXS(135, spd->mod_section.registered.reg_rev, 1581 "reg_rev (Registered) Register Revision Number"); 1582 PRINT_NXS(136, spd->mod_section.registered.reg_map, 1583 "reg_map (Registered) Address mapping"); 1584 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0], 1585 spd->mod_section.registered.crc[1], " Module CRC"); 1586 break; 1587 case 0x04: /* LRDIMM */ 1588 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height, 1589 "mod_height (Loadreduced) Module Nominal Height"); 1590 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness, 1591 "mod_thickness (Loadreduced) Module Maximum Thickness"); 1592 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card, 1593 "ref_raw_card (Loadreduced) Reference Raw Card Used"); 1594 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr, 1595 "modu_attr (Loadreduced) DIMM Module Attributes"); 1596 PRINT_NXS(132, spd->mod_section.loadreduced.thermal, 1597 "thermal (Loadreduced) Thermal Heat Spreader Solution"); 1598 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo, 1599 "reg_id_lo (Loadreduced) Register Manufacturer ID Code, LSB"); 1600 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi, 1601 "reg_id_hi (Loadreduced) Register Manufacturer ID Code, MSB"); 1602 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev, 1603 "reg_rev (Loadreduced) Register Revision Number"); 1604 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map, 1605 "reg_map (Loadreduced) Address mapping"); 1606 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv, 1607 "reg_drv (Loadreduced) Reg output drive strength"); 1608 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck, 1609 "reg_drv_ck (Loadreduced) Reg output drive strength for CK"); 1610 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev, 1611 "data_buf_rev (Loadreduced) Data Buffer Revision Numbe"); 1612 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0, 1613 "vrefqe_r0 (Loadreduced) DRAM VrefDQ for Package Rank 0"); 1614 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1, 1615 "vrefqe_r1 (Loadreduced) DRAM VrefDQ for Package Rank 1"); 1616 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2, 1617 "vrefqe_r2 (Loadreduced) DRAM VrefDQ for Package Rank 2"); 1618 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3, 1619 "vrefqe_r3 (Loadreduced) DRAM VrefDQ for Package Rank 3"); 1620 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf, 1621 "data_intf (Loadreduced) Data Buffer VrefDQ for DRAM Interface"); 1622 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866, 1623 "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT"); 1624 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400, 1625 "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT"); 1626 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200, 1627 "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT"); 1628 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv, 1629 "dram_drv (Loadreduced) DRAM Drive Strength"); 1630 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866, 1631 "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)"); 1632 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400, 1633 "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)"); 1634 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200, 1635 "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)"); 1636 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866, 1637 "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)"); 1638 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400, 1639 "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)"); 1640 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200, 1641 "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)"); 1642 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0], 1643 spd->mod_section.loadreduced.crc[1], 1644 " Module CRC"); 1645 break; 1646 default: 1647 /* Module-specific Section, Unsupported Module Type */ 1648 printf("%-3d-%3d: ", 128, 255); 1649 1650 for (i = 128; i <= 255; i++) 1651 printf("%02x", spd->mod_section.uc[i - 128]); 1652 1653 break; 1654 } 1655 1656 /* Unique Module ID: Bytes 320-383 */ 1657 PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); 1658 PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); 1659 PRINT_NXS(322, spd->mloc, "Mfg Location"); 1660 PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date"); 1661 1662 printf("%-3d-%3d: ", 325, 328); 1663 1664 for (i = 325; i <= 328; i++) 1665 printf("%02x ", spd->sernum[i - 325]); 1666 printf(" Module Serial Number\n"); 1667 1668 printf("%-3d-%3d: ", 329, 348); 1669 for (i = 329; i <= 348; i++) 1670 printf("%02x ", spd->mpart[i - 329]); 1671 printf(" Mfg's Module Part Number\n"); 1672 1673 PRINT_NXS(349, spd->mrev, "Module Revision code"); 1674 PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); 1675 PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); 1676 PRINT_NXS(352, spd->stepping, "DRAM stepping"); 1677 1678 printf("%-3d-%3d: ", 353, 381); 1679 for (i = 353; i <= 381; i++) 1680 printf("%02x ", spd->msd[i - 353]); 1681 printf(" Mfg's Specific Data\n"); 1682 } 1683 #endif 1684 1685 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd) 1686 { 1687 #if defined(CONFIG_SYS_FSL_DDR1) 1688 ddr1_spd_dump(spd); 1689 #elif defined(CONFIG_SYS_FSL_DDR2) 1690 ddr2_spd_dump(spd); 1691 #elif defined(CONFIG_SYS_FSL_DDR3) 1692 ddr3_spd_dump(spd); 1693 #elif defined(CONFIG_SYS_FSL_DDR4) 1694 ddr4_spd_dump(spd); 1695 #endif 1696 } 1697 1698 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo, 1699 unsigned int ctrl_mask, 1700 unsigned int dimm_mask, 1701 unsigned int do_mask) 1702 { 1703 unsigned int i, j, retval; 1704 1705 /* STEP 1: DIMM SPD data */ 1706 if (do_mask & STEP_GET_SPD) { 1707 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { 1708 if (!(ctrl_mask & (1 << i))) 1709 continue; 1710 1711 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 1712 if (!(dimm_mask & (1 << j))) 1713 continue; 1714 1715 printf("SPD info: Controller=%u " 1716 "DIMM=%u\n", i, j); 1717 generic_spd_dump( 1718 &(pinfo->spd_installed_dimms[i][j])); 1719 printf("\n"); 1720 } 1721 printf("\n"); 1722 } 1723 printf("\n"); 1724 } 1725 1726 /* STEP 2: DIMM Parameters */ 1727 if (do_mask & STEP_COMPUTE_DIMM_PARMS) { 1728 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { 1729 if (!(ctrl_mask & (1 << i))) 1730 continue; 1731 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 1732 if (!(dimm_mask & (1 << j))) 1733 continue; 1734 printf("DIMM parameters: Controller=%u " 1735 "DIMM=%u\n", i, j); 1736 print_dimm_parameters( 1737 &(pinfo->dimm_params[i][j])); 1738 printf("\n"); 1739 } 1740 printf("\n"); 1741 } 1742 printf("\n"); 1743 } 1744 1745 /* STEP 3: Common Parameters */ 1746 if (do_mask & STEP_COMPUTE_COMMON_PARMS) { 1747 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { 1748 if (!(ctrl_mask & (1 << i))) 1749 continue; 1750 printf("\"lowest common\" DIMM parameters: " 1751 "Controller=%u\n", i); 1752 print_lowest_common_dimm_parameters( 1753 &pinfo->common_timing_params[i]); 1754 printf("\n"); 1755 } 1756 printf("\n"); 1757 } 1758 1759 /* STEP 4: User Configuration Options */ 1760 if (do_mask & STEP_GATHER_OPTS) { 1761 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { 1762 if (!(ctrl_mask & (1 << i))) 1763 continue; 1764 printf("User Config Options: Controller=%u\n", i); 1765 print_memctl_options(&pinfo->memctl_opts[i]); 1766 printf("\n"); 1767 } 1768 printf("\n"); 1769 } 1770 1771 /* STEP 5: Address assignment */ 1772 if (do_mask & STEP_ASSIGN_ADDRESSES) { 1773 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { 1774 if (!(ctrl_mask & (1 << i))) 1775 continue; 1776 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 1777 printf("Address Assignment: Controller=%u " 1778 "DIMM=%u\n", i, j); 1779 printf("Don't have this functionality yet\n"); 1780 } 1781 printf("\n"); 1782 } 1783 printf("\n"); 1784 } 1785 1786 /* STEP 6: computed controller register values */ 1787 if (do_mask & STEP_COMPUTE_REGS) { 1788 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { 1789 if (!(ctrl_mask & (1 << i))) 1790 continue; 1791 printf("Computed Register Values: Controller=%u\n", i); 1792 print_fsl_memctl_config_regs( 1793 &pinfo->fsl_ddr_config_reg[i]); 1794 retval = check_fsl_memctl_config_regs( 1795 &pinfo->fsl_ddr_config_reg[i]); 1796 if (retval) { 1797 printf("check_fsl_memctl_config_regs " 1798 "result = %u\n", retval); 1799 } 1800 printf("\n"); 1801 } 1802 printf("\n"); 1803 } 1804 } 1805 1806 struct data_strings { 1807 const char *data_name; 1808 unsigned int step_mask; 1809 unsigned int dimm_number_required; 1810 }; 1811 1812 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm} 1813 1814 static unsigned int fsl_ddr_parse_interactive_cmd( 1815 char **argv, 1816 int argc, 1817 unsigned int *pstep_mask, 1818 unsigned int *pctlr_mask, 1819 unsigned int *pdimm_mask, 1820 unsigned int *pdimm_number_required 1821 ) { 1822 1823 static const struct data_strings options[] = { 1824 DATA_OPTIONS(spd, STEP_GET_SPD, 1), 1825 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1), 1826 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0), 1827 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0), 1828 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0), 1829 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0), 1830 }; 1831 static const unsigned int n_opts = ARRAY_SIZE(options); 1832 1833 unsigned int i, j; 1834 unsigned int error = 0; 1835 1836 for (i = 1; i < argc; i++) { 1837 unsigned int matched = 0; 1838 1839 for (j = 0; j < n_opts; j++) { 1840 if (strcmp(options[j].data_name, argv[i]) != 0) 1841 continue; 1842 *pstep_mask |= options[j].step_mask; 1843 *pdimm_number_required = 1844 options[j].dimm_number_required; 1845 matched = 1; 1846 break; 1847 } 1848 1849 if (matched) 1850 continue; 1851 1852 if (argv[i][0] == 'c') { 1853 char c = argv[i][1]; 1854 if (isdigit(c)) 1855 *pctlr_mask |= 1 << (c - '0'); 1856 continue; 1857 } 1858 1859 if (argv[i][0] == 'd') { 1860 char c = argv[i][1]; 1861 if (isdigit(c)) 1862 *pdimm_mask |= 1 << (c - '0'); 1863 continue; 1864 } 1865 1866 printf("unknown arg %s\n", argv[i]); 1867 *pstep_mask = 0; 1868 error = 1; 1869 break; 1870 } 1871 1872 return error; 1873 } 1874 1875 int fsl_ddr_interactive_env_var_exists(void) 1876 { 1877 char buffer[CONFIG_SYS_CBSIZE]; 1878 1879 if (env_get_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0) 1880 return 1; 1881 1882 return 0; 1883 } 1884 1885 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set) 1886 { 1887 unsigned long long ddrsize; 1888 const char *prompt = "FSL DDR>"; 1889 char buffer[CONFIG_SYS_CBSIZE]; 1890 char buffer2[CONFIG_SYS_CBSIZE]; 1891 char *p = NULL; 1892 char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ 1893 int argc; 1894 unsigned int next_step = STEP_GET_SPD; 1895 const char *usage = { 1896 "commands:\n" 1897 "print print SPD and intermediate computed data\n" 1898 "reset reboot machine\n" 1899 "recompute reload SPD and options to default and recompute regs\n" 1900 "edit modify spd, parameter, or option\n" 1901 "compute recompute registers from current next_step to end\n" 1902 "copy copy parameters\n" 1903 "next_step shows current next_step\n" 1904 "help this message\n" 1905 "go program the memory controller and continue with u-boot\n" 1906 }; 1907 1908 if (var_is_set) { 1909 if (env_get_f("ddr_interactive", buffer2, 1910 CONFIG_SYS_CBSIZE) > 0) 1911 p = buffer2; 1912 else 1913 var_is_set = 0; 1914 } 1915 1916 /* 1917 * The strategy for next_step is that it points to the next 1918 * step in the computation process that needs to be done. 1919 */ 1920 while (1) { 1921 if (var_is_set) { 1922 char *pend = strchr(p, ';'); 1923 if (pend) { 1924 /* found command separator, copy sub-command */ 1925 *pend = '\0'; 1926 strcpy(buffer, p); 1927 p = pend + 1; 1928 } else { 1929 /* separator not found, copy whole string */ 1930 strcpy(buffer, p); 1931 p = NULL; 1932 var_is_set = 0; 1933 } 1934 } else { 1935 /* 1936 * No need to worry for buffer overflow here in 1937 * this function; cli_readline() maxes out at 1938 * CFG_CBSIZE 1939 */ 1940 cli_readline_into_buffer(prompt, buffer, 0); 1941 } 1942 argc = cli_simple_parse_line(buffer, argv); 1943 if (argc == 0) 1944 continue; 1945 1946 1947 if (strcmp(argv[0], "help") == 0) { 1948 puts(usage); 1949 continue; 1950 } 1951 1952 if (strcmp(argv[0], "next_step") == 0) { 1953 printf("next_step = 0x%02X (%s)\n", 1954 next_step, 1955 step_to_string(next_step)); 1956 continue; 1957 } 1958 1959 if (strcmp(argv[0], "copy") == 0) { 1960 unsigned int error = 0; 1961 unsigned int step_mask = 0; 1962 unsigned int src_ctlr_mask = 0; 1963 unsigned int src_dimm_mask = 0; 1964 unsigned int dimm_number_required = 0; 1965 unsigned int src_ctlr_num = 0; 1966 unsigned int src_dimm_num = 0; 1967 unsigned int dst_ctlr_num = -1; 1968 unsigned int dst_dimm_num = -1; 1969 unsigned int i, num_dest_parms; 1970 1971 if (argc == 1) { 1972 printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n"); 1973 continue; 1974 } 1975 1976 error = fsl_ddr_parse_interactive_cmd( 1977 argv, argc, 1978 &step_mask, 1979 &src_ctlr_mask, 1980 &src_dimm_mask, 1981 &dimm_number_required 1982 ); 1983 1984 /* XXX: only dimm_number_required and step_mask will 1985 be used by this function. Parse the controller and 1986 DIMM number separately because it is easier. */ 1987 1988 if (error) 1989 continue; 1990 1991 /* parse source destination controller / DIMM */ 1992 1993 num_dest_parms = dimm_number_required ? 2 : 1; 1994 1995 for (i = 0; i < argc; i++) { 1996 if (argv[i][0] == 'c') { 1997 char c = argv[i][1]; 1998 if (isdigit(c)) { 1999 src_ctlr_num = (c - '0'); 2000 break; 2001 } 2002 } 2003 } 2004 2005 for (i = 0; i < argc; i++) { 2006 if (argv[i][0] == 'd') { 2007 char c = argv[i][1]; 2008 if (isdigit(c)) { 2009 src_dimm_num = (c - '0'); 2010 break; 2011 } 2012 } 2013 } 2014 2015 /* parse destination controller / DIMM */ 2016 2017 for (i = argc - 1; i >= argc - num_dest_parms; i--) { 2018 if (argv[i][0] == 'c') { 2019 char c = argv[i][1]; 2020 if (isdigit(c)) { 2021 dst_ctlr_num = (c - '0'); 2022 break; 2023 } 2024 } 2025 } 2026 2027 for (i = argc - 1; i >= argc - num_dest_parms; i--) { 2028 if (argv[i][0] == 'd') { 2029 char c = argv[i][1]; 2030 if (isdigit(c)) { 2031 dst_dimm_num = (c - '0'); 2032 break; 2033 } 2034 } 2035 } 2036 2037 /* TODO: validate inputs */ 2038 2039 debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n", 2040 src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask); 2041 2042 2043 switch (step_mask) { 2044 2045 case STEP_GET_SPD: 2046 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]), 2047 &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]), 2048 sizeof(pinfo->spd_installed_dimms[0][0])); 2049 break; 2050 2051 case STEP_COMPUTE_DIMM_PARMS: 2052 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]), 2053 &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]), 2054 sizeof(pinfo->dimm_params[0][0])); 2055 break; 2056 2057 case STEP_COMPUTE_COMMON_PARMS: 2058 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]), 2059 &(pinfo->common_timing_params[src_ctlr_num]), 2060 sizeof(pinfo->common_timing_params[0])); 2061 break; 2062 2063 case STEP_GATHER_OPTS: 2064 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]), 2065 &(pinfo->memctl_opts[src_ctlr_num]), 2066 sizeof(pinfo->memctl_opts[0])); 2067 break; 2068 2069 /* someday be able to have addresses to copy addresses... */ 2070 2071 case STEP_COMPUTE_REGS: 2072 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]), 2073 &(pinfo->fsl_ddr_config_reg[src_ctlr_num]), 2074 sizeof(pinfo->memctl_opts[0])); 2075 break; 2076 2077 default: 2078 printf("unexpected step_mask value\n"); 2079 } 2080 2081 continue; 2082 2083 } 2084 2085 if (strcmp(argv[0], "edit") == 0) { 2086 unsigned int error = 0; 2087 unsigned int step_mask = 0; 2088 unsigned int ctlr_mask = 0; 2089 unsigned int dimm_mask = 0; 2090 char *p_element = NULL; 2091 char *p_value = NULL; 2092 unsigned int dimm_number_required = 0; 2093 unsigned int ctrl_num; 2094 unsigned int dimm_num; 2095 2096 if (argc == 1) { 2097 /* Only the element and value must be last */ 2098 printf("edit <c#> <d#> " 2099 "<spd|dimmparms|commonparms|opts|" 2100 "addresses|regs> <element> <value>\n"); 2101 printf("for spd, specify byte number for " 2102 "element\n"); 2103 continue; 2104 } 2105 2106 error = fsl_ddr_parse_interactive_cmd( 2107 argv, argc - 2, 2108 &step_mask, 2109 &ctlr_mask, 2110 &dimm_mask, 2111 &dimm_number_required 2112 ); 2113 2114 if (error) 2115 continue; 2116 2117 2118 /* Check arguments */ 2119 2120 /* ERROR: If no steps were found */ 2121 if (step_mask == 0) { 2122 printf("Error: No valid steps were specified " 2123 "in argument.\n"); 2124 continue; 2125 } 2126 2127 /* ERROR: If multiple steps were found */ 2128 if (step_mask & (step_mask - 1)) { 2129 printf("Error: Multiple steps specified in " 2130 "argument.\n"); 2131 continue; 2132 } 2133 2134 /* ERROR: Controller not specified */ 2135 if (ctlr_mask == 0) { 2136 printf("Error: controller number not " 2137 "specified or no element and " 2138 "value specified\n"); 2139 continue; 2140 } 2141 2142 if (ctlr_mask & (ctlr_mask - 1)) { 2143 printf("Error: multiple controllers " 2144 "specified, %X\n", ctlr_mask); 2145 continue; 2146 } 2147 2148 /* ERROR: DIMM number not specified */ 2149 if (dimm_number_required && dimm_mask == 0) { 2150 printf("Error: DIMM number number not " 2151 "specified or no element and " 2152 "value specified\n"); 2153 continue; 2154 } 2155 2156 if (dimm_mask & (dimm_mask - 1)) { 2157 printf("Error: multipled DIMMs specified\n"); 2158 continue; 2159 } 2160 2161 p_element = argv[argc - 2]; 2162 p_value = argv[argc - 1]; 2163 2164 ctrl_num = __ilog2(ctlr_mask); 2165 dimm_num = __ilog2(dimm_mask); 2166 2167 switch (step_mask) { 2168 case STEP_GET_SPD: 2169 { 2170 unsigned int element_num; 2171 unsigned int value; 2172 2173 element_num = simple_strtoul(p_element, 2174 NULL, 0); 2175 value = simple_strtoul(p_value, 2176 NULL, 0); 2177 fsl_ddr_spd_edit(pinfo, 2178 ctrl_num, 2179 dimm_num, 2180 element_num, 2181 value); 2182 next_step = STEP_COMPUTE_DIMM_PARMS; 2183 } 2184 break; 2185 2186 case STEP_COMPUTE_DIMM_PARMS: 2187 fsl_ddr_dimm_parameters_edit( 2188 pinfo, ctrl_num, dimm_num, 2189 p_element, p_value); 2190 next_step = STEP_COMPUTE_COMMON_PARMS; 2191 break; 2192 2193 case STEP_COMPUTE_COMMON_PARMS: 2194 lowest_common_dimm_parameters_edit(pinfo, 2195 ctrl_num, p_element, p_value); 2196 next_step = STEP_GATHER_OPTS; 2197 break; 2198 2199 case STEP_GATHER_OPTS: 2200 fsl_ddr_options_edit(pinfo, ctrl_num, 2201 p_element, p_value); 2202 next_step = STEP_ASSIGN_ADDRESSES; 2203 break; 2204 2205 case STEP_ASSIGN_ADDRESSES: 2206 printf("editing of address assignment " 2207 "not yet implemented\n"); 2208 break; 2209 2210 case STEP_COMPUTE_REGS: 2211 { 2212 fsl_ddr_regs_edit(pinfo, 2213 ctrl_num, 2214 p_element, 2215 p_value); 2216 next_step = STEP_PROGRAM_REGS; 2217 } 2218 break; 2219 2220 default: 2221 printf("programming error\n"); 2222 while (1) 2223 ; 2224 break; 2225 } 2226 continue; 2227 } 2228 2229 if (strcmp(argv[0], "reset") == 0) { 2230 /* 2231 * Reboot machine. 2232 * Args don't seem to matter because this 2233 * doesn't return 2234 */ 2235 do_reset(NULL, 0, 0, NULL); 2236 printf("Reset didn't work\n"); 2237 } 2238 2239 if (strcmp(argv[0], "recompute") == 0) { 2240 /* 2241 * Recalculate everything, starting with 2242 * loading SPD EEPROM from DIMMs 2243 */ 2244 next_step = STEP_GET_SPD; 2245 ddrsize = fsl_ddr_compute(pinfo, next_step, 0); 2246 continue; 2247 } 2248 2249 if (strcmp(argv[0], "compute") == 0) { 2250 /* 2251 * Compute rest of steps starting at 2252 * the current next_step/ 2253 */ 2254 ddrsize = fsl_ddr_compute(pinfo, next_step, 0); 2255 continue; 2256 } 2257 2258 if (strcmp(argv[0], "print") == 0) { 2259 unsigned int error = 0; 2260 unsigned int step_mask = 0; 2261 unsigned int ctlr_mask = 0; 2262 unsigned int dimm_mask = 0; 2263 unsigned int dimm_number_required = 0; 2264 2265 if (argc == 1) { 2266 printf("print [c<n>] [d<n>] [spd] [dimmparms] " 2267 "[commonparms] [opts] [addresses] [regs]\n"); 2268 continue; 2269 } 2270 2271 error = fsl_ddr_parse_interactive_cmd( 2272 argv, argc, 2273 &step_mask, 2274 &ctlr_mask, 2275 &dimm_mask, 2276 &dimm_number_required 2277 ); 2278 2279 if (error) 2280 continue; 2281 2282 /* If no particular controller was found, print all */ 2283 if (ctlr_mask == 0) 2284 ctlr_mask = 0xFF; 2285 2286 /* If no particular dimm was found, print all dimms. */ 2287 if (dimm_mask == 0) 2288 dimm_mask = 0xFF; 2289 2290 /* If no steps were found, print all steps. */ 2291 if (step_mask == 0) 2292 step_mask = STEP_ALL; 2293 2294 fsl_ddr_printinfo(pinfo, ctlr_mask, 2295 dimm_mask, step_mask); 2296 continue; 2297 } 2298 2299 if (strcmp(argv[0], "go") == 0) { 2300 if (next_step) 2301 ddrsize = fsl_ddr_compute(pinfo, next_step, 0); 2302 break; 2303 } 2304 2305 printf("unknown command %s\n", argv[0]); 2306 } 2307 2308 debug("end of memory = %llu\n", (u64)ddrsize); 2309 2310 return ddrsize; 2311 } 2312