1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 #include <fsl_immap.h> 12 #include <fsl_ddr.h> 13 #include <fsl_errata.h> 14 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ 15 defined(CONFIG_ARM) 16 #include <asm/arch/clock.h> 17 #endif 18 19 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \ 20 defined(CONFIG_SYS_FSL_ERRATUM_A009803) 21 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 22 { 23 int timeout = 1000; 24 25 ddr_out32(ptr, value); 26 27 while (ddr_in32(ptr) & bits) { 28 udelay(100); 29 timeout--; 30 } 31 if (timeout <= 0) 32 puts("Error: wait for clear timeout.\n"); 33 } 34 #endif 35 36 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 37 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 38 #endif 39 40 /* 41 * regs has the to-be-set values for DDR controller registers 42 * ctrl_num is the DDR controller number 43 * step: 0 goes through the initialization in one pass 44 * 1 sets registers and returns before enabling controller 45 * 2 resumes from step 1 and continues to initialize 46 * Dividing the initialization to two steps to deassert DDR reset signal 47 * to comply with JEDEC specs for RDIMMs. 48 */ 49 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 50 unsigned int ctrl_num, int step) 51 { 52 unsigned int i, bus_width; 53 struct ccsr_ddr __iomem *ddr; 54 u32 temp32; 55 u32 total_gb_size_per_controller; 56 int timeout; 57 58 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 59 u32 mr6; 60 u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */ 61 u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ 62 u32 *vref_seq = vref_seq1; 63 #endif 64 #ifdef CONFIG_FSL_DDR_BIST 65 u32 mtcr, err_detect, err_sbe; 66 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; 67 #endif 68 #ifdef CONFIG_FSL_DDR_BIST 69 char buffer[CONFIG_SYS_CBSIZE]; 70 #endif 71 switch (ctrl_num) { 72 case 0: 73 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 74 break; 75 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) 76 case 1: 77 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 78 break; 79 #endif 80 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) 81 case 2: 82 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 83 break; 84 #endif 85 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) 86 case 3: 87 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 88 break; 89 #endif 90 default: 91 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 92 return; 93 } 94 95 if (step == 2) 96 goto step2; 97 98 /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/ 99 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 100 101 if (regs->ddr_eor) 102 ddr_out32(&ddr->eor, regs->ddr_eor); 103 104 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 105 106 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 107 if (i == 0) { 108 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 109 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 110 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 111 112 } else if (i == 1) { 113 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 114 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 115 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 116 117 } else if (i == 2) { 118 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 119 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 120 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 121 122 } else if (i == 3) { 123 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 124 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 125 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 126 } 127 } 128 129 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 130 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 131 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 132 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 133 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 134 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 135 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); 136 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); 137 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); 138 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); 139 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 140 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); 141 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); 142 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); 143 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); 144 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); 145 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 146 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 147 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 148 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 149 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 150 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 151 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 152 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 153 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); 154 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); 155 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); 156 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); 157 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); 158 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); 159 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); 160 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); 161 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 162 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 163 ddr_out32(&ddr->sdram_interval, 164 regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); 165 #else 166 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 167 #endif 168 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 169 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 170 #ifndef CONFIG_SYS_FSL_DDR_EMU 171 /* 172 * Skip these two registers if running on emulator 173 * because emulator doesn't have skew between bytes. 174 */ 175 176 if (regs->ddr_wrlvl_cntl_2) 177 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 178 if (regs->ddr_wrlvl_cntl_3) 179 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 180 #endif 181 182 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 183 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 184 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 185 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); 186 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); 187 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); 188 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); 189 #ifdef CONFIG_DEEP_SLEEP 190 if (is_warm_boot()) { 191 ddr_out32(&ddr->sdram_cfg_2, 192 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 193 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 194 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 195 196 /* DRAM VRef will not be trained */ 197 ddr_out32(&ddr->ddr_cdr2, 198 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 199 } else 200 #endif 201 { 202 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 203 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 204 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 205 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 206 } 207 208 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803 209 /* part 1 of 2 */ 210 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 211 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */ 212 ddr_out32(&ddr->ddr_sdram_rcw_2, 213 regs->ddr_sdram_rcw_2 & ~0x0f000000); 214 } 215 ddr_out32(&ddr->err_disable, regs->err_disable | 216 DDR_ERR_DISABLE_APED); 217 } 218 #else 219 ddr_out32(&ddr->err_disable, regs->err_disable); 220 #endif 221 ddr_out32(&ddr->err_int_en, regs->err_int_en); 222 for (i = 0; i < 64; i++) { 223 if (regs->debug[i]) { 224 debug("Write to debug_%d as %08x\n", 225 i+1, regs->debug[i]); 226 ddr_out32(&ddr->debug[i], regs->debug[i]); 227 } 228 } 229 230 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 231 /* Part 1 of 2 */ 232 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 233 /* Disable DRAM VRef training */ 234 ddr_out32(&ddr->ddr_cdr2, 235 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 236 /* disable transmit bit deskew */ 237 temp32 = ddr_in32(&ddr->debug[28]); 238 temp32 |= DDR_TX_BD_DIS; 239 ddr_out32(&ddr->debug[28], temp32); 240 ddr_out32(&ddr->debug[25], 0x9000); 241 } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) { 242 /* Output enable forced off */ 243 ddr_out32(&ddr->debug[37], 1 << 31); 244 /* Enable Vref training */ 245 ddr_out32(&ddr->ddr_cdr2, 246 regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN); 247 } else { 248 debug("Erratum A008511 doesn't apply.\n"); 249 } 250 #endif 251 252 #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \ 253 defined(CONFIG_SYS_FSL_ERRATUM_A008511) 254 /* Disable D_INIT */ 255 ddr_out32(&ddr->sdram_cfg_2, 256 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 257 #endif 258 259 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801 260 temp32 = ddr_in32(&ddr->debug[25]); 261 temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; 262 temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; 263 ddr_out32(&ddr->debug[25], temp32); 264 #endif 265 266 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165 267 temp32 = get_ddr_freq(ctrl_num) / 1000000; 268 if ((temp32 > 1900) && (temp32 < 2300)) { 269 temp32 = ddr_in32(&ddr->debug[28]); 270 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000); 271 } 272 #endif 273 /* 274 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 275 * deasserted. Clocks start when any chip select is enabled and clock 276 * control register is set. Because all DDR components are connected to 277 * one reset signal, this needs to be done in two steps. Step 1 is to 278 * get the clocks started. Step 2 resumes after reset signal is 279 * deasserted. 280 */ 281 if (step == 1) { 282 udelay(200); 283 return; 284 } 285 286 step2: 287 /* Set, but do not enable the memory */ 288 temp32 = regs->ddr_sdram_cfg; 289 temp32 &= ~(SDRAM_CFG_MEM_EN); 290 ddr_out32(&ddr->sdram_cfg, temp32); 291 292 /* 293 * 500 painful micro-seconds must elapse between 294 * the DDR clock setup and the DDR config enable. 295 * DDR2 need 200 us, and DDR3 need 500 us from spec, 296 * we choose the max, that is 500 us for all of case. 297 */ 298 udelay(500); 299 mb(); 300 isb(); 301 302 #ifdef CONFIG_DEEP_SLEEP 303 if (is_warm_boot()) { 304 /* enter self-refresh */ 305 temp32 = ddr_in32(&ddr->sdram_cfg_2); 306 temp32 |= SDRAM_CFG2_FRC_SR; 307 ddr_out32(&ddr->sdram_cfg_2, temp32); 308 /* do board specific memory setup */ 309 board_mem_sleep_setup(); 310 311 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 312 } else 313 #endif 314 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 315 /* Let the controller go */ 316 ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN); 317 mb(); 318 isb(); 319 320 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \ 321 defined(CONFIG_SYS_FSL_ERRATUM_A009803) 322 /* Part 2 of 2 */ 323 timeout = 40; 324 /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */ 325 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 326 (timeout > 0)) { 327 udelay(1000); 328 timeout--; 329 } 330 if (timeout <= 0) { 331 printf("Controler %d timeout, debug_2 = %x\n", 332 ctrl_num, ddr_in32(&ddr->debug[1])); 333 } 334 335 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 336 /* This erraum only applies to verion 5.2.0 */ 337 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 338 /* The vref setting sequence is different for range 2 */ 339 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) 340 vref_seq = vref_seq2; 341 342 /* Set VREF */ 343 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 344 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 345 continue; 346 347 mr6 = (regs->ddr_sdram_mode_10 >> 16) | 348 MD_CNTL_MD_EN | 349 MD_CNTL_CS_SEL(i) | 350 MD_CNTL_MD_SEL(6) | 351 0x00200000; 352 temp32 = mr6 | vref_seq[0]; 353 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 354 temp32, MD_CNTL_MD_EN); 355 udelay(1); 356 debug("MR6 = 0x%08x\n", temp32); 357 temp32 = mr6 | vref_seq[1]; 358 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 359 temp32, MD_CNTL_MD_EN); 360 udelay(1); 361 debug("MR6 = 0x%08x\n", temp32); 362 temp32 = mr6 | vref_seq[2]; 363 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 364 temp32, MD_CNTL_MD_EN); 365 udelay(1); 366 debug("MR6 = 0x%08x\n", temp32); 367 } 368 ddr_out32(&ddr->sdram_md_cntl, 0); 369 temp32 = ddr_in32(&ddr->debug[28]); 370 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */ 371 ddr_out32(&ddr->debug[28], temp32); 372 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ 373 /* wait for idle */ 374 timeout = 40; 375 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 376 (timeout > 0)) { 377 udelay(1000); 378 timeout--; 379 } 380 if (timeout <= 0) { 381 printf("Controler %d timeout, debug_2 = %x\n", 382 ctrl_num, ddr_in32(&ddr->debug[1])); 383 } 384 } 385 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 386 387 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803 388 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 389 /* if it's RDIMM */ 390 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { 391 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 392 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 393 continue; 394 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 395 MD_CNTL_MD_EN | 396 MD_CNTL_CS_SEL(i) | 397 0x070000ed, 398 MD_CNTL_MD_EN); 399 udelay(1); 400 } 401 } 402 403 ddr_out32(&ddr->err_disable, 404 regs->err_disable & ~DDR_ERR_DISABLE_APED); 405 } 406 #endif 407 /* Restore D_INIT */ 408 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 409 #endif 410 411 total_gb_size_per_controller = 0; 412 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 413 if (!(regs->cs[i].config & 0x80000000)) 414 continue; 415 total_gb_size_per_controller += 1 << ( 416 ((regs->cs[i].config >> 14) & 0x3) + 2 + 417 ((regs->cs[i].config >> 8) & 0x7) + 12 + 418 ((regs->cs[i].config >> 4) & 0x3) + 0 + 419 ((regs->cs[i].config >> 0) & 0x7) + 8 + 420 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 421 26); /* minus 26 (count of 64M) */ 422 } 423 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 424 total_gb_size_per_controller *= 3; 425 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 426 total_gb_size_per_controller <<= 1; 427 /* 428 * total memory / bus width = transactions needed 429 * transactions needed / data rate = seconds 430 * to add plenty of buffer, double the time 431 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 432 * Let's wait for 800ms 433 */ 434 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 435 >> SDRAM_CFG_DBW_SHIFT); 436 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 437 (get_ddr_freq(ctrl_num) >> 20)) << 2; 438 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 439 debug("total %d GB\n", total_gb_size_per_controller); 440 debug("Need to wait up to %d * 10ms\n", timeout); 441 442 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 443 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 444 (timeout >= 0)) { 445 udelay(10000); /* throttle polling rate */ 446 timeout--; 447 } 448 449 if (timeout <= 0) 450 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 451 452 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 453 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 454 #endif 455 456 #ifdef CONFIG_DEEP_SLEEP 457 if (is_warm_boot()) { 458 /* exit self-refresh */ 459 temp32 = ddr_in32(&ddr->sdram_cfg_2); 460 temp32 &= ~SDRAM_CFG2_FRC_SR; 461 ddr_out32(&ddr->sdram_cfg_2, temp32); 462 } 463 #endif 464 465 #ifdef CONFIG_FSL_DDR_BIST 466 #define BIST_PATTERN1 0xFFFFFFFF 467 #define BIST_PATTERN2 0x0 468 #define BIST_CR 0x80010000 469 #define BIST_CR_EN 0x80000000 470 #define BIST_CR_STAT 0x00000001 471 #define CTLR_INTLV_MASK 0x20000000 472 /* Perform build-in test on memory. Three-way interleaving is not yet 473 * supported by this code. */ 474 if (env_get_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) { 475 puts("Running BIST test. This will take a while..."); 476 cs0_config = ddr_in32(&ddr->cs0_config); 477 cs0_bnds = ddr_in32(&ddr->cs0_bnds); 478 cs1_bnds = ddr_in32(&ddr->cs1_bnds); 479 cs2_bnds = ddr_in32(&ddr->cs2_bnds); 480 cs3_bnds = ddr_in32(&ddr->cs3_bnds); 481 if (cs0_config & CTLR_INTLV_MASK) { 482 /* set bnds to non-interleaving */ 483 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); 484 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); 485 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); 486 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); 487 } 488 ddr_out32(&ddr->mtp1, BIST_PATTERN1); 489 ddr_out32(&ddr->mtp2, BIST_PATTERN1); 490 ddr_out32(&ddr->mtp3, BIST_PATTERN2); 491 ddr_out32(&ddr->mtp4, BIST_PATTERN2); 492 ddr_out32(&ddr->mtp5, BIST_PATTERN1); 493 ddr_out32(&ddr->mtp6, BIST_PATTERN1); 494 ddr_out32(&ddr->mtp7, BIST_PATTERN2); 495 ddr_out32(&ddr->mtp8, BIST_PATTERN2); 496 ddr_out32(&ddr->mtp9, BIST_PATTERN1); 497 ddr_out32(&ddr->mtp10, BIST_PATTERN2); 498 mtcr = BIST_CR; 499 ddr_out32(&ddr->mtcr, mtcr); 500 timeout = 100; 501 while (timeout > 0 && (mtcr & BIST_CR_EN)) { 502 mdelay(1000); 503 timeout--; 504 mtcr = ddr_in32(&ddr->mtcr); 505 } 506 if (timeout <= 0) 507 puts("Timeout\n"); 508 else 509 puts("Done\n"); 510 err_detect = ddr_in32(&ddr->err_detect); 511 err_sbe = ddr_in32(&ddr->err_sbe); 512 if (mtcr & BIST_CR_STAT) { 513 printf("BIST test failed on controller %d.\n", 514 ctrl_num); 515 } 516 if (err_detect || (err_sbe & 0xffff)) { 517 printf("ECC error detected on controller %d.\n", 518 ctrl_num); 519 } 520 521 if (cs0_config & CTLR_INTLV_MASK) { 522 /* restore bnds registers */ 523 ddr_out32(&ddr->cs0_bnds, cs0_bnds); 524 ddr_out32(&ddr->cs1_bnds, cs1_bnds); 525 ddr_out32(&ddr->cs2_bnds, cs2_bnds); 526 ddr_out32(&ddr->cs3_bnds, cs3_bnds); 527 } 528 } 529 #endif 530 } 531