1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 #include <fsl_immap.h> 12 #include <fsl_ddr.h> 13 #include <fsl_errata.h> 14 15 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \ 16 defined(CONFIG_SYS_FSL_ERRATUM_A009803) 17 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 18 { 19 int timeout = 1000; 20 21 ddr_out32(ptr, value); 22 23 while (ddr_in32(ptr) & bits) { 24 udelay(100); 25 timeout--; 26 } 27 if (timeout <= 0) 28 puts("Error: wait for clear timeout.\n"); 29 } 30 #endif 31 32 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 33 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 34 #endif 35 36 /* 37 * regs has the to-be-set values for DDR controller registers 38 * ctrl_num is the DDR controller number 39 * step: 0 goes through the initialization in one pass 40 * 1 sets registers and returns before enabling controller 41 * 2 resumes from step 1 and continues to initialize 42 * Dividing the initialization to two steps to deassert DDR reset signal 43 * to comply with JEDEC specs for RDIMMs. 44 */ 45 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 46 unsigned int ctrl_num, int step) 47 { 48 unsigned int i, bus_width; 49 struct ccsr_ddr __iomem *ddr; 50 u32 temp_sdram_cfg; 51 u32 total_gb_size_per_controller; 52 int timeout; 53 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \ 54 defined(CONFIG_SYS_FSL_ERRATUM_A009801) 55 u32 temp32; 56 #endif 57 58 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 59 u32 mr6; 60 u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */ 61 u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ 62 u32 *vref_seq = vref_seq1; 63 #endif 64 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \ 65 defined(CONFIG_SYS_FSL_ERRATUM_A010165) 66 ulong ddr_freq; 67 u32 tmp; 68 #endif 69 #ifdef CONFIG_FSL_DDR_BIST 70 u32 mtcr, err_detect, err_sbe; 71 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; 72 #endif 73 #ifdef CONFIG_FSL_DDR_BIST 74 char buffer[CONFIG_SYS_CBSIZE]; 75 #endif 76 77 switch (ctrl_num) { 78 case 0: 79 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 80 break; 81 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 82 case 1: 83 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 84 break; 85 #endif 86 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 87 case 2: 88 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 89 break; 90 #endif 91 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 92 case 3: 93 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 94 break; 95 #endif 96 default: 97 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 98 return; 99 } 100 101 if (step == 2) 102 goto step2; 103 104 if (regs->ddr_eor) 105 ddr_out32(&ddr->eor, regs->ddr_eor); 106 107 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 108 109 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 110 if (i == 0) { 111 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 112 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 113 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 114 115 } else if (i == 1) { 116 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 117 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 118 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 119 120 } else if (i == 2) { 121 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 122 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 123 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 124 125 } else if (i == 3) { 126 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 127 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 128 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 129 } 130 } 131 132 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 133 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 134 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 135 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 136 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 137 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 138 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); 139 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); 140 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); 141 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); 142 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 143 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); 144 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); 145 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); 146 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); 147 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); 148 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 149 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 150 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 151 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 152 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 153 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 154 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 155 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 156 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); 157 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); 158 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); 159 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); 160 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); 161 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); 162 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); 163 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); 164 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 165 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 166 ddr_out32(&ddr->sdram_interval, 167 regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); 168 #else 169 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 170 #endif 171 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 172 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 173 #ifndef CONFIG_SYS_FSL_DDR_EMU 174 /* 175 * Skip these two registers if running on emulator 176 * because emulator doesn't have skew between bytes. 177 */ 178 179 if (regs->ddr_wrlvl_cntl_2) 180 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 181 if (regs->ddr_wrlvl_cntl_3) 182 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 183 #endif 184 185 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 186 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 187 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 188 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); 189 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); 190 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); 191 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); 192 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 193 #ifdef CONFIG_DEEP_SLEEP 194 if (is_warm_boot()) { 195 ddr_out32(&ddr->sdram_cfg_2, 196 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 197 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 198 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 199 200 /* DRAM VRef will not be trained */ 201 ddr_out32(&ddr->ddr_cdr2, 202 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 203 } else 204 #endif 205 { 206 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 207 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 208 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 209 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 210 } 211 212 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803 213 /* part 1 of 2 */ 214 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 215 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */ 216 ddr_out32(&ddr->ddr_sdram_rcw_2, 217 regs->ddr_sdram_rcw_2 & ~0x0f000000); 218 } 219 ddr_out32(&ddr->err_disable, regs->err_disable | 220 DDR_ERR_DISABLE_APED); 221 } 222 #else 223 ddr_out32(&ddr->err_disable, regs->err_disable); 224 #endif 225 ddr_out32(&ddr->err_int_en, regs->err_int_en); 226 for (i = 0; i < 64; i++) { 227 if (regs->debug[i]) { 228 debug("Write to debug_%d as %08x\n", 229 i+1, regs->debug[i]); 230 ddr_out32(&ddr->debug[i], regs->debug[i]); 231 } 232 } 233 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378 234 /* Erratum applies when accumulated ECC is used, or DBI is enabled */ 235 #define IS_ACC_ECC_EN(v) ((v) & 0x4) 236 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) 237 if (has_erratum_a008378()) { 238 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || 239 IS_DBI(regs->ddr_sdram_cfg_3)) 240 ddr_setbits32(&ddr->debug[28], 0x9 << 20); 241 } 242 #endif 243 244 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 245 /* Part 1 of 2 */ 246 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 247 /* Disable DRAM VRef training */ 248 ddr_out32(&ddr->ddr_cdr2, 249 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 250 /* disable transmit bit deskew */ 251 temp32 = ddr_in32(&ddr->debug[28]); 252 temp32 |= DDR_TX_BD_DIS; 253 ddr_out32(&ddr->debug[28], temp32); 254 ddr_out32(&ddr->debug[25], 0x9000); 255 } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) { 256 /* Output enable forced off */ 257 ddr_out32(&ddr->debug[37], 1 << 31); 258 /* Enable Vref training */ 259 ddr_out32(&ddr->ddr_cdr2, 260 regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN); 261 } else { 262 debug("Erratum A008511 doesn't apply.\n"); 263 } 264 #endif 265 266 #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \ 267 defined(CONFIG_SYS_FSL_ERRATUM_A008511) 268 /* Disable D_INIT */ 269 ddr_out32(&ddr->sdram_cfg_2, 270 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 271 #endif 272 273 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801 274 temp32 = ddr_in32(&ddr->debug[25]); 275 temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; 276 temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; 277 ddr_out32(&ddr->debug[25], temp32); 278 #endif 279 280 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 281 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; 282 tmp = ddr_in32(&ddr->debug[28]); 283 if (ddr_freq <= 1333) 284 ddr_out32(&ddr->debug[28], tmp | 0x0080006a); 285 else if (ddr_freq <= 1600) 286 ddr_out32(&ddr->debug[28], tmp | 0x0070006f); 287 else if (ddr_freq <= 1867) 288 ddr_out32(&ddr->debug[28], tmp | 0x00700076); 289 else if (ddr_freq <= 2133) 290 ddr_out32(&ddr->debug[28], tmp | 0x0060007b); 291 #endif 292 293 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165 294 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; 295 if ((ddr_freq > 1900) && (ddr_freq < 2300)) { 296 tmp = ddr_in32(&ddr->debug[28]); 297 ddr_out32(&ddr->debug[28], tmp | 0x000a0000); 298 } 299 #endif 300 /* 301 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 302 * deasserted. Clocks start when any chip select is enabled and clock 303 * control register is set. Because all DDR components are connected to 304 * one reset signal, this needs to be done in two steps. Step 1 is to 305 * get the clocks started. Step 2 resumes after reset signal is 306 * deasserted. 307 */ 308 if (step == 1) { 309 udelay(200); 310 return; 311 } 312 313 step2: 314 /* Set, but do not enable the memory */ 315 temp_sdram_cfg = regs->ddr_sdram_cfg; 316 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 317 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); 318 319 /* 320 * 500 painful micro-seconds must elapse between 321 * the DDR clock setup and the DDR config enable. 322 * DDR2 need 200 us, and DDR3 need 500 us from spec, 323 * we choose the max, that is 500 us for all of case. 324 */ 325 udelay(500); 326 mb(); 327 isb(); 328 329 #ifdef CONFIG_DEEP_SLEEP 330 if (is_warm_boot()) { 331 /* enter self-refresh */ 332 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 333 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 334 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 335 /* do board specific memory setup */ 336 board_mem_sleep_setup(); 337 338 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 339 } else 340 #endif 341 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 342 /* Let the controller go */ 343 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 344 mb(); 345 isb(); 346 347 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \ 348 defined(CONFIG_SYS_FSL_ERRATUM_A009803) 349 /* Part 2 of 2 */ 350 timeout = 40; 351 /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */ 352 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 353 (timeout > 0)) { 354 udelay(1000); 355 timeout--; 356 } 357 if (timeout <= 0) { 358 printf("Controler %d timeout, debug_2 = %x\n", 359 ctrl_num, ddr_in32(&ddr->debug[1])); 360 } 361 362 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 363 /* This erraum only applies to verion 5.2.0 */ 364 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 365 /* The vref setting sequence is different for range 2 */ 366 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) 367 vref_seq = vref_seq2; 368 369 /* Set VREF */ 370 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 371 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 372 continue; 373 374 mr6 = (regs->ddr_sdram_mode_10 >> 16) | 375 MD_CNTL_MD_EN | 376 MD_CNTL_CS_SEL(i) | 377 MD_CNTL_MD_SEL(6) | 378 0x00200000; 379 temp32 = mr6 | vref_seq[0]; 380 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 381 temp32, MD_CNTL_MD_EN); 382 udelay(1); 383 debug("MR6 = 0x%08x\n", temp32); 384 temp32 = mr6 | vref_seq[1]; 385 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 386 temp32, MD_CNTL_MD_EN); 387 udelay(1); 388 debug("MR6 = 0x%08x\n", temp32); 389 temp32 = mr6 | vref_seq[2]; 390 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 391 temp32, MD_CNTL_MD_EN); 392 udelay(1); 393 debug("MR6 = 0x%08x\n", temp32); 394 } 395 ddr_out32(&ddr->sdram_md_cntl, 0); 396 temp32 = ddr_in32(&ddr->debug[28]); 397 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */ 398 ddr_out32(&ddr->debug[28], temp32); 399 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ 400 /* wait for idle */ 401 timeout = 40; 402 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 403 (timeout > 0)) { 404 udelay(1000); 405 timeout--; 406 } 407 if (timeout <= 0) { 408 printf("Controler %d timeout, debug_2 = %x\n", 409 ctrl_num, ddr_in32(&ddr->debug[1])); 410 } 411 } 412 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 413 414 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803 415 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 416 /* if it's RDIMM */ 417 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { 418 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 419 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 420 continue; 421 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 422 MD_CNTL_MD_EN | 423 MD_CNTL_CS_SEL(i) | 424 0x070000ed, 425 MD_CNTL_MD_EN); 426 udelay(1); 427 } 428 } 429 430 ddr_out32(&ddr->err_disable, 431 regs->err_disable & ~DDR_ERR_DISABLE_APED); 432 } 433 #endif 434 /* Restore D_INIT */ 435 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 436 #endif 437 438 total_gb_size_per_controller = 0; 439 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 440 if (!(regs->cs[i].config & 0x80000000)) 441 continue; 442 total_gb_size_per_controller += 1 << ( 443 ((regs->cs[i].config >> 14) & 0x3) + 2 + 444 ((regs->cs[i].config >> 8) & 0x7) + 12 + 445 ((regs->cs[i].config >> 4) & 0x3) + 0 + 446 ((regs->cs[i].config >> 0) & 0x7) + 8 + 447 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 448 26); /* minus 26 (count of 64M) */ 449 } 450 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 451 total_gb_size_per_controller *= 3; 452 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 453 total_gb_size_per_controller <<= 1; 454 /* 455 * total memory / bus width = transactions needed 456 * transactions needed / data rate = seconds 457 * to add plenty of buffer, double the time 458 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 459 * Let's wait for 800ms 460 */ 461 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 462 >> SDRAM_CFG_DBW_SHIFT); 463 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 464 (get_ddr_freq(ctrl_num) >> 20)) << 2; 465 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 466 debug("total %d GB\n", total_gb_size_per_controller); 467 debug("Need to wait up to %d * 10ms\n", timeout); 468 469 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 470 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 471 (timeout >= 0)) { 472 udelay(10000); /* throttle polling rate */ 473 timeout--; 474 } 475 476 if (timeout <= 0) 477 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 478 479 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 480 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 481 #endif 482 483 #ifdef CONFIG_DEEP_SLEEP 484 if (is_warm_boot()) { 485 /* exit self-refresh */ 486 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 487 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 488 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 489 } 490 #endif 491 492 #ifdef CONFIG_FSL_DDR_BIST 493 #define BIST_PATTERN1 0xFFFFFFFF 494 #define BIST_PATTERN2 0x0 495 #define BIST_CR 0x80010000 496 #define BIST_CR_EN 0x80000000 497 #define BIST_CR_STAT 0x00000001 498 #define CTLR_INTLV_MASK 0x20000000 499 /* Perform build-in test on memory. Three-way interleaving is not yet 500 * supported by this code. */ 501 if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) { 502 puts("Running BIST test. This will take a while..."); 503 cs0_config = ddr_in32(&ddr->cs0_config); 504 cs0_bnds = ddr_in32(&ddr->cs0_bnds); 505 cs1_bnds = ddr_in32(&ddr->cs1_bnds); 506 cs2_bnds = ddr_in32(&ddr->cs2_bnds); 507 cs3_bnds = ddr_in32(&ddr->cs3_bnds); 508 if (cs0_config & CTLR_INTLV_MASK) { 509 /* set bnds to non-interleaving */ 510 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); 511 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); 512 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); 513 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); 514 } 515 ddr_out32(&ddr->mtp1, BIST_PATTERN1); 516 ddr_out32(&ddr->mtp2, BIST_PATTERN1); 517 ddr_out32(&ddr->mtp3, BIST_PATTERN2); 518 ddr_out32(&ddr->mtp4, BIST_PATTERN2); 519 ddr_out32(&ddr->mtp5, BIST_PATTERN1); 520 ddr_out32(&ddr->mtp6, BIST_PATTERN1); 521 ddr_out32(&ddr->mtp7, BIST_PATTERN2); 522 ddr_out32(&ddr->mtp8, BIST_PATTERN2); 523 ddr_out32(&ddr->mtp9, BIST_PATTERN1); 524 ddr_out32(&ddr->mtp10, BIST_PATTERN2); 525 mtcr = BIST_CR; 526 ddr_out32(&ddr->mtcr, mtcr); 527 timeout = 100; 528 while (timeout > 0 && (mtcr & BIST_CR_EN)) { 529 mdelay(1000); 530 timeout--; 531 mtcr = ddr_in32(&ddr->mtcr); 532 } 533 if (timeout <= 0) 534 puts("Timeout\n"); 535 else 536 puts("Done\n"); 537 err_detect = ddr_in32(&ddr->err_detect); 538 err_sbe = ddr_in32(&ddr->err_sbe); 539 if (mtcr & BIST_CR_STAT) { 540 printf("BIST test failed on controller %d.\n", 541 ctrl_num); 542 } 543 if (err_detect || (err_sbe & 0xffff)) { 544 printf("ECC error detected on controller %d.\n", 545 ctrl_num); 546 } 547 548 if (cs0_config & CTLR_INTLV_MASK) { 549 /* restore bnds registers */ 550 ddr_out32(&ddr->cs0_bnds, cs0_bnds); 551 ddr_out32(&ddr->cs1_bnds, cs1_bnds); 552 ddr_out32(&ddr->cs2_bnds, cs2_bnds); 553 ddr_out32(&ddr->cs3_bnds, cs3_bnds); 554 } 555 } 556 #endif 557 } 558