1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 #include <fsl_immap.h> 12 #include <fsl_ddr.h> 13 #include <fsl_errata.h> 14 15 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \ 16 defined(CONFIG_SYS_FSL_ERRATUM_A009803) 17 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 18 { 19 int timeout = 1000; 20 21 ddr_out32(ptr, value); 22 23 while (ddr_in32(ptr) & bits) { 24 udelay(100); 25 timeout--; 26 } 27 if (timeout <= 0) 28 puts("Error: wait for clear timeout.\n"); 29 } 30 #endif 31 32 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 33 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 34 #endif 35 36 /* 37 * regs has the to-be-set values for DDR controller registers 38 * ctrl_num is the DDR controller number 39 * step: 0 goes through the initialization in one pass 40 * 1 sets registers and returns before enabling controller 41 * 2 resumes from step 1 and continues to initialize 42 * Dividing the initialization to two steps to deassert DDR reset signal 43 * to comply with JEDEC specs for RDIMMs. 44 */ 45 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 46 unsigned int ctrl_num, int step) 47 { 48 unsigned int i, bus_width; 49 struct ccsr_ddr __iomem *ddr; 50 u32 temp_sdram_cfg; 51 u32 total_gb_size_per_controller; 52 int timeout; 53 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 54 u32 temp32, mr6; 55 u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */ 56 u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ 57 u32 *vref_seq = vref_seq1; 58 #endif 59 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \ 60 defined(CONFIG_SYS_FSL_ERRATUM_A010165) 61 ulong ddr_freq; 62 u32 tmp; 63 #endif 64 #ifdef CONFIG_FSL_DDR_BIST 65 u32 mtcr, err_detect, err_sbe; 66 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; 67 #endif 68 #ifdef CONFIG_FSL_DDR_BIST 69 char buffer[CONFIG_SYS_CBSIZE]; 70 #endif 71 72 switch (ctrl_num) { 73 case 0: 74 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 75 break; 76 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 77 case 1: 78 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 79 break; 80 #endif 81 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 82 case 2: 83 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 84 break; 85 #endif 86 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 87 case 3: 88 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 89 break; 90 #endif 91 default: 92 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 93 return; 94 } 95 96 if (step == 2) 97 goto step2; 98 99 if (regs->ddr_eor) 100 ddr_out32(&ddr->eor, regs->ddr_eor); 101 102 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 103 104 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 105 if (i == 0) { 106 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 107 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 108 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 109 110 } else if (i == 1) { 111 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 112 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 113 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 114 115 } else if (i == 2) { 116 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 117 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 118 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 119 120 } else if (i == 3) { 121 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 122 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 123 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 124 } 125 } 126 127 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 128 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 129 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 130 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 131 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 132 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 133 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); 134 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); 135 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); 136 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); 137 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 138 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); 139 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); 140 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); 141 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); 142 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); 143 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 144 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 145 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 146 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 147 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 148 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 149 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 150 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 151 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); 152 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); 153 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); 154 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); 155 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); 156 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); 157 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); 158 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); 159 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 160 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 161 ddr_out32(&ddr->sdram_interval, 162 regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); 163 #else 164 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 165 #endif 166 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 167 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 168 #ifndef CONFIG_SYS_FSL_DDR_EMU 169 /* 170 * Skip these two registers if running on emulator 171 * because emulator doesn't have skew between bytes. 172 */ 173 174 if (regs->ddr_wrlvl_cntl_2) 175 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 176 if (regs->ddr_wrlvl_cntl_3) 177 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 178 #endif 179 180 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 181 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 182 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 183 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); 184 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); 185 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); 186 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); 187 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 188 #ifdef CONFIG_DEEP_SLEEP 189 if (is_warm_boot()) { 190 ddr_out32(&ddr->sdram_cfg_2, 191 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 192 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 193 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 194 195 /* DRAM VRef will not be trained */ 196 ddr_out32(&ddr->ddr_cdr2, 197 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 198 } else 199 #endif 200 { 201 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 202 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 203 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 204 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 205 } 206 207 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803 208 /* part 1 of 2 */ 209 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */ 210 ddr_out32(&ddr->ddr_sdram_rcw_2, 211 regs->ddr_sdram_rcw_2 & ~0x0f000000); 212 } 213 214 ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED); 215 #else 216 ddr_out32(&ddr->err_disable, regs->err_disable); 217 #endif 218 ddr_out32(&ddr->err_int_en, regs->err_int_en); 219 for (i = 0; i < 32; i++) { 220 if (regs->debug[i]) { 221 debug("Write to debug_%d as %08x\n", 222 i+1, regs->debug[i]); 223 ddr_out32(&ddr->debug[i], regs->debug[i]); 224 } 225 } 226 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378 227 /* Erratum applies when accumulated ECC is used, or DBI is enabled */ 228 #define IS_ACC_ECC_EN(v) ((v) & 0x4) 229 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) 230 if (has_erratum_a008378()) { 231 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || 232 IS_DBI(regs->ddr_sdram_cfg_3)) 233 ddr_setbits32(&ddr->debug[28], 0x9 << 20); 234 } 235 #endif 236 237 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 238 /* Part 1 of 2 */ 239 /* This erraum only applies to verion 5.2.0 */ 240 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 241 /* Disable DRAM VRef training */ 242 ddr_out32(&ddr->ddr_cdr2, 243 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 244 /* disable transmit bit deskew */ 245 temp32 = ddr_in32(&ddr->debug[28]); 246 temp32 |= DDR_TX_BD_DIS; 247 ddr_out32(&ddr->debug[28], temp32); 248 /* Disable D_INIT */ 249 ddr_out32(&ddr->sdram_cfg_2, 250 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 251 ddr_out32(&ddr->debug[25], 0x9000); 252 } 253 #endif 254 255 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801 256 temp32 = ddr_in32(&ddr->debug[25]); 257 temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; 258 temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; 259 ddr_out32(&ddr->debug[25], temp32); 260 #endif 261 262 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 263 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; 264 tmp = ddr_in32(&ddr->debug[28]); 265 if (ddr_freq <= 1333) 266 ddr_out32(&ddr->debug[28], tmp | 0x0080006a); 267 else if (ddr_freq <= 1600) 268 ddr_out32(&ddr->debug[28], tmp | 0x0070006f); 269 else if (ddr_freq <= 1867) 270 ddr_out32(&ddr->debug[28], tmp | 0x00700076); 271 else if (ddr_freq <= 2133) 272 ddr_out32(&ddr->debug[28], tmp | 0x0060007b); 273 #endif 274 275 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165 276 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; 277 if ((ddr_freq > 1900) && (ddr_freq < 2300)) { 278 tmp = ddr_in32(&ddr->debug[28]); 279 ddr_out32(&ddr->debug[28], tmp | 0x000a0000); 280 } 281 #endif 282 /* 283 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 284 * deasserted. Clocks start when any chip select is enabled and clock 285 * control register is set. Because all DDR components are connected to 286 * one reset signal, this needs to be done in two steps. Step 1 is to 287 * get the clocks started. Step 2 resumes after reset signal is 288 * deasserted. 289 */ 290 if (step == 1) { 291 udelay(200); 292 return; 293 } 294 295 step2: 296 /* Set, but do not enable the memory */ 297 temp_sdram_cfg = regs->ddr_sdram_cfg; 298 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 299 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); 300 301 /* 302 * 500 painful micro-seconds must elapse between 303 * the DDR clock setup and the DDR config enable. 304 * DDR2 need 200 us, and DDR3 need 500 us from spec, 305 * we choose the max, that is 500 us for all of case. 306 */ 307 udelay(500); 308 mb(); 309 isb(); 310 311 #ifdef CONFIG_DEEP_SLEEP 312 if (is_warm_boot()) { 313 /* enter self-refresh */ 314 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 315 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 316 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 317 /* do board specific memory setup */ 318 board_mem_sleep_setup(); 319 320 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 321 } else 322 #endif 323 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 324 /* Let the controller go */ 325 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 326 mb(); 327 isb(); 328 329 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \ 330 defined(CONFIG_SYS_FSL_ERRATUM_A009803) 331 /* Part 2 of 2 */ 332 /* This erraum only applies to verion 5.2.0 */ 333 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 334 /* Wait for idle */ 335 timeout = 40; 336 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 337 (timeout > 0)) { 338 udelay(1000); 339 timeout--; 340 } 341 if (timeout <= 0) { 342 printf("Controler %d timeout, debug_2 = %x\n", 343 ctrl_num, ddr_in32(&ddr->debug[1])); 344 } 345 346 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 347 /* The vref setting sequence is different for range 2 */ 348 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) 349 vref_seq = vref_seq2; 350 351 /* Set VREF */ 352 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 353 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 354 continue; 355 356 mr6 = (regs->ddr_sdram_mode_10 >> 16) | 357 MD_CNTL_MD_EN | 358 MD_CNTL_CS_SEL(i) | 359 MD_CNTL_MD_SEL(6) | 360 0x00200000; 361 temp32 = mr6 | vref_seq[0]; 362 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 363 temp32, MD_CNTL_MD_EN); 364 udelay(1); 365 debug("MR6 = 0x%08x\n", temp32); 366 temp32 = mr6 | vref_seq[1]; 367 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 368 temp32, MD_CNTL_MD_EN); 369 udelay(1); 370 debug("MR6 = 0x%08x\n", temp32); 371 temp32 = mr6 | vref_seq[2]; 372 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 373 temp32, MD_CNTL_MD_EN); 374 udelay(1); 375 debug("MR6 = 0x%08x\n", temp32); 376 } 377 ddr_out32(&ddr->sdram_md_cntl, 0); 378 temp32 = ddr_in32(&ddr->debug[28]); 379 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */ 380 ddr_out32(&ddr->debug[28], temp32); 381 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ 382 /* wait for idle */ 383 timeout = 40; 384 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 385 (timeout > 0)) { 386 udelay(1000); 387 timeout--; 388 } 389 if (timeout <= 0) { 390 printf("Controler %d timeout, debug_2 = %x\n", 391 ctrl_num, ddr_in32(&ddr->debug[1])); 392 } 393 /* Restore D_INIT */ 394 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 395 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 396 397 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803 398 /* if it's RDIMM */ 399 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { 400 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 401 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 402 continue; 403 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 404 MD_CNTL_MD_EN | 405 MD_CNTL_CS_SEL(i) | 406 0x070000ed, 407 MD_CNTL_MD_EN); 408 udelay(1); 409 } 410 } 411 412 ddr_out32(&ddr->err_disable, 413 regs->err_disable & ~DDR_ERR_DISABLE_APED); 414 #endif 415 } 416 #endif 417 418 total_gb_size_per_controller = 0; 419 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 420 if (!(regs->cs[i].config & 0x80000000)) 421 continue; 422 total_gb_size_per_controller += 1 << ( 423 ((regs->cs[i].config >> 14) & 0x3) + 2 + 424 ((regs->cs[i].config >> 8) & 0x7) + 12 + 425 ((regs->cs[i].config >> 4) & 0x3) + 0 + 426 ((regs->cs[i].config >> 0) & 0x7) + 8 + 427 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 428 26); /* minus 26 (count of 64M) */ 429 } 430 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 431 total_gb_size_per_controller *= 3; 432 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 433 total_gb_size_per_controller <<= 1; 434 /* 435 * total memory / bus width = transactions needed 436 * transactions needed / data rate = seconds 437 * to add plenty of buffer, double the time 438 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 439 * Let's wait for 800ms 440 */ 441 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 442 >> SDRAM_CFG_DBW_SHIFT); 443 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 444 (get_ddr_freq(ctrl_num) >> 20)) << 2; 445 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 446 debug("total %d GB\n", total_gb_size_per_controller); 447 debug("Need to wait up to %d * 10ms\n", timeout); 448 449 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 450 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 451 (timeout >= 0)) { 452 udelay(10000); /* throttle polling rate */ 453 timeout--; 454 } 455 456 if (timeout <= 0) 457 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 458 459 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 460 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 461 #endif 462 463 #ifdef CONFIG_DEEP_SLEEP 464 if (is_warm_boot()) { 465 /* exit self-refresh */ 466 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 467 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 468 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 469 } 470 #endif 471 472 #ifdef CONFIG_FSL_DDR_BIST 473 #define BIST_PATTERN1 0xFFFFFFFF 474 #define BIST_PATTERN2 0x0 475 #define BIST_CR 0x80010000 476 #define BIST_CR_EN 0x80000000 477 #define BIST_CR_STAT 0x00000001 478 #define CTLR_INTLV_MASK 0x20000000 479 /* Perform build-in test on memory. Three-way interleaving is not yet 480 * supported by this code. */ 481 if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) { 482 puts("Running BIST test. This will take a while..."); 483 cs0_config = ddr_in32(&ddr->cs0_config); 484 cs0_bnds = ddr_in32(&ddr->cs0_bnds); 485 cs1_bnds = ddr_in32(&ddr->cs1_bnds); 486 cs2_bnds = ddr_in32(&ddr->cs2_bnds); 487 cs3_bnds = ddr_in32(&ddr->cs3_bnds); 488 if (cs0_config & CTLR_INTLV_MASK) { 489 /* set bnds to non-interleaving */ 490 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); 491 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); 492 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); 493 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); 494 } 495 ddr_out32(&ddr->mtp1, BIST_PATTERN1); 496 ddr_out32(&ddr->mtp2, BIST_PATTERN1); 497 ddr_out32(&ddr->mtp3, BIST_PATTERN2); 498 ddr_out32(&ddr->mtp4, BIST_PATTERN2); 499 ddr_out32(&ddr->mtp5, BIST_PATTERN1); 500 ddr_out32(&ddr->mtp6, BIST_PATTERN1); 501 ddr_out32(&ddr->mtp7, BIST_PATTERN2); 502 ddr_out32(&ddr->mtp8, BIST_PATTERN2); 503 ddr_out32(&ddr->mtp9, BIST_PATTERN1); 504 ddr_out32(&ddr->mtp10, BIST_PATTERN2); 505 mtcr = BIST_CR; 506 ddr_out32(&ddr->mtcr, mtcr); 507 timeout = 100; 508 while (timeout > 0 && (mtcr & BIST_CR_EN)) { 509 mdelay(1000); 510 timeout--; 511 mtcr = ddr_in32(&ddr->mtcr); 512 } 513 if (timeout <= 0) 514 puts("Timeout\n"); 515 else 516 puts("Done\n"); 517 err_detect = ddr_in32(&ddr->err_detect); 518 err_sbe = ddr_in32(&ddr->err_sbe); 519 if (mtcr & BIST_CR_STAT) { 520 printf("BIST test failed on controller %d.\n", 521 ctrl_num); 522 } 523 if (err_detect || (err_sbe & 0xffff)) { 524 printf("ECC error detected on controller %d.\n", 525 ctrl_num); 526 } 527 528 if (cs0_config & CTLR_INTLV_MASK) { 529 /* restore bnds registers */ 530 ddr_out32(&ddr->cs0_bnds, cs0_bnds); 531 ddr_out32(&ddr->cs1_bnds, cs1_bnds); 532 ddr_out32(&ddr->cs2_bnds, cs2_bnds); 533 ddr_out32(&ddr->cs3_bnds, cs3_bnds); 534 } 535 } 536 #endif 537 } 538