1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 #include <fsl_immap.h> 12 #include <fsl_ddr.h> 13 #include <fsl_errata.h> 14 15 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \ 16 defined(CONFIG_SYS_FSL_ERRATUM_A009803) 17 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 18 { 19 int timeout = 1000; 20 21 ddr_out32(ptr, value); 22 23 while (ddr_in32(ptr) & bits) { 24 udelay(100); 25 timeout--; 26 } 27 if (timeout <= 0) 28 puts("Error: wait for clear timeout.\n"); 29 } 30 #endif 31 32 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 33 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 34 #endif 35 36 /* 37 * regs has the to-be-set values for DDR controller registers 38 * ctrl_num is the DDR controller number 39 * step: 0 goes through the initialization in one pass 40 * 1 sets registers and returns before enabling controller 41 * 2 resumes from step 1 and continues to initialize 42 * Dividing the initialization to two steps to deassert DDR reset signal 43 * to comply with JEDEC specs for RDIMMs. 44 */ 45 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 46 unsigned int ctrl_num, int step) 47 { 48 unsigned int i, bus_width; 49 struct ccsr_ddr __iomem *ddr; 50 u32 temp_sdram_cfg; 51 u32 total_gb_size_per_controller; 52 int timeout; 53 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 54 u32 temp32, mr6; 55 u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */ 56 u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ 57 u32 *vref_seq = vref_seq1; 58 #endif 59 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 60 ulong ddr_freq; 61 u32 tmp; 62 #endif 63 #ifdef CONFIG_FSL_DDR_BIST 64 u32 mtcr, err_detect, err_sbe; 65 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; 66 #endif 67 #ifdef CONFIG_FSL_DDR_BIST 68 char buffer[CONFIG_SYS_CBSIZE]; 69 #endif 70 71 switch (ctrl_num) { 72 case 0: 73 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 74 break; 75 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 76 case 1: 77 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 78 break; 79 #endif 80 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 81 case 2: 82 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 83 break; 84 #endif 85 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 86 case 3: 87 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 88 break; 89 #endif 90 default: 91 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 92 return; 93 } 94 95 if (step == 2) 96 goto step2; 97 98 if (regs->ddr_eor) 99 ddr_out32(&ddr->eor, regs->ddr_eor); 100 101 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 102 103 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 104 if (i == 0) { 105 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 106 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 107 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 108 109 } else if (i == 1) { 110 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 111 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 112 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 113 114 } else if (i == 2) { 115 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 116 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 117 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 118 119 } else if (i == 3) { 120 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 121 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 122 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 123 } 124 } 125 126 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 127 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 128 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 129 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 130 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 131 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 132 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); 133 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); 134 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); 135 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); 136 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 137 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); 138 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); 139 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); 140 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); 141 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); 142 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 143 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 144 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 145 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 146 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 147 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 148 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 149 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 150 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); 151 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); 152 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); 153 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); 154 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); 155 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); 156 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); 157 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); 158 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 159 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 160 ddr_out32(&ddr->sdram_interval, 161 regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); 162 #else 163 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 164 #endif 165 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 166 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 167 #ifndef CONFIG_SYS_FSL_DDR_EMU 168 /* 169 * Skip these two registers if running on emulator 170 * because emulator doesn't have skew between bytes. 171 */ 172 173 if (regs->ddr_wrlvl_cntl_2) 174 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 175 if (regs->ddr_wrlvl_cntl_3) 176 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 177 #endif 178 179 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 180 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 181 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 182 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); 183 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); 184 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); 185 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); 186 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 187 #ifdef CONFIG_DEEP_SLEEP 188 if (is_warm_boot()) { 189 ddr_out32(&ddr->sdram_cfg_2, 190 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 191 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 192 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 193 194 /* DRAM VRef will not be trained */ 195 ddr_out32(&ddr->ddr_cdr2, 196 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 197 } else 198 #endif 199 { 200 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 201 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 202 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 203 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 204 } 205 206 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803 207 /* part 1 of 2 */ 208 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */ 209 ddr_out32(&ddr->ddr_sdram_rcw_2, 210 regs->ddr_sdram_rcw_2 & ~0x0f000000); 211 } 212 213 ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED); 214 #else 215 ddr_out32(&ddr->err_disable, regs->err_disable); 216 #endif 217 ddr_out32(&ddr->err_int_en, regs->err_int_en); 218 for (i = 0; i < 32; i++) { 219 if (regs->debug[i]) { 220 debug("Write to debug_%d as %08x\n", 221 i+1, regs->debug[i]); 222 ddr_out32(&ddr->debug[i], regs->debug[i]); 223 } 224 } 225 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378 226 /* Erratum applies when accumulated ECC is used, or DBI is enabled */ 227 #define IS_ACC_ECC_EN(v) ((v) & 0x4) 228 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) 229 if (has_erratum_a008378()) { 230 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || 231 IS_DBI(regs->ddr_sdram_cfg_3)) 232 ddr_setbits32(&ddr->debug[28], 0x9 << 20); 233 } 234 #endif 235 236 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 237 /* Part 1 of 2 */ 238 /* This erraum only applies to verion 5.2.0 */ 239 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 240 /* Disable DRAM VRef training */ 241 ddr_out32(&ddr->ddr_cdr2, 242 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 243 /* disable transmit bit deskew */ 244 temp32 = ddr_in32(&ddr->debug[28]); 245 temp32 |= DDR_TX_BD_DIS; 246 ddr_out32(&ddr->debug[28], temp32); 247 /* Disable D_INIT */ 248 ddr_out32(&ddr->sdram_cfg_2, 249 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 250 ddr_out32(&ddr->debug[25], 0x9000); 251 } 252 #endif 253 254 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801 255 temp32 = ddr_in32(&ddr->debug[25]); 256 temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; 257 temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; 258 ddr_out32(&ddr->debug[25], temp32); 259 #endif 260 261 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 262 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; 263 tmp = ddr_in32(&ddr->debug[28]); 264 if (ddr_freq <= 1333) 265 ddr_out32(&ddr->debug[28], tmp | 0x0080006a); 266 else if (ddr_freq <= 1600) 267 ddr_out32(&ddr->debug[28], tmp | 0x0070006f); 268 else if (ddr_freq <= 1867) 269 ddr_out32(&ddr->debug[28], tmp | 0x00700076); 270 else if (ddr_freq <= 2133) 271 ddr_out32(&ddr->debug[28], tmp | 0x0060007b); 272 #endif 273 274 /* 275 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 276 * deasserted. Clocks start when any chip select is enabled and clock 277 * control register is set. Because all DDR components are connected to 278 * one reset signal, this needs to be done in two steps. Step 1 is to 279 * get the clocks started. Step 2 resumes after reset signal is 280 * deasserted. 281 */ 282 if (step == 1) { 283 udelay(200); 284 return; 285 } 286 287 step2: 288 /* Set, but do not enable the memory */ 289 temp_sdram_cfg = regs->ddr_sdram_cfg; 290 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 291 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); 292 293 /* 294 * 500 painful micro-seconds must elapse between 295 * the DDR clock setup and the DDR config enable. 296 * DDR2 need 200 us, and DDR3 need 500 us from spec, 297 * we choose the max, that is 500 us for all of case. 298 */ 299 udelay(500); 300 mb(); 301 isb(); 302 303 #ifdef CONFIG_DEEP_SLEEP 304 if (is_warm_boot()) { 305 /* enter self-refresh */ 306 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 307 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 308 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 309 /* do board specific memory setup */ 310 board_mem_sleep_setup(); 311 312 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 313 } else 314 #endif 315 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 316 /* Let the controller go */ 317 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 318 mb(); 319 isb(); 320 321 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \ 322 defined(CONFIG_SYS_FSL_ERRATUM_A009803) 323 /* Part 2 of 2 */ 324 /* This erraum only applies to verion 5.2.0 */ 325 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 326 /* Wait for idle */ 327 timeout = 40; 328 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 329 (timeout > 0)) { 330 udelay(1000); 331 timeout--; 332 } 333 if (timeout <= 0) { 334 printf("Controler %d timeout, debug_2 = %x\n", 335 ctrl_num, ddr_in32(&ddr->debug[1])); 336 } 337 338 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 339 /* The vref setting sequence is different for range 2 */ 340 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) 341 vref_seq = vref_seq2; 342 343 /* Set VREF */ 344 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 345 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 346 continue; 347 348 mr6 = (regs->ddr_sdram_mode_10 >> 16) | 349 MD_CNTL_MD_EN | 350 MD_CNTL_CS_SEL(i) | 351 MD_CNTL_MD_SEL(6) | 352 0x00200000; 353 temp32 = mr6 | vref_seq[0]; 354 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 355 temp32, MD_CNTL_MD_EN); 356 udelay(1); 357 debug("MR6 = 0x%08x\n", temp32); 358 temp32 = mr6 | vref_seq[1]; 359 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 360 temp32, MD_CNTL_MD_EN); 361 udelay(1); 362 debug("MR6 = 0x%08x\n", temp32); 363 temp32 = mr6 | vref_seq[2]; 364 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 365 temp32, MD_CNTL_MD_EN); 366 udelay(1); 367 debug("MR6 = 0x%08x\n", temp32); 368 } 369 ddr_out32(&ddr->sdram_md_cntl, 0); 370 temp32 = ddr_in32(&ddr->debug[28]); 371 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */ 372 ddr_out32(&ddr->debug[28], temp32); 373 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ 374 /* wait for idle */ 375 timeout = 40; 376 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 377 (timeout > 0)) { 378 udelay(1000); 379 timeout--; 380 } 381 if (timeout <= 0) { 382 printf("Controler %d timeout, debug_2 = %x\n", 383 ctrl_num, ddr_in32(&ddr->debug[1])); 384 } 385 /* Restore D_INIT */ 386 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 387 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 388 389 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803 390 /* if it's RDIMM */ 391 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { 392 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 393 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 394 continue; 395 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 396 MD_CNTL_MD_EN | 397 MD_CNTL_CS_SEL(i) | 398 0x070000ed, 399 MD_CNTL_MD_EN); 400 udelay(1); 401 } 402 } 403 404 ddr_out32(&ddr->err_disable, 405 regs->err_disable & ~DDR_ERR_DISABLE_APED); 406 #endif 407 } 408 #endif 409 410 total_gb_size_per_controller = 0; 411 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 412 if (!(regs->cs[i].config & 0x80000000)) 413 continue; 414 total_gb_size_per_controller += 1 << ( 415 ((regs->cs[i].config >> 14) & 0x3) + 2 + 416 ((regs->cs[i].config >> 8) & 0x7) + 12 + 417 ((regs->cs[i].config >> 4) & 0x3) + 0 + 418 ((regs->cs[i].config >> 0) & 0x7) + 8 + 419 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 420 26); /* minus 26 (count of 64M) */ 421 } 422 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 423 total_gb_size_per_controller *= 3; 424 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 425 total_gb_size_per_controller <<= 1; 426 /* 427 * total memory / bus width = transactions needed 428 * transactions needed / data rate = seconds 429 * to add plenty of buffer, double the time 430 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 431 * Let's wait for 800ms 432 */ 433 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 434 >> SDRAM_CFG_DBW_SHIFT); 435 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 436 (get_ddr_freq(ctrl_num) >> 20)) << 2; 437 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 438 debug("total %d GB\n", total_gb_size_per_controller); 439 debug("Need to wait up to %d * 10ms\n", timeout); 440 441 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 442 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 443 (timeout >= 0)) { 444 udelay(10000); /* throttle polling rate */ 445 timeout--; 446 } 447 448 if (timeout <= 0) 449 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 450 451 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 452 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 453 #endif 454 455 #ifdef CONFIG_DEEP_SLEEP 456 if (is_warm_boot()) { 457 /* exit self-refresh */ 458 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 459 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 460 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 461 } 462 #endif 463 464 #ifdef CONFIG_FSL_DDR_BIST 465 #define BIST_PATTERN1 0xFFFFFFFF 466 #define BIST_PATTERN2 0x0 467 #define BIST_CR 0x80010000 468 #define BIST_CR_EN 0x80000000 469 #define BIST_CR_STAT 0x00000001 470 #define CTLR_INTLV_MASK 0x20000000 471 /* Perform build-in test on memory. Three-way interleaving is not yet 472 * supported by this code. */ 473 if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) { 474 puts("Running BIST test. This will take a while..."); 475 cs0_config = ddr_in32(&ddr->cs0_config); 476 cs0_bnds = ddr_in32(&ddr->cs0_bnds); 477 cs1_bnds = ddr_in32(&ddr->cs1_bnds); 478 cs2_bnds = ddr_in32(&ddr->cs2_bnds); 479 cs3_bnds = ddr_in32(&ddr->cs3_bnds); 480 if (cs0_config & CTLR_INTLV_MASK) { 481 /* set bnds to non-interleaving */ 482 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); 483 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); 484 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); 485 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); 486 } 487 ddr_out32(&ddr->mtp1, BIST_PATTERN1); 488 ddr_out32(&ddr->mtp2, BIST_PATTERN1); 489 ddr_out32(&ddr->mtp3, BIST_PATTERN2); 490 ddr_out32(&ddr->mtp4, BIST_PATTERN2); 491 ddr_out32(&ddr->mtp5, BIST_PATTERN1); 492 ddr_out32(&ddr->mtp6, BIST_PATTERN1); 493 ddr_out32(&ddr->mtp7, BIST_PATTERN2); 494 ddr_out32(&ddr->mtp8, BIST_PATTERN2); 495 ddr_out32(&ddr->mtp9, BIST_PATTERN1); 496 ddr_out32(&ddr->mtp10, BIST_PATTERN2); 497 mtcr = BIST_CR; 498 ddr_out32(&ddr->mtcr, mtcr); 499 timeout = 100; 500 while (timeout > 0 && (mtcr & BIST_CR_EN)) { 501 mdelay(1000); 502 timeout--; 503 mtcr = ddr_in32(&ddr->mtcr); 504 } 505 if (timeout <= 0) 506 puts("Timeout\n"); 507 else 508 puts("Done\n"); 509 err_detect = ddr_in32(&ddr->err_detect); 510 err_sbe = ddr_in32(&ddr->err_sbe); 511 if (mtcr & BIST_CR_STAT) { 512 printf("BIST test failed on controller %d.\n", 513 ctrl_num); 514 } 515 if (err_detect || (err_sbe & 0xffff)) { 516 printf("ECC error detected on controller %d.\n", 517 ctrl_num); 518 } 519 520 if (cs0_config & CTLR_INTLV_MASK) { 521 /* restore bnds registers */ 522 ddr_out32(&ddr->cs0_bnds, cs0_bnds); 523 ddr_out32(&ddr->cs1_bnds, cs1_bnds); 524 ddr_out32(&ddr->cs2_bnds, cs2_bnds); 525 ddr_out32(&ddr->cs3_bnds, cs3_bnds); 526 } 527 } 528 #endif 529 } 530