1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 #include <fsl_immap.h> 12 #include <fsl_ddr.h> 13 14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 16 #endif 17 18 /* 19 * regs has the to-be-set values for DDR controller registers 20 * ctrl_num is the DDR controller number 21 * step: 0 goes through the initialization in one pass 22 * 1 sets registers and returns before enabling controller 23 * 2 resumes from step 1 and continues to initialize 24 * Dividing the initialization to two steps to deassert DDR reset signal 25 * to comply with JEDEC specs for RDIMMs. 26 */ 27 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 28 unsigned int ctrl_num, int step) 29 { 30 unsigned int i, bus_width; 31 struct ccsr_ddr __iomem *ddr; 32 u32 temp_sdram_cfg; 33 u32 total_gb_size_per_controller; 34 int timeout; 35 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 36 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 37 u32 *eddrtqcr1; 38 #endif 39 40 switch (ctrl_num) { 41 case 0: 42 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 43 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 44 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 45 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 46 #endif 47 break; 48 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 49 case 1: 50 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 51 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 52 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 53 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 54 #endif 55 break; 56 #endif 57 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 58 case 2: 59 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 60 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 61 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 62 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 63 #endif 64 break; 65 #endif 66 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 67 case 3: 68 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 69 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 70 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 71 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800; 72 #endif 73 break; 74 #endif 75 default: 76 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 77 return; 78 } 79 80 if (step == 2) 81 goto step2; 82 83 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 84 #ifdef CONFIG_LS2085A 85 /* A008336 only applies to general DDR controllers */ 86 if ((ctrl_num == 0) || (ctrl_num == 1)) 87 #endif 88 ddr_out32(eddrtqcr1, 0x63b30002); 89 #endif 90 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 91 #ifdef CONFIG_LS2085A 92 /* A008514 only applies to DP-DDR controler */ 93 if (ctrl_num == 2) 94 #endif 95 ddr_out32(eddrtqcr1, 0x63b20002); 96 #endif 97 if (regs->ddr_eor) 98 ddr_out32(&ddr->eor, regs->ddr_eor); 99 100 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 101 102 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 103 if (i == 0) { 104 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 105 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 106 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 107 108 } else if (i == 1) { 109 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 110 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 111 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 112 113 } else if (i == 2) { 114 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 115 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 116 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 117 118 } else if (i == 3) { 119 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 120 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 121 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 122 } 123 } 124 125 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 126 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 127 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 128 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 129 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 130 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 131 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); 132 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); 133 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); 134 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); 135 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 136 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); 137 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); 138 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); 139 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); 140 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); 141 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 142 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 143 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 144 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 145 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 146 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 147 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 148 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 149 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); 150 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); 151 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); 152 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); 153 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); 154 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); 155 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); 156 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); 157 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 158 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 159 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 160 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 161 #ifndef CONFIG_SYS_FSL_DDR_EMU 162 /* 163 * Skip these two registers if running on emulator 164 * because emulator doesn't have skew between bytes. 165 */ 166 167 if (regs->ddr_wrlvl_cntl_2) 168 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 169 if (regs->ddr_wrlvl_cntl_3) 170 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 171 #endif 172 173 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 174 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 175 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 176 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); 177 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); 178 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); 179 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); 180 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 181 #ifdef CONFIG_DEEP_SLEEP 182 if (is_warm_boot()) { 183 ddr_out32(&ddr->sdram_cfg_2, 184 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 185 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 186 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 187 188 /* DRAM VRef will not be trained */ 189 ddr_out32(&ddr->ddr_cdr2, 190 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 191 } else 192 #endif 193 { 194 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 195 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 196 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 197 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 198 } 199 ddr_out32(&ddr->err_disable, regs->err_disable); 200 ddr_out32(&ddr->err_int_en, regs->err_int_en); 201 for (i = 0; i < 32; i++) { 202 if (regs->debug[i]) { 203 debug("Write to debug_%d as %08x\n", 204 i+1, regs->debug[i]); 205 ddr_out32(&ddr->debug[i], regs->debug[i]); 206 } 207 } 208 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378 209 /* Erratum applies when accumulated ECC is used, or DBI is enabled */ 210 #define IS_ACC_ECC_EN(v) ((v) & 0x4) 211 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) 212 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || 213 IS_DBI(regs->ddr_sdram_cfg_3)) 214 ddr_setbits32(ddr->debug[28], 0x9 << 20); 215 #endif 216 217 /* 218 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 219 * deasserted. Clocks start when any chip select is enabled and clock 220 * control register is set. Because all DDR components are connected to 221 * one reset signal, this needs to be done in two steps. Step 1 is to 222 * get the clocks started. Step 2 resumes after reset signal is 223 * deasserted. 224 */ 225 if (step == 1) { 226 udelay(200); 227 return; 228 } 229 230 step2: 231 /* Set, but do not enable the memory */ 232 temp_sdram_cfg = regs->ddr_sdram_cfg; 233 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 234 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); 235 236 /* 237 * 500 painful micro-seconds must elapse between 238 * the DDR clock setup and the DDR config enable. 239 * DDR2 need 200 us, and DDR3 need 500 us from spec, 240 * we choose the max, that is 500 us for all of case. 241 */ 242 udelay(500); 243 mb(); 244 isb(); 245 246 #ifdef CONFIG_DEEP_SLEEP 247 if (is_warm_boot()) { 248 /* enter self-refresh */ 249 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 250 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 251 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 252 /* do board specific memory setup */ 253 board_mem_sleep_setup(); 254 255 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 256 } else 257 #endif 258 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 259 /* Let the controller go */ 260 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 261 mb(); 262 isb(); 263 264 total_gb_size_per_controller = 0; 265 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 266 if (!(regs->cs[i].config & 0x80000000)) 267 continue; 268 total_gb_size_per_controller += 1 << ( 269 ((regs->cs[i].config >> 14) & 0x3) + 2 + 270 ((regs->cs[i].config >> 8) & 0x7) + 12 + 271 ((regs->cs[i].config >> 4) & 0x3) + 0 + 272 ((regs->cs[i].config >> 0) & 0x7) + 8 + 273 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 274 26); /* minus 26 (count of 64M) */ 275 } 276 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 277 total_gb_size_per_controller *= 3; 278 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 279 total_gb_size_per_controller <<= 1; 280 /* 281 * total memory / bus width = transactions needed 282 * transactions needed / data rate = seconds 283 * to add plenty of buffer, double the time 284 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 285 * Let's wait for 800ms 286 */ 287 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 288 >> SDRAM_CFG_DBW_SHIFT); 289 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 290 (get_ddr_freq(ctrl_num) >> 20)) << 2; 291 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 292 debug("total %d GB\n", total_gb_size_per_controller); 293 debug("Need to wait up to %d * 10ms\n", timeout); 294 295 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 296 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 297 (timeout >= 0)) { 298 udelay(10000); /* throttle polling rate */ 299 timeout--; 300 } 301 302 if (timeout <= 0) 303 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 304 #ifdef CONFIG_DEEP_SLEEP 305 if (is_warm_boot()) { 306 /* exit self-refresh */ 307 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 308 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 309 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 310 } 311 #endif 312 } 313