1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 #include <fsl_immap.h> 12 #include <fsl_ddr.h> 13 #include <fsl_errata.h> 14 15 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \ 16 defined(CONFIG_SYS_FSL_ERRATUM_A009803) 17 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 18 { 19 int timeout = 1000; 20 21 ddr_out32(ptr, value); 22 23 while (ddr_in32(ptr) & bits) { 24 udelay(100); 25 timeout--; 26 } 27 if (timeout <= 0) 28 puts("Error: wait for clear timeout.\n"); 29 } 30 #endif 31 32 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 33 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 34 #endif 35 36 /* 37 * regs has the to-be-set values for DDR controller registers 38 * ctrl_num is the DDR controller number 39 * step: 0 goes through the initialization in one pass 40 * 1 sets registers and returns before enabling controller 41 * 2 resumes from step 1 and continues to initialize 42 * Dividing the initialization to two steps to deassert DDR reset signal 43 * to comply with JEDEC specs for RDIMMs. 44 */ 45 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 46 unsigned int ctrl_num, int step) 47 { 48 unsigned int i, bus_width; 49 struct ccsr_ddr __iomem *ddr; 50 u32 temp32; 51 u32 total_gb_size_per_controller; 52 int timeout; 53 54 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 55 u32 mr6; 56 u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */ 57 u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ 58 u32 *vref_seq = vref_seq1; 59 #endif 60 #ifdef CONFIG_FSL_DDR_BIST 61 u32 mtcr, err_detect, err_sbe; 62 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; 63 #endif 64 #ifdef CONFIG_FSL_DDR_BIST 65 char buffer[CONFIG_SYS_CBSIZE]; 66 #endif 67 switch (ctrl_num) { 68 case 0: 69 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 70 break; 71 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) 72 case 1: 73 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 74 break; 75 #endif 76 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) 77 case 2: 78 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 79 break; 80 #endif 81 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) 82 case 3: 83 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 84 break; 85 #endif 86 default: 87 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 88 return; 89 } 90 91 if (step == 2) 92 goto step2; 93 94 if (regs->ddr_eor) 95 ddr_out32(&ddr->eor, regs->ddr_eor); 96 97 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 98 99 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 100 if (i == 0) { 101 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 102 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 103 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 104 105 } else if (i == 1) { 106 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 107 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 108 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 109 110 } else if (i == 2) { 111 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 112 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 113 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 114 115 } else if (i == 3) { 116 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 117 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 118 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 119 } 120 } 121 122 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 123 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 124 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 125 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 126 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 127 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 128 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); 129 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); 130 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); 131 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); 132 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 133 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); 134 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); 135 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); 136 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); 137 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); 138 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 139 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 140 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 141 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 142 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 143 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 144 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 145 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 146 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); 147 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); 148 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); 149 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); 150 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); 151 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); 152 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); 153 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); 154 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 155 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 156 ddr_out32(&ddr->sdram_interval, 157 regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); 158 #else 159 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 160 #endif 161 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 162 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 163 #ifndef CONFIG_SYS_FSL_DDR_EMU 164 /* 165 * Skip these two registers if running on emulator 166 * because emulator doesn't have skew between bytes. 167 */ 168 169 if (regs->ddr_wrlvl_cntl_2) 170 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 171 if (regs->ddr_wrlvl_cntl_3) 172 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 173 #endif 174 175 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 176 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 177 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 178 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); 179 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); 180 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); 181 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); 182 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 183 #ifdef CONFIG_DEEP_SLEEP 184 if (is_warm_boot()) { 185 ddr_out32(&ddr->sdram_cfg_2, 186 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 187 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 188 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 189 190 /* DRAM VRef will not be trained */ 191 ddr_out32(&ddr->ddr_cdr2, 192 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 193 } else 194 #endif 195 { 196 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 197 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 198 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 199 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 200 } 201 202 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803 203 /* part 1 of 2 */ 204 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 205 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */ 206 ddr_out32(&ddr->ddr_sdram_rcw_2, 207 regs->ddr_sdram_rcw_2 & ~0x0f000000); 208 } 209 ddr_out32(&ddr->err_disable, regs->err_disable | 210 DDR_ERR_DISABLE_APED); 211 } 212 #else 213 ddr_out32(&ddr->err_disable, regs->err_disable); 214 #endif 215 ddr_out32(&ddr->err_int_en, regs->err_int_en); 216 for (i = 0; i < 64; i++) { 217 if (regs->debug[i]) { 218 debug("Write to debug_%d as %08x\n", 219 i+1, regs->debug[i]); 220 ddr_out32(&ddr->debug[i], regs->debug[i]); 221 } 222 } 223 224 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 225 /* Part 1 of 2 */ 226 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 227 /* Disable DRAM VRef training */ 228 ddr_out32(&ddr->ddr_cdr2, 229 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 230 /* disable transmit bit deskew */ 231 temp32 = ddr_in32(&ddr->debug[28]); 232 temp32 |= DDR_TX_BD_DIS; 233 ddr_out32(&ddr->debug[28], temp32); 234 ddr_out32(&ddr->debug[25], 0x9000); 235 } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) { 236 /* Output enable forced off */ 237 ddr_out32(&ddr->debug[37], 1 << 31); 238 /* Enable Vref training */ 239 ddr_out32(&ddr->ddr_cdr2, 240 regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN); 241 } else { 242 debug("Erratum A008511 doesn't apply.\n"); 243 } 244 #endif 245 246 #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \ 247 defined(CONFIG_SYS_FSL_ERRATUM_A008511) 248 /* Disable D_INIT */ 249 ddr_out32(&ddr->sdram_cfg_2, 250 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 251 #endif 252 253 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801 254 temp32 = ddr_in32(&ddr->debug[25]); 255 temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; 256 temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; 257 ddr_out32(&ddr->debug[25], temp32); 258 #endif 259 260 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165 261 temp32 = get_ddr_freq(ctrl_num) / 1000000; 262 if ((temp32 > 1900) && (temp32 < 2300)) { 263 temp32 = ddr_in32(&ddr->debug[28]); 264 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000); 265 } 266 #endif 267 /* 268 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 269 * deasserted. Clocks start when any chip select is enabled and clock 270 * control register is set. Because all DDR components are connected to 271 * one reset signal, this needs to be done in two steps. Step 1 is to 272 * get the clocks started. Step 2 resumes after reset signal is 273 * deasserted. 274 */ 275 if (step == 1) { 276 udelay(200); 277 return; 278 } 279 280 step2: 281 /* Set, but do not enable the memory */ 282 temp32 = regs->ddr_sdram_cfg; 283 temp32 &= ~(SDRAM_CFG_MEM_EN); 284 ddr_out32(&ddr->sdram_cfg, temp32); 285 286 /* 287 * 500 painful micro-seconds must elapse between 288 * the DDR clock setup and the DDR config enable. 289 * DDR2 need 200 us, and DDR3 need 500 us from spec, 290 * we choose the max, that is 500 us for all of case. 291 */ 292 udelay(500); 293 mb(); 294 isb(); 295 296 #ifdef CONFIG_DEEP_SLEEP 297 if (is_warm_boot()) { 298 /* enter self-refresh */ 299 temp32 = ddr_in32(&ddr->sdram_cfg_2); 300 temp32 |= SDRAM_CFG2_FRC_SR; 301 ddr_out32(&ddr->sdram_cfg_2, temp32); 302 /* do board specific memory setup */ 303 board_mem_sleep_setup(); 304 305 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 306 } else 307 #endif 308 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 309 /* Let the controller go */ 310 ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN); 311 mb(); 312 isb(); 313 314 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \ 315 defined(CONFIG_SYS_FSL_ERRATUM_A009803) 316 /* Part 2 of 2 */ 317 timeout = 40; 318 /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */ 319 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 320 (timeout > 0)) { 321 udelay(1000); 322 timeout--; 323 } 324 if (timeout <= 0) { 325 printf("Controler %d timeout, debug_2 = %x\n", 326 ctrl_num, ddr_in32(&ddr->debug[1])); 327 } 328 329 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 330 /* This erraum only applies to verion 5.2.0 */ 331 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 332 /* The vref setting sequence is different for range 2 */ 333 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) 334 vref_seq = vref_seq2; 335 336 /* Set VREF */ 337 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 338 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 339 continue; 340 341 mr6 = (regs->ddr_sdram_mode_10 >> 16) | 342 MD_CNTL_MD_EN | 343 MD_CNTL_CS_SEL(i) | 344 MD_CNTL_MD_SEL(6) | 345 0x00200000; 346 temp32 = mr6 | vref_seq[0]; 347 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 348 temp32, MD_CNTL_MD_EN); 349 udelay(1); 350 debug("MR6 = 0x%08x\n", temp32); 351 temp32 = mr6 | vref_seq[1]; 352 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 353 temp32, MD_CNTL_MD_EN); 354 udelay(1); 355 debug("MR6 = 0x%08x\n", temp32); 356 temp32 = mr6 | vref_seq[2]; 357 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 358 temp32, MD_CNTL_MD_EN); 359 udelay(1); 360 debug("MR6 = 0x%08x\n", temp32); 361 } 362 ddr_out32(&ddr->sdram_md_cntl, 0); 363 temp32 = ddr_in32(&ddr->debug[28]); 364 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */ 365 ddr_out32(&ddr->debug[28], temp32); 366 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ 367 /* wait for idle */ 368 timeout = 40; 369 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 370 (timeout > 0)) { 371 udelay(1000); 372 timeout--; 373 } 374 if (timeout <= 0) { 375 printf("Controler %d timeout, debug_2 = %x\n", 376 ctrl_num, ddr_in32(&ddr->debug[1])); 377 } 378 } 379 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 380 381 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803 382 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 383 /* if it's RDIMM */ 384 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { 385 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 386 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 387 continue; 388 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 389 MD_CNTL_MD_EN | 390 MD_CNTL_CS_SEL(i) | 391 0x070000ed, 392 MD_CNTL_MD_EN); 393 udelay(1); 394 } 395 } 396 397 ddr_out32(&ddr->err_disable, 398 regs->err_disable & ~DDR_ERR_DISABLE_APED); 399 } 400 #endif 401 /* Restore D_INIT */ 402 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 403 #endif 404 405 total_gb_size_per_controller = 0; 406 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 407 if (!(regs->cs[i].config & 0x80000000)) 408 continue; 409 total_gb_size_per_controller += 1 << ( 410 ((regs->cs[i].config >> 14) & 0x3) + 2 + 411 ((regs->cs[i].config >> 8) & 0x7) + 12 + 412 ((regs->cs[i].config >> 4) & 0x3) + 0 + 413 ((regs->cs[i].config >> 0) & 0x7) + 8 + 414 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 415 26); /* minus 26 (count of 64M) */ 416 } 417 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 418 total_gb_size_per_controller *= 3; 419 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 420 total_gb_size_per_controller <<= 1; 421 /* 422 * total memory / bus width = transactions needed 423 * transactions needed / data rate = seconds 424 * to add plenty of buffer, double the time 425 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 426 * Let's wait for 800ms 427 */ 428 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 429 >> SDRAM_CFG_DBW_SHIFT); 430 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 431 (get_ddr_freq(ctrl_num) >> 20)) << 2; 432 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 433 debug("total %d GB\n", total_gb_size_per_controller); 434 debug("Need to wait up to %d * 10ms\n", timeout); 435 436 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 437 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 438 (timeout >= 0)) { 439 udelay(10000); /* throttle polling rate */ 440 timeout--; 441 } 442 443 if (timeout <= 0) 444 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 445 446 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 447 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 448 #endif 449 450 #ifdef CONFIG_DEEP_SLEEP 451 if (is_warm_boot()) { 452 /* exit self-refresh */ 453 temp32 = ddr_in32(&ddr->sdram_cfg_2); 454 temp32 &= ~SDRAM_CFG2_FRC_SR; 455 ddr_out32(&ddr->sdram_cfg_2, temp32); 456 } 457 #endif 458 459 #ifdef CONFIG_FSL_DDR_BIST 460 #define BIST_PATTERN1 0xFFFFFFFF 461 #define BIST_PATTERN2 0x0 462 #define BIST_CR 0x80010000 463 #define BIST_CR_EN 0x80000000 464 #define BIST_CR_STAT 0x00000001 465 #define CTLR_INTLV_MASK 0x20000000 466 /* Perform build-in test on memory. Three-way interleaving is not yet 467 * supported by this code. */ 468 if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) { 469 puts("Running BIST test. This will take a while..."); 470 cs0_config = ddr_in32(&ddr->cs0_config); 471 cs0_bnds = ddr_in32(&ddr->cs0_bnds); 472 cs1_bnds = ddr_in32(&ddr->cs1_bnds); 473 cs2_bnds = ddr_in32(&ddr->cs2_bnds); 474 cs3_bnds = ddr_in32(&ddr->cs3_bnds); 475 if (cs0_config & CTLR_INTLV_MASK) { 476 /* set bnds to non-interleaving */ 477 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); 478 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); 479 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); 480 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); 481 } 482 ddr_out32(&ddr->mtp1, BIST_PATTERN1); 483 ddr_out32(&ddr->mtp2, BIST_PATTERN1); 484 ddr_out32(&ddr->mtp3, BIST_PATTERN2); 485 ddr_out32(&ddr->mtp4, BIST_PATTERN2); 486 ddr_out32(&ddr->mtp5, BIST_PATTERN1); 487 ddr_out32(&ddr->mtp6, BIST_PATTERN1); 488 ddr_out32(&ddr->mtp7, BIST_PATTERN2); 489 ddr_out32(&ddr->mtp8, BIST_PATTERN2); 490 ddr_out32(&ddr->mtp9, BIST_PATTERN1); 491 ddr_out32(&ddr->mtp10, BIST_PATTERN2); 492 mtcr = BIST_CR; 493 ddr_out32(&ddr->mtcr, mtcr); 494 timeout = 100; 495 while (timeout > 0 && (mtcr & BIST_CR_EN)) { 496 mdelay(1000); 497 timeout--; 498 mtcr = ddr_in32(&ddr->mtcr); 499 } 500 if (timeout <= 0) 501 puts("Timeout\n"); 502 else 503 puts("Done\n"); 504 err_detect = ddr_in32(&ddr->err_detect); 505 err_sbe = ddr_in32(&ddr->err_sbe); 506 if (mtcr & BIST_CR_STAT) { 507 printf("BIST test failed on controller %d.\n", 508 ctrl_num); 509 } 510 if (err_detect || (err_sbe & 0xffff)) { 511 printf("ECC error detected on controller %d.\n", 512 ctrl_num); 513 } 514 515 if (cs0_config & CTLR_INTLV_MASK) { 516 /* restore bnds registers */ 517 ddr_out32(&ddr->cs0_bnds, cs0_bnds); 518 ddr_out32(&ddr->cs1_bnds, cs1_bnds); 519 ddr_out32(&ddr->cs2_bnds, cs2_bnds); 520 ddr_out32(&ddr->cs3_bnds, cs3_bnds); 521 } 522 } 523 #endif 524 } 525