1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 #include <fsl_immap.h> 12 #include <fsl_ddr.h> 13 14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 16 #endif 17 18 /* 19 * regs has the to-be-set values for DDR controller registers 20 * ctrl_num is the DDR controller number 21 * step: 0 goes through the initialization in one pass 22 * 1 sets registers and returns before enabling controller 23 * 2 resumes from step 1 and continues to initialize 24 * Dividing the initialization to two steps to deassert DDR reset signal 25 * to comply with JEDEC specs for RDIMMs. 26 */ 27 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 28 unsigned int ctrl_num, int step) 29 { 30 unsigned int i, bus_width; 31 struct ccsr_ddr __iomem *ddr; 32 u32 temp_sdram_cfg; 33 u32 total_gb_size_per_controller; 34 int timeout; 35 36 switch (ctrl_num) { 37 case 0: 38 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 39 break; 40 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 41 case 1: 42 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 43 break; 44 #endif 45 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 46 case 2: 47 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 48 break; 49 #endif 50 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 51 case 3: 52 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 53 break; 54 #endif 55 default: 56 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 57 return; 58 } 59 60 if (step == 2) 61 goto step2; 62 63 if (regs->ddr_eor) 64 ddr_out32(&ddr->eor, regs->ddr_eor); 65 66 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 67 68 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 69 if (i == 0) { 70 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 71 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 72 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 73 74 } else if (i == 1) { 75 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 76 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 77 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 78 79 } else if (i == 2) { 80 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 81 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 82 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 83 84 } else if (i == 3) { 85 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 86 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 87 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 88 } 89 } 90 91 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 92 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 93 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 94 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 95 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 96 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 97 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); 98 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); 99 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); 100 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); 101 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 102 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); 103 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); 104 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); 105 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); 106 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); 107 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 108 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 109 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 110 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 111 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 112 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 113 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 114 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 115 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); 116 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); 117 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); 118 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); 119 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); 120 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); 121 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); 122 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); 123 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 124 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 125 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 126 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 127 #ifndef CONFIG_SYS_FSL_DDR_EMU 128 /* 129 * Skip these two registers if running on emulator 130 * because emulator doesn't have skew between bytes. 131 */ 132 133 if (regs->ddr_wrlvl_cntl_2) 134 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 135 if (regs->ddr_wrlvl_cntl_3) 136 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 137 #endif 138 139 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 140 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 141 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 142 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); 143 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); 144 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); 145 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); 146 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 147 #ifdef CONFIG_DEEP_SLEEP 148 if (is_warm_boot()) { 149 ddr_out32(&ddr->sdram_cfg_2, 150 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 151 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 152 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 153 154 /* DRAM VRef will not be trained */ 155 ddr_out32(&ddr->ddr_cdr2, 156 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 157 } else 158 #endif 159 { 160 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 161 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 162 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 163 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 164 } 165 ddr_out32(&ddr->err_disable, regs->err_disable); 166 ddr_out32(&ddr->err_int_en, regs->err_int_en); 167 for (i = 0; i < 32; i++) { 168 if (regs->debug[i]) { 169 debug("Write to debug_%d as %08x\n", 170 i+1, regs->debug[i]); 171 ddr_out32(&ddr->debug[i], regs->debug[i]); 172 } 173 } 174 175 /* 176 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 177 * deasserted. Clocks start when any chip select is enabled and clock 178 * control register is set. Because all DDR components are connected to 179 * one reset signal, this needs to be done in two steps. Step 1 is to 180 * get the clocks started. Step 2 resumes after reset signal is 181 * deasserted. 182 */ 183 if (step == 1) { 184 udelay(200); 185 return; 186 } 187 188 step2: 189 /* Set, but do not enable the memory */ 190 temp_sdram_cfg = regs->ddr_sdram_cfg; 191 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 192 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); 193 194 /* 195 * 500 painful micro-seconds must elapse between 196 * the DDR clock setup and the DDR config enable. 197 * DDR2 need 200 us, and DDR3 need 500 us from spec, 198 * we choose the max, that is 500 us for all of case. 199 */ 200 udelay(500); 201 mb(); 202 isb(); 203 204 #ifdef CONFIG_DEEP_SLEEP 205 if (is_warm_boot()) { 206 /* enter self-refresh */ 207 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 208 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 209 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 210 /* do board specific memory setup */ 211 board_mem_sleep_setup(); 212 213 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 214 } else 215 #endif 216 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 217 /* Let the controller go */ 218 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 219 mb(); 220 isb(); 221 222 total_gb_size_per_controller = 0; 223 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 224 if (!(regs->cs[i].config & 0x80000000)) 225 continue; 226 total_gb_size_per_controller += 1 << ( 227 ((regs->cs[i].config >> 14) & 0x3) + 2 + 228 ((regs->cs[i].config >> 8) & 0x7) + 12 + 229 ((regs->cs[i].config >> 4) & 0x3) + 0 + 230 ((regs->cs[i].config >> 0) & 0x7) + 8 + 231 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 232 26); /* minus 26 (count of 64M) */ 233 } 234 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 235 total_gb_size_per_controller *= 3; 236 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 237 total_gb_size_per_controller <<= 1; 238 /* 239 * total memory / bus width = transactions needed 240 * transactions needed / data rate = seconds 241 * to add plenty of buffer, double the time 242 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 243 * Let's wait for 800ms 244 */ 245 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 246 >> SDRAM_CFG_DBW_SHIFT); 247 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 248 (get_ddr_freq(0) >> 20)) << 2; 249 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 250 debug("total %d GB\n", total_gb_size_per_controller); 251 debug("Need to wait up to %d * 10ms\n", timeout); 252 253 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 254 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 255 (timeout >= 0)) { 256 udelay(10000); /* throttle polling rate */ 257 timeout--; 258 } 259 260 if (timeout <= 0) 261 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 262 #ifdef CONFIG_DEEP_SLEEP 263 if (is_warm_boot()) { 264 /* exit self-refresh */ 265 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 266 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 267 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 268 } 269 #endif 270 } 271