1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 #include <fsl_immap.h> 12 #include <fsl_ddr.h> 13 14 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 15 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 16 { 17 int timeout = 1000; 18 19 ddr_out32(ptr, value); 20 21 while (ddr_in32(ptr) & bits) { 22 udelay(100); 23 timeout--; 24 } 25 if (timeout <= 0) 26 puts("Error: A007865 wait for clear timeout.\n"); 27 } 28 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 29 30 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 31 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 32 #endif 33 34 /* 35 * regs has the to-be-set values for DDR controller registers 36 * ctrl_num is the DDR controller number 37 * step: 0 goes through the initialization in one pass 38 * 1 sets registers and returns before enabling controller 39 * 2 resumes from step 1 and continues to initialize 40 * Dividing the initialization to two steps to deassert DDR reset signal 41 * to comply with JEDEC specs for RDIMMs. 42 */ 43 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 44 unsigned int ctrl_num, int step) 45 { 46 unsigned int i, bus_width; 47 struct ccsr_ddr __iomem *ddr; 48 u32 temp_sdram_cfg; 49 u32 total_gb_size_per_controller; 50 int timeout; 51 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 52 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 53 u32 *eddrtqcr1; 54 #endif 55 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 56 u32 temp32, mr6; 57 #endif 58 #ifdef CONFIG_FSL_DDR_BIST 59 u32 mtcr, err_detect, err_sbe; 60 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; 61 #endif 62 #ifdef CONFIG_FSL_DDR_BIST 63 char buffer[CONFIG_SYS_CBSIZE]; 64 #endif 65 66 switch (ctrl_num) { 67 case 0: 68 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 69 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 70 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 71 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 72 #endif 73 break; 74 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 75 case 1: 76 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 77 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 78 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 79 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 80 #endif 81 break; 82 #endif 83 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 84 case 2: 85 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 86 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 87 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 88 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 89 #endif 90 break; 91 #endif 92 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 93 case 3: 94 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 95 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ 96 defined(CONFIG_SYS_FSL_ERRATUM_A008514) 97 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800; 98 #endif 99 break; 100 #endif 101 default: 102 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 103 return; 104 } 105 106 if (step == 2) 107 goto step2; 108 109 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 110 #ifdef CONFIG_LS2085A 111 /* A008336 only applies to general DDR controllers */ 112 if ((ctrl_num == 0) || (ctrl_num == 1)) 113 #endif 114 ddr_out32(eddrtqcr1, 0x63b30002); 115 #endif 116 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 117 #ifdef CONFIG_LS2085A 118 /* A008514 only applies to DP-DDR controler */ 119 if (ctrl_num == 2) 120 #endif 121 ddr_out32(eddrtqcr1, 0x63b20002); 122 #endif 123 if (regs->ddr_eor) 124 ddr_out32(&ddr->eor, regs->ddr_eor); 125 126 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 127 128 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 129 if (i == 0) { 130 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 131 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 132 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 133 134 } else if (i == 1) { 135 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 136 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 137 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 138 139 } else if (i == 2) { 140 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 141 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 142 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 143 144 } else if (i == 3) { 145 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 146 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 147 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 148 } 149 } 150 151 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 152 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 153 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 154 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 155 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 156 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 157 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); 158 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); 159 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); 160 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); 161 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 162 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); 163 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); 164 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); 165 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); 166 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); 167 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 168 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 169 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 170 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 171 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 172 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 173 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 174 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 175 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); 176 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); 177 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); 178 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); 179 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); 180 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); 181 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); 182 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); 183 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 184 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 185 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 186 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 187 #ifndef CONFIG_SYS_FSL_DDR_EMU 188 /* 189 * Skip these two registers if running on emulator 190 * because emulator doesn't have skew between bytes. 191 */ 192 193 if (regs->ddr_wrlvl_cntl_2) 194 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 195 if (regs->ddr_wrlvl_cntl_3) 196 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 197 #endif 198 199 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 200 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 201 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 202 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); 203 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); 204 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); 205 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); 206 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 207 #ifdef CONFIG_DEEP_SLEEP 208 if (is_warm_boot()) { 209 ddr_out32(&ddr->sdram_cfg_2, 210 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 211 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 212 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 213 214 /* DRAM VRef will not be trained */ 215 ddr_out32(&ddr->ddr_cdr2, 216 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 217 } else 218 #endif 219 { 220 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 221 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 222 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 223 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 224 } 225 ddr_out32(&ddr->err_disable, regs->err_disable); 226 ddr_out32(&ddr->err_int_en, regs->err_int_en); 227 for (i = 0; i < 32; i++) { 228 if (regs->debug[i]) { 229 debug("Write to debug_%d as %08x\n", 230 i+1, regs->debug[i]); 231 ddr_out32(&ddr->debug[i], regs->debug[i]); 232 } 233 } 234 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378 235 /* Erratum applies when accumulated ECC is used, or DBI is enabled */ 236 #define IS_ACC_ECC_EN(v) ((v) & 0x4) 237 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) 238 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || 239 IS_DBI(regs->ddr_sdram_cfg_3)) 240 ddr_setbits32(ddr->debug[28], 0x9 << 20); 241 #endif 242 243 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 244 /* Part 1 of 2 */ 245 /* This erraum only applies to verion 5.2.0 */ 246 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 247 /* Disable DRAM VRef training */ 248 ddr_out32(&ddr->ddr_cdr2, 249 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 250 /* Disable deskew */ 251 ddr_out32(&ddr->debug[28], 0x400); 252 /* Disable D_INIT */ 253 ddr_out32(&ddr->sdram_cfg_2, 254 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 255 ddr_out32(&ddr->debug[25], 0x9000); 256 } 257 #endif 258 /* 259 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 260 * deasserted. Clocks start when any chip select is enabled and clock 261 * control register is set. Because all DDR components are connected to 262 * one reset signal, this needs to be done in two steps. Step 1 is to 263 * get the clocks started. Step 2 resumes after reset signal is 264 * deasserted. 265 */ 266 if (step == 1) { 267 udelay(200); 268 return; 269 } 270 271 step2: 272 /* Set, but do not enable the memory */ 273 temp_sdram_cfg = regs->ddr_sdram_cfg; 274 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 275 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); 276 277 /* 278 * 500 painful micro-seconds must elapse between 279 * the DDR clock setup and the DDR config enable. 280 * DDR2 need 200 us, and DDR3 need 500 us from spec, 281 * we choose the max, that is 500 us for all of case. 282 */ 283 udelay(500); 284 mb(); 285 isb(); 286 287 #ifdef CONFIG_DEEP_SLEEP 288 if (is_warm_boot()) { 289 /* enter self-refresh */ 290 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 291 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 292 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 293 /* do board specific memory setup */ 294 board_mem_sleep_setup(); 295 296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 297 } else 298 #endif 299 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 300 /* Let the controller go */ 301 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 302 mb(); 303 isb(); 304 305 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 306 /* Part 2 of 2 */ 307 /* This erraum only applies to verion 5.2.0 */ 308 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 309 /* Wait for idle */ 310 timeout = 200; 311 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 312 (timeout > 0)) { 313 udelay(100); 314 timeout--; 315 } 316 if (timeout <= 0) { 317 printf("Controler %d timeout, debug_2 = %x\n", 318 ctrl_num, ddr_in32(&ddr->debug[1])); 319 } 320 /* Set VREF */ 321 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 322 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 323 continue; 324 325 mr6 = (regs->ddr_sdram_mode_10 >> 16) | 326 MD_CNTL_MD_EN | 327 MD_CNTL_CS_SEL(i) | 328 MD_CNTL_MD_SEL(6) | 329 0x00200000; 330 temp32 = mr6 | 0xc0; 331 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 332 temp32, MD_CNTL_MD_EN); 333 udelay(1); 334 debug("MR6 = 0x%08x\n", temp32); 335 temp32 = mr6 | 0xf0; 336 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 337 temp32, MD_CNTL_MD_EN); 338 udelay(1); 339 debug("MR6 = 0x%08x\n", temp32); 340 temp32 = mr6 | 0x70; 341 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 342 temp32, MD_CNTL_MD_EN); 343 udelay(1); 344 debug("MR6 = 0x%08x\n", temp32); 345 } 346 ddr_out32(&ddr->sdram_md_cntl, 0); 347 ddr_out32(&ddr->debug[28], 0); /* Enable deskew */ 348 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ 349 /* wait for idle */ 350 timeout = 200; 351 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 352 (timeout > 0)) { 353 udelay(100); 354 timeout--; 355 } 356 if (timeout <= 0) { 357 printf("Controler %d timeout, debug_2 = %x\n", 358 ctrl_num, ddr_in32(&ddr->debug[1])); 359 } 360 /* Restore D_INIT */ 361 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 362 } 363 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 364 365 total_gb_size_per_controller = 0; 366 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 367 if (!(regs->cs[i].config & 0x80000000)) 368 continue; 369 total_gb_size_per_controller += 1 << ( 370 ((regs->cs[i].config >> 14) & 0x3) + 2 + 371 ((regs->cs[i].config >> 8) & 0x7) + 12 + 372 ((regs->cs[i].config >> 4) & 0x3) + 0 + 373 ((regs->cs[i].config >> 0) & 0x7) + 8 + 374 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 375 26); /* minus 26 (count of 64M) */ 376 } 377 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 378 total_gb_size_per_controller *= 3; 379 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 380 total_gb_size_per_controller <<= 1; 381 /* 382 * total memory / bus width = transactions needed 383 * transactions needed / data rate = seconds 384 * to add plenty of buffer, double the time 385 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 386 * Let's wait for 800ms 387 */ 388 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 389 >> SDRAM_CFG_DBW_SHIFT); 390 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 391 (get_ddr_freq(ctrl_num) >> 20)) << 2; 392 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 393 debug("total %d GB\n", total_gb_size_per_controller); 394 debug("Need to wait up to %d * 10ms\n", timeout); 395 396 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 397 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 398 (timeout >= 0)) { 399 udelay(10000); /* throttle polling rate */ 400 timeout--; 401 } 402 403 if (timeout <= 0) 404 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 405 #ifdef CONFIG_DEEP_SLEEP 406 if (is_warm_boot()) { 407 /* exit self-refresh */ 408 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 409 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 410 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 411 } 412 #endif 413 414 #ifdef CONFIG_FSL_DDR_BIST 415 #define BIST_PATTERN1 0xFFFFFFFF 416 #define BIST_PATTERN2 0x0 417 #define BIST_CR 0x80010000 418 #define BIST_CR_EN 0x80000000 419 #define BIST_CR_STAT 0x00000001 420 #define CTLR_INTLV_MASK 0x20000000 421 /* Perform build-in test on memory. Three-way interleaving is not yet 422 * supported by this code. */ 423 if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) { 424 puts("Running BIST test. This will take a while..."); 425 cs0_config = ddr_in32(&ddr->cs0_config); 426 if (cs0_config & CTLR_INTLV_MASK) { 427 cs0_bnds = ddr_in32(&cs0_bnds); 428 cs1_bnds = ddr_in32(&cs1_bnds); 429 cs2_bnds = ddr_in32(&cs2_bnds); 430 cs3_bnds = ddr_in32(&cs3_bnds); 431 /* set bnds to non-interleaving */ 432 ddr_out32(&cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); 433 ddr_out32(&cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); 434 ddr_out32(&cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); 435 ddr_out32(&cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); 436 } 437 ddr_out32(&ddr->mtp1, BIST_PATTERN1); 438 ddr_out32(&ddr->mtp2, BIST_PATTERN1); 439 ddr_out32(&ddr->mtp3, BIST_PATTERN2); 440 ddr_out32(&ddr->mtp4, BIST_PATTERN2); 441 ddr_out32(&ddr->mtp5, BIST_PATTERN1); 442 ddr_out32(&ddr->mtp6, BIST_PATTERN1); 443 ddr_out32(&ddr->mtp7, BIST_PATTERN2); 444 ddr_out32(&ddr->mtp8, BIST_PATTERN2); 445 ddr_out32(&ddr->mtp9, BIST_PATTERN1); 446 ddr_out32(&ddr->mtp10, BIST_PATTERN2); 447 mtcr = BIST_CR; 448 ddr_out32(&ddr->mtcr, mtcr); 449 timeout = 100; 450 while (timeout > 0 && (mtcr & BIST_CR_EN)) { 451 mdelay(1000); 452 timeout--; 453 mtcr = ddr_in32(&ddr->mtcr); 454 } 455 if (timeout <= 0) 456 puts("Timeout\n"); 457 else 458 puts("Done\n"); 459 err_detect = ddr_in32(&ddr->err_detect); 460 err_sbe = ddr_in32(&ddr->err_sbe); 461 if (mtcr & BIST_CR_STAT) { 462 printf("BIST test failed on controller %d.\n", 463 ctrl_num); 464 } 465 if (err_detect || (err_sbe & 0xffff)) { 466 printf("ECC error detected on controller %d.\n", 467 ctrl_num); 468 } 469 470 if (cs0_config & CTLR_INTLV_MASK) { 471 /* restore bnds registers */ 472 ddr_out32(&cs0_bnds, cs0_bnds); 473 ddr_out32(&cs1_bnds, cs1_bnds); 474 ddr_out32(&cs2_bnds, cs2_bnds); 475 ddr_out32(&cs3_bnds, cs3_bnds); 476 } 477 } 478 #endif 479 } 480