1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/processor.h> 11 #include <fsl_immap.h> 12 #include <fsl_ddr.h> 13 #include <fsl_errata.h> 14 15 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 16 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 17 { 18 int timeout = 1000; 19 20 ddr_out32(ptr, value); 21 22 while (ddr_in32(ptr) & bits) { 23 udelay(100); 24 timeout--; 25 } 26 if (timeout <= 0) 27 puts("Error: A007865 wait for clear timeout.\n"); 28 } 29 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 30 31 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 32 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 33 #endif 34 35 /* 36 * regs has the to-be-set values for DDR controller registers 37 * ctrl_num is the DDR controller number 38 * step: 0 goes through the initialization in one pass 39 * 1 sets registers and returns before enabling controller 40 * 2 resumes from step 1 and continues to initialize 41 * Dividing the initialization to two steps to deassert DDR reset signal 42 * to comply with JEDEC specs for RDIMMs. 43 */ 44 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 45 unsigned int ctrl_num, int step) 46 { 47 unsigned int i, bus_width; 48 struct ccsr_ddr __iomem *ddr; 49 u32 temp_sdram_cfg; 50 u32 total_gb_size_per_controller; 51 int timeout; 52 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 53 u32 temp32, mr6; 54 u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */ 55 u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ 56 u32 *vref_seq = vref_seq1; 57 #endif 58 #ifdef CONFIG_FSL_DDR_BIST 59 u32 mtcr, err_detect, err_sbe; 60 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; 61 #endif 62 #ifdef CONFIG_FSL_DDR_BIST 63 char buffer[CONFIG_SYS_CBSIZE]; 64 #endif 65 66 switch (ctrl_num) { 67 case 0: 68 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 69 break; 70 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 71 case 1: 72 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 73 break; 74 #endif 75 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 76 case 2: 77 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 78 break; 79 #endif 80 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 81 case 3: 82 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 83 break; 84 #endif 85 default: 86 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 87 return; 88 } 89 90 if (step == 2) 91 goto step2; 92 93 if (regs->ddr_eor) 94 ddr_out32(&ddr->eor, regs->ddr_eor); 95 96 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 97 98 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 99 if (i == 0) { 100 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 101 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 102 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 103 104 } else if (i == 1) { 105 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 106 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 107 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 108 109 } else if (i == 2) { 110 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 111 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 112 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 113 114 } else if (i == 3) { 115 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 116 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 117 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 118 } 119 } 120 121 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 122 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 123 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 124 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 125 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 126 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 127 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); 128 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); 129 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); 130 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); 131 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 132 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); 133 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); 134 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); 135 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); 136 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); 137 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 138 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 139 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 140 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 141 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 142 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 143 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 144 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 145 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); 146 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); 147 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); 148 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); 149 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); 150 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); 151 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); 152 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); 153 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 154 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 155 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 156 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 157 #ifndef CONFIG_SYS_FSL_DDR_EMU 158 /* 159 * Skip these two registers if running on emulator 160 * because emulator doesn't have skew between bytes. 161 */ 162 163 if (regs->ddr_wrlvl_cntl_2) 164 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 165 if (regs->ddr_wrlvl_cntl_3) 166 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 167 #endif 168 169 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 170 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 171 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 172 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); 173 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); 174 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); 175 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); 176 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 177 #ifdef CONFIG_DEEP_SLEEP 178 if (is_warm_boot()) { 179 ddr_out32(&ddr->sdram_cfg_2, 180 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 181 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 182 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 183 184 /* DRAM VRef will not be trained */ 185 ddr_out32(&ddr->ddr_cdr2, 186 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 187 } else 188 #endif 189 { 190 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 191 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 192 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 193 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 194 } 195 ddr_out32(&ddr->err_disable, regs->err_disable); 196 ddr_out32(&ddr->err_int_en, regs->err_int_en); 197 for (i = 0; i < 32; i++) { 198 if (regs->debug[i]) { 199 debug("Write to debug_%d as %08x\n", 200 i+1, regs->debug[i]); 201 ddr_out32(&ddr->debug[i], regs->debug[i]); 202 } 203 } 204 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378 205 /* Erratum applies when accumulated ECC is used, or DBI is enabled */ 206 #define IS_ACC_ECC_EN(v) ((v) & 0x4) 207 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) 208 if (has_erratum_a008378()) { 209 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || 210 IS_DBI(regs->ddr_sdram_cfg_3)) 211 ddr_setbits32(&ddr->debug[28], 0x9 << 20); 212 } 213 #endif 214 215 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 216 /* Part 1 of 2 */ 217 /* This erraum only applies to verion 5.2.0 */ 218 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 219 /* Disable DRAM VRef training */ 220 ddr_out32(&ddr->ddr_cdr2, 221 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 222 /* Disable deskew */ 223 ddr_out32(&ddr->debug[28], 0x400); 224 /* Disable D_INIT */ 225 ddr_out32(&ddr->sdram_cfg_2, 226 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 227 ddr_out32(&ddr->debug[25], 0x9000); 228 } 229 #endif 230 /* 231 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 232 * deasserted. Clocks start when any chip select is enabled and clock 233 * control register is set. Because all DDR components are connected to 234 * one reset signal, this needs to be done in two steps. Step 1 is to 235 * get the clocks started. Step 2 resumes after reset signal is 236 * deasserted. 237 */ 238 if (step == 1) { 239 udelay(200); 240 return; 241 } 242 243 step2: 244 /* Set, but do not enable the memory */ 245 temp_sdram_cfg = regs->ddr_sdram_cfg; 246 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 247 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); 248 249 /* 250 * 500 painful micro-seconds must elapse between 251 * the DDR clock setup and the DDR config enable. 252 * DDR2 need 200 us, and DDR3 need 500 us from spec, 253 * we choose the max, that is 500 us for all of case. 254 */ 255 udelay(500); 256 mb(); 257 isb(); 258 259 #ifdef CONFIG_DEEP_SLEEP 260 if (is_warm_boot()) { 261 /* enter self-refresh */ 262 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 263 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 264 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 265 /* do board specific memory setup */ 266 board_mem_sleep_setup(); 267 268 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 269 } else 270 #endif 271 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 272 /* Let the controller go */ 273 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 274 mb(); 275 isb(); 276 277 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 278 /* Part 2 of 2 */ 279 /* This erraum only applies to verion 5.2.0 */ 280 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { 281 /* Wait for idle */ 282 timeout = 40; 283 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 284 (timeout > 0)) { 285 udelay(1000); 286 timeout--; 287 } 288 if (timeout <= 0) { 289 printf("Controler %d timeout, debug_2 = %x\n", 290 ctrl_num, ddr_in32(&ddr->debug[1])); 291 } 292 293 /* The vref setting sequence is different for range 2 */ 294 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) 295 vref_seq = vref_seq2; 296 297 /* Set VREF */ 298 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 299 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) 300 continue; 301 302 mr6 = (regs->ddr_sdram_mode_10 >> 16) | 303 MD_CNTL_MD_EN | 304 MD_CNTL_CS_SEL(i) | 305 MD_CNTL_MD_SEL(6) | 306 0x00200000; 307 temp32 = mr6 | vref_seq[0]; 308 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 309 temp32, MD_CNTL_MD_EN); 310 udelay(1); 311 debug("MR6 = 0x%08x\n", temp32); 312 temp32 = mr6 | vref_seq[1]; 313 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 314 temp32, MD_CNTL_MD_EN); 315 udelay(1); 316 debug("MR6 = 0x%08x\n", temp32); 317 temp32 = mr6 | vref_seq[2]; 318 set_wait_for_bits_clear(&ddr->sdram_md_cntl, 319 temp32, MD_CNTL_MD_EN); 320 udelay(1); 321 debug("MR6 = 0x%08x\n", temp32); 322 } 323 ddr_out32(&ddr->sdram_md_cntl, 0); 324 ddr_out32(&ddr->debug[28], 0); /* Enable deskew */ 325 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ 326 /* wait for idle */ 327 timeout = 40; 328 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && 329 (timeout > 0)) { 330 udelay(1000); 331 timeout--; 332 } 333 if (timeout <= 0) { 334 printf("Controler %d timeout, debug_2 = %x\n", 335 ctrl_num, ddr_in32(&ddr->debug[1])); 336 } 337 /* Restore D_INIT */ 338 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 339 } 340 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */ 341 342 total_gb_size_per_controller = 0; 343 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 344 if (!(regs->cs[i].config & 0x80000000)) 345 continue; 346 total_gb_size_per_controller += 1 << ( 347 ((regs->cs[i].config >> 14) & 0x3) + 2 + 348 ((regs->cs[i].config >> 8) & 0x7) + 12 + 349 ((regs->cs[i].config >> 4) & 0x3) + 0 + 350 ((regs->cs[i].config >> 0) & 0x7) + 8 + 351 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 352 26); /* minus 26 (count of 64M) */ 353 } 354 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 355 total_gb_size_per_controller *= 3; 356 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 357 total_gb_size_per_controller <<= 1; 358 /* 359 * total memory / bus width = transactions needed 360 * transactions needed / data rate = seconds 361 * to add plenty of buffer, double the time 362 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 363 * Let's wait for 800ms 364 */ 365 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 366 >> SDRAM_CFG_DBW_SHIFT); 367 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 368 (get_ddr_freq(ctrl_num) >> 20)) << 2; 369 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 370 debug("total %d GB\n", total_gb_size_per_controller); 371 debug("Need to wait up to %d * 10ms\n", timeout); 372 373 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 374 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 375 (timeout >= 0)) { 376 udelay(10000); /* throttle polling rate */ 377 timeout--; 378 } 379 380 if (timeout <= 0) 381 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 382 #ifdef CONFIG_DEEP_SLEEP 383 if (is_warm_boot()) { 384 /* exit self-refresh */ 385 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 386 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 387 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 388 } 389 #endif 390 391 #ifdef CONFIG_FSL_DDR_BIST 392 #define BIST_PATTERN1 0xFFFFFFFF 393 #define BIST_PATTERN2 0x0 394 #define BIST_CR 0x80010000 395 #define BIST_CR_EN 0x80000000 396 #define BIST_CR_STAT 0x00000001 397 #define CTLR_INTLV_MASK 0x20000000 398 /* Perform build-in test on memory. Three-way interleaving is not yet 399 * supported by this code. */ 400 if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) { 401 puts("Running BIST test. This will take a while..."); 402 cs0_config = ddr_in32(&ddr->cs0_config); 403 cs0_bnds = ddr_in32(&ddr->cs0_bnds); 404 cs1_bnds = ddr_in32(&ddr->cs1_bnds); 405 cs2_bnds = ddr_in32(&ddr->cs2_bnds); 406 cs3_bnds = ddr_in32(&ddr->cs3_bnds); 407 if (cs0_config & CTLR_INTLV_MASK) { 408 /* set bnds to non-interleaving */ 409 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); 410 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); 411 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); 412 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); 413 } 414 ddr_out32(&ddr->mtp1, BIST_PATTERN1); 415 ddr_out32(&ddr->mtp2, BIST_PATTERN1); 416 ddr_out32(&ddr->mtp3, BIST_PATTERN2); 417 ddr_out32(&ddr->mtp4, BIST_PATTERN2); 418 ddr_out32(&ddr->mtp5, BIST_PATTERN1); 419 ddr_out32(&ddr->mtp6, BIST_PATTERN1); 420 ddr_out32(&ddr->mtp7, BIST_PATTERN2); 421 ddr_out32(&ddr->mtp8, BIST_PATTERN2); 422 ddr_out32(&ddr->mtp9, BIST_PATTERN1); 423 ddr_out32(&ddr->mtp10, BIST_PATTERN2); 424 mtcr = BIST_CR; 425 ddr_out32(&ddr->mtcr, mtcr); 426 timeout = 100; 427 while (timeout > 0 && (mtcr & BIST_CR_EN)) { 428 mdelay(1000); 429 timeout--; 430 mtcr = ddr_in32(&ddr->mtcr); 431 } 432 if (timeout <= 0) 433 puts("Timeout\n"); 434 else 435 puts("Done\n"); 436 err_detect = ddr_in32(&ddr->err_detect); 437 err_sbe = ddr_in32(&ddr->err_sbe); 438 if (mtcr & BIST_CR_STAT) { 439 printf("BIST test failed on controller %d.\n", 440 ctrl_num); 441 } 442 if (err_detect || (err_sbe & 0xffff)) { 443 printf("ECC error detected on controller %d.\n", 444 ctrl_num); 445 } 446 447 if (cs0_config & CTLR_INTLV_MASK) { 448 /* restore bnds registers */ 449 ddr_out32(&ddr->cs0_bnds, cs0_bnds); 450 ddr_out32(&ddr->cs1_bnds, cs1_bnds); 451 ddr_out32(&ddr->cs2_bnds, cs2_bnds); 452 ddr_out32(&ddr->cs3_bnds, cs3_bnds); 453 } 454 } 455 #endif 456 } 457