1 /*
2  * Copyright 2014-2016 Freescale Semiconductor, Inc.
3  * Copyright 2017-2018 NXP Semiconductor
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  *
7  * calculate the organization and timing parameter
8  * from ddr3 spd, please refer to the spec
9  * JEDEC standard No.21-C 4_01_02_12R23A.pdf
10  *
11  *
12  */
13 
14 #include <common.h>
15 #include <fsl_ddr_sdram.h>
16 
17 #include <fsl_ddr.h>
18 
19 /*
20  * Calculate the Density of each Physical Rank.
21  * Returned size is in bytes.
22  *
23  * Total DIMM size =
24  * sdram capacity(bit) / 8 * primary bus width / sdram width
25  *                     * Logical Ranks per DIMM
26  *
27  * where: sdram capacity  = spd byte4[3:0]
28  *        primary bus width = spd byte13[2:0]
29  *        sdram width = spd byte12[2:0]
30  *        Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
31  *                                 spd byte12{5:3] * spd byte6[6:4] for 3DS
32  *
33  * To simplify each rank size = total DIMM size / Number of Package Ranks
34  * where Number of Package Ranks = spd byte12[5:3]
35  *
36  * SPD byte4 - sdram density and banks
37  *	bit[3:0]	size(bit)	size(byte)
38  *	0000		256Mb		32MB
39  *	0001		512Mb		64MB
40  *	0010		1Gb		128MB
41  *	0011		2Gb		256MB
42  *	0100		4Gb		512MB
43  *	0101		8Gb		1GB
44  *	0110		16Gb		2GB
45  *      0111		32Gb		4GB
46  *
47  * SPD byte13 - module memory bus width
48  *	bit[2:0]	primary bus width
49  *	000		8bits
50  *	001		16bits
51  *	010		32bits
52  *	011		64bits
53  *
54  * SPD byte12 - module organization
55  *	bit[2:0]	sdram device width
56  *	000		4bits
57  *	001		8bits
58  *	010		16bits
59  *	011		32bits
60  *
61  * SPD byte12 - module organization
62  *	bit[5:3]	number of package ranks per DIMM
63  *	000		1
64  *	001		2
65  *	010		3
66  *	011		4
67  *
68  * SPD byte6 - SDRAM package type
69  *	bit[6:4]	Die count
70  *	000		1
71  *	001		2
72  *	010		3
73  *	011		4
74  *	100		5
75  *	101		6
76  *	110		7
77  *	111		8
78  *
79  * SPD byte6 - SRAM package type
80  *	bit[1:0]	Signal loading
81  *	00		Not specified
82  *	01		Multi load stack
83  *	10		Sigle load stack (3DS)
84  *	11		Reserved
85  */
86 static unsigned long long
87 compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
88 {
89 	unsigned long long bsize;
90 
91 	int nbit_sdram_cap_bsize = 0;
92 	int nbit_primary_bus_width = 0;
93 	int nbit_sdram_width = 0;
94 	int die_count = 0;
95 	bool package_3ds;
96 
97 	if ((spd->density_banks & 0xf) <= 7)
98 		nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
99 	if ((spd->bus_width & 0x7) < 4)
100 		nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
101 	if ((spd->organization & 0x7) < 4)
102 		nbit_sdram_width = (spd->organization & 0x7) + 2;
103 	package_3ds = (spd->package_type & 0x3) == 0x2;
104 	if ((spd->package_type & 0x80) && !package_3ds) { /* other than 3DS */
105 		printf("Warning: not supported SDRAM package type\n");
106 		return 0;
107 	}
108 	if (package_3ds)
109 		die_count = (spd->package_type >> 4) & 0x7;
110 
111 	bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
112 			 nbit_primary_bus_width - nbit_sdram_width +
113 			 die_count);
114 
115 	debug("DDR: DDR rank density = 0x%16llx\n", bsize);
116 
117 	return bsize;
118 }
119 
120 #define spd_to_ps(mtb, ftb)	\
121 	(mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
122 /*
123  * ddr_compute_dimm_parameters for DDR4 SPD
124  *
125  * Compute DIMM parameters based upon the SPD information in spd.
126  * Writes the results to the dimm_params_t structure pointed by pdimm.
127  *
128  */
129 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
130 					 const generic_spd_eeprom_t *spd,
131 					 dimm_params_t *pdimm,
132 					 unsigned int dimm_number)
133 {
134 	unsigned int retval;
135 	int i;
136 	const u8 udimm_rc_e_dq[18] = {
137 		0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
138 		0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
139 	};
140 	int spd_error = 0;
141 	u8 *ptr;
142 	u8 val;
143 
144 	if (spd->mem_type) {
145 		if (spd->mem_type != SPD_MEMTYPE_DDR4) {
146 			printf("Ctrl %u DIMM %u: is not a DDR4 SPD.\n",
147 			       ctrl_num, dimm_number);
148 			return 1;
149 		}
150 	} else {
151 		memset(pdimm, 0, sizeof(dimm_params_t));
152 		return 1;
153 	}
154 
155 	retval = ddr4_spd_check(spd);
156 	if (retval) {
157 		printf("DIMM %u: failed checksum\n", dimm_number);
158 		return 2;
159 	}
160 
161 	/*
162 	 * The part name in ASCII in the SPD EEPROM is not null terminated.
163 	 * Guarantee null termination here by presetting all bytes to 0
164 	 * and copying the part name in ASCII from the SPD onto it
165 	 */
166 	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
167 	if ((spd->info_size_crc & 0xF) > 2)
168 		memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
169 
170 	/* DIMM organization parameters */
171 	pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
172 	pdimm->rank_density = compute_ranksize(spd);
173 	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
174 	pdimm->die_density = spd->density_banks & 0xf;
175 	pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
176 	if ((spd->bus_width >> 3) & 0x3)
177 		pdimm->ec_sdram_width = 8;
178 	else
179 		pdimm->ec_sdram_width = 0;
180 	pdimm->data_width = pdimm->primary_sdram_width
181 			  + pdimm->ec_sdram_width;
182 	pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
183 	pdimm->package_3ds = (spd->package_type & 0x3) == 0x2 ?
184 			     (spd->package_type >> 4) & 0x7 : 0;
185 
186 	/* These are the types defined by the JEDEC SPD spec */
187 	pdimm->mirrored_dimm = 0;
188 	pdimm->registered_dimm = 0;
189 	switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
190 	case DDR4_SPD_MODULETYPE_RDIMM:
191 		/* Registered/buffered DIMMs */
192 		pdimm->registered_dimm = 1;
193 		if (spd->mod_section.registered.reg_map & 0x1)
194 			pdimm->mirrored_dimm = 1;
195 		val = spd->mod_section.registered.ca_stren;
196 		pdimm->rcw[3] = val >> 4;
197 		pdimm->rcw[4] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
198 		val = spd->mod_section.registered.clk_stren;
199 		pdimm->rcw[5] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
200 		/* Not all in SPD. For convience only. Boards may overwrite. */
201 		pdimm->rcw[6] = 0xf;
202 		/*
203 		 * A17 only used for 16Gb and above devices.
204 		 * C[2:0] only used for 3DS.
205 		 */
206 		pdimm->rcw[8] = pdimm->die_density >= 0x6 ? 0x0 : 0x8 |
207 				(pdimm->package_3ds > 0x3 ? 0x0 :
208 				 (pdimm->package_3ds > 0x1 ? 0x1 :
209 				  (pdimm->package_3ds > 0 ? 0x2 : 0x3)));
210 		if (pdimm->package_3ds || pdimm->n_ranks != 4)
211 			pdimm->rcw[13] = 0xc;
212 		else
213 			pdimm->rcw[13] = 0xd;	/* Fix encoded by board */
214 
215 		break;
216 
217 	case DDR4_SPD_MODULETYPE_UDIMM:
218 	case DDR4_SPD_MODULETYPE_SO_DIMM:
219 		/* Unbuffered DIMMs */
220 		if (spd->mod_section.unbuffered.addr_mapping & 0x1)
221 			pdimm->mirrored_dimm = 1;
222 		if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
223 		    (spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
224 			/* Fix SPD error found on DIMMs with raw card E0 */
225 			for (i = 0; i < 18; i++) {
226 				if (spd->mapping[i] == udimm_rc_e_dq[i])
227 					continue;
228 				spd_error = 1;
229 				debug("SPD byte %d: 0x%x, should be 0x%x\n",
230 				      60 + i, spd->mapping[i],
231 				      udimm_rc_e_dq[i]);
232 				ptr = (u8 *)&spd->mapping[i];
233 				*ptr = udimm_rc_e_dq[i];
234 			}
235 			if (spd_error)
236 				puts("SPD DQ mapping error fixed\n");
237 		}
238 		break;
239 
240 	default:
241 		printf("unknown module_type 0x%02X\n", spd->module_type);
242 		return 1;
243 	}
244 
245 	/* SDRAM device parameters */
246 	pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
247 	pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
248 	pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
249 	pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
250 
251 	/*
252 	 * The SPD spec has not the ECC bit,
253 	 * We consider the DIMM as ECC capability
254 	 * when the extension bus exist
255 	 */
256 	if (pdimm->ec_sdram_width)
257 		pdimm->edc_config = 0x02;
258 	else
259 		pdimm->edc_config = 0x00;
260 
261 	/*
262 	 * The SPD spec has not the burst length byte
263 	 * but DDR4 spec has nature BL8 and BC4,
264 	 * BL8 -bit3, BC4 -bit2
265 	 */
266 	pdimm->burst_lengths_bitmask = 0x0c;
267 
268 	/* MTB - medium timebase
269 	 * The MTB in the SPD spec is 125ps,
270 	 *
271 	 * FTB - fine timebase
272 	 * use 1/10th of ps as our unit to avoid floating point
273 	 * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
274 	 */
275 	if ((spd->timebases & 0xf) == 0x0) {
276 		pdimm->mtb_ps = 125;
277 		pdimm->ftb_10th_ps = 10;
278 
279 	} else {
280 		printf("Unknown Timebases\n");
281 	}
282 
283 	/* sdram minimum cycle time */
284 	pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
285 
286 	/* sdram max cycle time */
287 	pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
288 
289 	/*
290 	 * CAS latency supported
291 	 * bit0 - CL7
292 	 * bit4 - CL11
293 	 * bit8 - CL15
294 	 * bit12- CL19
295 	 * bit16- CL23
296 	 */
297 	pdimm->caslat_x  = (spd->caslat_b1 << 7)	|
298 			   (spd->caslat_b2 << 15)	|
299 			   (spd->caslat_b3 << 23);
300 
301 	BUG_ON(spd->caslat_b4 != 0);
302 
303 	/*
304 	 * min CAS latency time
305 	 */
306 	pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
307 
308 	/*
309 	 * min RAS to CAS delay time
310 	 */
311 	pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
312 
313 	/*
314 	 * Min Row Precharge Delay Time
315 	 */
316 	pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
317 
318 	/* min active to precharge delay time */
319 	pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
320 			  spd->tras_min_lsb) * pdimm->mtb_ps;
321 
322 	/* min active to actice/refresh delay time */
323 	pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
324 				   spd->trc_min_lsb), spd->fine_trc_min);
325 	/* Min Refresh Recovery Delay Time */
326 	pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
327 		       pdimm->mtb_ps;
328 	pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
329 		       pdimm->mtb_ps;
330 	pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
331 			pdimm->mtb_ps;
332 	/* min four active window delay time */
333 	pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
334 			pdimm->mtb_ps;
335 
336 	/* min row active to row active delay time, different bank group */
337 	pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
338 	/* min row active to row active delay time, same bank group */
339 	pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
340 	/* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
341 	pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
342 
343 	if (pdimm->package_3ds) {
344 		if (pdimm->die_density <= 0x4) {
345 			pdimm->trfc_slr_ps = 260000;
346 		} else if (pdimm->die_density <= 0x5) {
347 			pdimm->trfc_slr_ps = 350000;
348 		} else {
349 			printf("WARN: Unsupported logical rank density 0x%x\n",
350 			       pdimm->die_density);
351 		}
352 	}
353 
354 	/*
355 	 * Average periodic refresh interval
356 	 * tREFI = 7.8 us at normal temperature range
357 	 */
358 	pdimm->refresh_rate_ps = 7800000;
359 
360 	for (i = 0; i < 18; i++)
361 		pdimm->dq_mapping[i] = spd->mapping[i];
362 
363 	pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
364 
365 	return 0;
366 }
367