1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * calculate the organization and timing parameter 5 * from ddr3 spd, please refer to the spec 6 * JEDEC standard No.21-C 4_01_02_12R23A.pdf 7 * 8 * 9 */ 10 11 #include <common.h> 12 #include <fsl_ddr_sdram.h> 13 14 #include <fsl_ddr.h> 15 16 /* 17 * Calculate the Density of each Physical Rank. 18 * Returned size is in bytes. 19 * 20 * Total DIMM size = 21 * sdram capacity(bit) / 8 * primary bus width / sdram width 22 * * Logical Ranks per DIMM 23 * 24 * where: sdram capacity = spd byte4[3:0] 25 * primary bus width = spd byte13[2:0] 26 * sdram width = spd byte12[2:0] 27 * Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP 28 * spd byte12{5:3] * spd byte6[6:4] for 3DS 29 * 30 * To simplify each rank size = total DIMM size / Number of Package Ranks 31 * where Number of Package Ranks = spd byte12[5:3] 32 * 33 * SPD byte4 - sdram density and banks 34 * bit[3:0] size(bit) size(byte) 35 * 0000 256Mb 32MB 36 * 0001 512Mb 64MB 37 * 0010 1Gb 128MB 38 * 0011 2Gb 256MB 39 * 0100 4Gb 512MB 40 * 0101 8Gb 1GB 41 * 0110 16Gb 2GB 42 * 0111 32Gb 4GB 43 * 44 * SPD byte13 - module memory bus width 45 * bit[2:0] primary bus width 46 * 000 8bits 47 * 001 16bits 48 * 010 32bits 49 * 011 64bits 50 * 51 * SPD byte12 - module organization 52 * bit[2:0] sdram device width 53 * 000 4bits 54 * 001 8bits 55 * 010 16bits 56 * 011 32bits 57 * 58 * SPD byte12 - module organization 59 * bit[5:3] number of package ranks per DIMM 60 * 000 1 61 * 001 2 62 * 010 3 63 * 011 4 64 * 65 * SPD byte6 - SDRAM package type 66 * bit[6:4] Die count 67 * 000 1 68 * 001 2 69 * 010 3 70 * 011 4 71 * 100 5 72 * 101 6 73 * 110 7 74 * 111 8 75 * 76 * SPD byte6 - SRAM package type 77 * bit[1:0] Signal loading 78 * 00 Not specified 79 * 01 Multi load stack 80 * 10 Sigle load stack (3DS) 81 * 11 Reserved 82 */ 83 static unsigned long long 84 compute_ranksize(const struct ddr4_spd_eeprom_s *spd) 85 { 86 unsigned long long bsize; 87 88 int nbit_sdram_cap_bsize = 0; 89 int nbit_primary_bus_width = 0; 90 int nbit_sdram_width = 0; 91 int die_count = 0; 92 bool package_3ds; 93 94 if ((spd->density_banks & 0xf) <= 7) 95 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; 96 if ((spd->bus_width & 0x7) < 4) 97 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; 98 if ((spd->organization & 0x7) < 4) 99 nbit_sdram_width = (spd->organization & 0x7) + 2; 100 package_3ds = (spd->package_type & 0x3) == 0x2; 101 if (package_3ds) 102 die_count = (spd->package_type >> 4) & 0x7; 103 104 bsize = 1ULL << (nbit_sdram_cap_bsize - 3 + 105 nbit_primary_bus_width - nbit_sdram_width + 106 die_count); 107 108 debug("DDR: DDR III rank density = 0x%16llx\n", bsize); 109 110 return bsize; 111 } 112 113 #define spd_to_ps(mtb, ftb) \ 114 (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10) 115 /* 116 * ddr_compute_dimm_parameters for DDR4 SPD 117 * 118 * Compute DIMM parameters based upon the SPD information in spd. 119 * Writes the results to the dimm_params_t structure pointed by pdimm. 120 * 121 */ 122 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, 123 const generic_spd_eeprom_t *spd, 124 dimm_params_t *pdimm, 125 unsigned int dimm_number) 126 { 127 unsigned int retval; 128 int i; 129 const u8 udimm_rc_e_dq[18] = { 130 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15, 131 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36 132 }; 133 int spd_error = 0; 134 u8 *ptr; 135 136 if (spd->mem_type) { 137 if (spd->mem_type != SPD_MEMTYPE_DDR4) { 138 printf("DIMM %u: is not a DDR4 SPD.\n", dimm_number); 139 return 1; 140 } 141 } else { 142 memset(pdimm, 0, sizeof(dimm_params_t)); 143 return 1; 144 } 145 146 retval = ddr4_spd_check(spd); 147 if (retval) { 148 printf("DIMM %u: failed checksum\n", dimm_number); 149 return 2; 150 } 151 152 /* 153 * The part name in ASCII in the SPD EEPROM is not null terminated. 154 * Guarantee null termination here by presetting all bytes to 0 155 * and copying the part name in ASCII from the SPD onto it 156 */ 157 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 158 if ((spd->info_size_crc & 0xF) > 2) 159 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); 160 161 /* DIMM organization parameters */ 162 pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; 163 pdimm->rank_density = compute_ranksize(spd); 164 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; 165 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); 166 if ((spd->bus_width >> 3) & 0x3) 167 pdimm->ec_sdram_width = 8; 168 else 169 pdimm->ec_sdram_width = 0; 170 pdimm->data_width = pdimm->primary_sdram_width 171 + pdimm->ec_sdram_width; 172 pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); 173 174 /* These are the types defined by the JEDEC SPD spec */ 175 pdimm->mirrored_dimm = 0; 176 pdimm->registered_dimm = 0; 177 switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) { 178 case DDR4_SPD_MODULETYPE_RDIMM: 179 /* Registered/buffered DIMMs */ 180 pdimm->registered_dimm = 1; 181 break; 182 183 case DDR4_SPD_MODULETYPE_UDIMM: 184 case DDR4_SPD_MODULETYPE_SO_DIMM: 185 /* Unbuffered DIMMs */ 186 if (spd->mod_section.unbuffered.addr_mapping & 0x1) 187 pdimm->mirrored_dimm = 1; 188 if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 && 189 (spd->mod_section.unbuffered.ref_raw_card == 0x04)) { 190 /* Fix SPD error found on DIMMs with raw card E0 */ 191 for (i = 0; i < 18; i++) { 192 if (spd->mapping[i] == udimm_rc_e_dq[i]) 193 continue; 194 spd_error = 1; 195 debug("SPD byte %d: 0x%x, should be 0x%x\n", 196 60 + i, spd->mapping[i], 197 udimm_rc_e_dq[i]); 198 ptr = (u8 *)&spd->mapping[i]; 199 *ptr = udimm_rc_e_dq[i]; 200 } 201 if (spd_error) 202 puts("SPD DQ mapping error fixed\n"); 203 } 204 break; 205 206 default: 207 printf("unknown module_type 0x%02X\n", spd->module_type); 208 return 1; 209 } 210 211 /* SDRAM device parameters */ 212 pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; 213 pdimm->n_col_addr = (spd->addressing & 0x7) + 9; 214 pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3; 215 pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3; 216 217 /* 218 * The SPD spec has not the ECC bit, 219 * We consider the DIMM as ECC capability 220 * when the extension bus exist 221 */ 222 if (pdimm->ec_sdram_width) 223 pdimm->edc_config = 0x02; 224 else 225 pdimm->edc_config = 0x00; 226 227 /* 228 * The SPD spec has not the burst length byte 229 * but DDR4 spec has nature BL8 and BC4, 230 * BL8 -bit3, BC4 -bit2 231 */ 232 pdimm->burst_lengths_bitmask = 0x0c; 233 pdimm->row_density = __ilog2(pdimm->rank_density); 234 235 /* MTB - medium timebase 236 * The MTB in the SPD spec is 125ps, 237 * 238 * FTB - fine timebase 239 * use 1/10th of ps as our unit to avoid floating point 240 * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps 241 */ 242 if ((spd->timebases & 0xf) == 0x0) { 243 pdimm->mtb_ps = 125; 244 pdimm->ftb_10th_ps = 10; 245 246 } else { 247 printf("Unknown Timebases\n"); 248 } 249 250 /* sdram minimum cycle time */ 251 pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min); 252 253 /* sdram max cycle time */ 254 pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max); 255 256 /* 257 * CAS latency supported 258 * bit0 - CL7 259 * bit4 - CL11 260 * bit8 - CL15 261 * bit12- CL19 262 * bit16- CL23 263 */ 264 pdimm->caslat_x = (spd->caslat_b1 << 7) | 265 (spd->caslat_b2 << 15) | 266 (spd->caslat_b3 << 23); 267 268 BUG_ON(spd->caslat_b4 != 0); 269 270 /* 271 * min CAS latency time 272 */ 273 pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min); 274 275 /* 276 * min RAS to CAS delay time 277 */ 278 pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min); 279 280 /* 281 * Min Row Precharge Delay Time 282 */ 283 pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min); 284 285 /* min active to precharge delay time */ 286 pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) + 287 spd->tras_min_lsb) * pdimm->mtb_ps; 288 289 /* min active to actice/refresh delay time */ 290 pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) + 291 spd->trc_min_lsb), spd->fine_trc_min); 292 /* Min Refresh Recovery Delay Time */ 293 pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) * 294 pdimm->mtb_ps; 295 pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) * 296 pdimm->mtb_ps; 297 pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) * 298 pdimm->mtb_ps; 299 /* min four active window delay time */ 300 pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) * 301 pdimm->mtb_ps; 302 303 /* min row active to row active delay time, different bank group */ 304 pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min); 305 /* min row active to row active delay time, same bank group */ 306 pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min); 307 /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */ 308 pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min); 309 310 /* 311 * Average periodic refresh interval 312 * tREFI = 7.8 us at normal temperature range 313 */ 314 pdimm->refresh_rate_ps = 7800000; 315 316 for (i = 0; i < 18; i++) 317 pdimm->dq_mapping[i] = spd->mapping[i]; 318 319 pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0; 320 321 return 0; 322 } 323