1 /* 2 * Copyright 2008-2012 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * calculate the organization and timing parameter 6 * from ddr3 spd, please refer to the spec 7 * JEDEC standard No.21-C 4_01_02_11R18.pdf 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * Version 2 as published by the Free Software Foundation. 12 */ 13 14 #include <common.h> 15 #include <fsl_ddr_sdram.h> 16 17 #include <fsl_ddr.h> 18 19 /* 20 * Calculate the Density of each Physical Rank. 21 * Returned size is in bytes. 22 * 23 * each rank size = 24 * sdram capacity(bit) / 8 * primary bus width / sdram width 25 * 26 * where: sdram capacity = spd byte4[3:0] 27 * primary bus width = spd byte8[2:0] 28 * sdram width = spd byte7[2:0] 29 * 30 * SPD byte4 - sdram density and banks 31 * bit[3:0] size(bit) size(byte) 32 * 0000 256Mb 32MB 33 * 0001 512Mb 64MB 34 * 0010 1Gb 128MB 35 * 0011 2Gb 256MB 36 * 0100 4Gb 512MB 37 * 0101 8Gb 1GB 38 * 0110 16Gb 2GB 39 * 40 * SPD byte8 - module memory bus width 41 * bit[2:0] primary bus width 42 * 000 8bits 43 * 001 16bits 44 * 010 32bits 45 * 011 64bits 46 * 47 * SPD byte7 - module organiztion 48 * bit[2:0] sdram device width 49 * 000 4bits 50 * 001 8bits 51 * 010 16bits 52 * 011 32bits 53 * 54 */ 55 static unsigned long long 56 compute_ranksize(const ddr3_spd_eeprom_t *spd) 57 { 58 unsigned long long bsize; 59 60 int nbit_sdram_cap_bsize = 0; 61 int nbit_primary_bus_width = 0; 62 int nbit_sdram_width = 0; 63 64 if ((spd->density_banks & 0xf) < 7) 65 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; 66 if ((spd->bus_width & 0x7) < 4) 67 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; 68 if ((spd->organization & 0x7) < 4) 69 nbit_sdram_width = (spd->organization & 0x7) + 2; 70 71 bsize = 1ULL << (nbit_sdram_cap_bsize - 3 72 + nbit_primary_bus_width - nbit_sdram_width); 73 74 debug("DDR: DDR III rank density = 0x%16llx\n", bsize); 75 76 return bsize; 77 } 78 79 /* 80 * ddr_compute_dimm_parameters for DDR3 SPD 81 * 82 * Compute DIMM parameters based upon the SPD information in spd. 83 * Writes the results to the dimm_params_t structure pointed by pdimm. 84 * 85 */ 86 unsigned int 87 ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, 88 dimm_params_t *pdimm, 89 unsigned int dimm_number) 90 { 91 unsigned int retval; 92 unsigned int mtb_ps; 93 int ftb_10th_ps; 94 int i; 95 96 if (spd->mem_type) { 97 if (spd->mem_type != SPD_MEMTYPE_DDR3) { 98 printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number); 99 return 1; 100 } 101 } else { 102 memset(pdimm, 0, sizeof(dimm_params_t)); 103 return 1; 104 } 105 106 retval = ddr3_spd_check(spd); 107 if (retval) { 108 printf("DIMM %u: failed checksum\n", dimm_number); 109 return 2; 110 } 111 112 /* 113 * The part name in ASCII in the SPD EEPROM is not null terminated. 114 * Guarantee null termination here by presetting all bytes to 0 115 * and copying the part name in ASCII from the SPD onto it 116 */ 117 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 118 if ((spd->info_size_crc & 0xF) > 1) 119 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); 120 121 /* DIMM organization parameters */ 122 pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; 123 pdimm->rank_density = compute_ranksize(spd); 124 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; 125 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); 126 if ((spd->bus_width >> 3) & 0x3) 127 pdimm->ec_sdram_width = 8; 128 else 129 pdimm->ec_sdram_width = 0; 130 pdimm->data_width = pdimm->primary_sdram_width 131 + pdimm->ec_sdram_width; 132 pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); 133 134 /* These are the types defined by the JEDEC DDR3 SPD spec */ 135 pdimm->mirrored_dimm = 0; 136 pdimm->registered_dimm = 0; 137 switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { 138 case DDR3_SPD_MODULETYPE_RDIMM: 139 case DDR3_SPD_MODULETYPE_MINI_RDIMM: 140 case DDR3_SPD_MODULETYPE_72B_SO_RDIMM: 141 /* Registered/buffered DIMMs */ 142 pdimm->registered_dimm = 1; 143 for (i = 0; i < 16; i += 2) { 144 u8 rcw = spd->mod_section.registered.rcw[i/2]; 145 pdimm->rcw[i] = (rcw >> 0) & 0x0F; 146 pdimm->rcw[i+1] = (rcw >> 4) & 0x0F; 147 } 148 break; 149 150 case DDR3_SPD_MODULETYPE_UDIMM: 151 case DDR3_SPD_MODULETYPE_SO_DIMM: 152 case DDR3_SPD_MODULETYPE_MICRO_DIMM: 153 case DDR3_SPD_MODULETYPE_MINI_UDIMM: 154 case DDR3_SPD_MODULETYPE_MINI_CDIMM: 155 case DDR3_SPD_MODULETYPE_72B_SO_UDIMM: 156 case DDR3_SPD_MODULETYPE_72B_SO_CDIMM: 157 case DDR3_SPD_MODULETYPE_LRDIMM: 158 case DDR3_SPD_MODULETYPE_16B_SO_DIMM: 159 case DDR3_SPD_MODULETYPE_32B_SO_DIMM: 160 /* Unbuffered DIMMs */ 161 if (spd->mod_section.unbuffered.addr_mapping & 0x1) 162 pdimm->mirrored_dimm = 1; 163 break; 164 165 default: 166 printf("unknown module_type 0x%02X\n", spd->module_type); 167 return 1; 168 } 169 170 /* SDRAM device parameters */ 171 pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; 172 pdimm->n_col_addr = (spd->addressing & 0x7) + 9; 173 pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7); 174 175 /* 176 * The SPD spec has not the ECC bit, 177 * We consider the DIMM as ECC capability 178 * when the extension bus exist 179 */ 180 if (pdimm->ec_sdram_width) 181 pdimm->edc_config = 0x02; 182 else 183 pdimm->edc_config = 0x00; 184 185 /* 186 * The SPD spec has not the burst length byte 187 * but DDR3 spec has nature BL8 and BC4, 188 * BL8 -bit3, BC4 -bit2 189 */ 190 pdimm->burst_lengths_bitmask = 0x0c; 191 pdimm->row_density = __ilog2(pdimm->rank_density); 192 193 /* MTB - medium timebase 194 * The unit in the SPD spec is ns, 195 * We convert it to ps. 196 * eg: MTB = 0.125ns (125ps) 197 */ 198 mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor; 199 pdimm->mtb_ps = mtb_ps; 200 201 /* 202 * FTB - fine timebase 203 * use 1/10th of ps as our unit to avoid floating point 204 * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps 205 */ 206 ftb_10th_ps = 207 ((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f); 208 pdimm->ftb_10th_ps = ftb_10th_ps; 209 /* 210 * sdram minimum cycle time 211 * we assume the MTB is 0.125ns 212 * eg: 213 * tck_min=15 MTB (1.875ns) ->DDR3-1066 214 * =12 MTB (1.5ns) ->DDR3-1333 215 * =10 MTB (1.25ns) ->DDR3-1600 216 */ 217 pdimm->tckmin_x_ps = spd->tck_min * mtb_ps + 218 (spd->fine_tck_min * ftb_10th_ps) / 10; 219 220 /* 221 * CAS latency supported 222 * bit4 - CL4 223 * bit5 - CL5 224 * bit18 - CL18 225 */ 226 pdimm->caslat_x = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; 227 228 /* 229 * min CAS latency time 230 * eg: taa_min = 231 * DDR3-800D 100 MTB (12.5ns) 232 * DDR3-1066F 105 MTB (13.125ns) 233 * DDR3-1333H 108 MTB (13.5ns) 234 * DDR3-1600H 90 MTB (11.25ns) 235 */ 236 pdimm->taa_ps = spd->taa_min * mtb_ps + 237 (spd->fine_taa_min * ftb_10th_ps) / 10; 238 239 /* 240 * min write recovery time 241 * eg: 242 * twr_min = 120 MTB (15ns) -> all speed grades. 243 */ 244 pdimm->twr_ps = spd->twr_min * mtb_ps; 245 246 /* 247 * min RAS to CAS delay time 248 * eg: trcd_min = 249 * DDR3-800 100 MTB (12.5ns) 250 * DDR3-1066F 105 MTB (13.125ns) 251 * DDR3-1333H 108 MTB (13.5ns) 252 * DDR3-1600H 90 MTB (11.25) 253 */ 254 pdimm->trcd_ps = spd->trcd_min * mtb_ps + 255 (spd->fine_trcd_min * ftb_10th_ps) / 10; 256 257 /* 258 * min row active to row active delay time 259 * eg: trrd_min = 260 * DDR3-800(1KB page) 80 MTB (10ns) 261 * DDR3-1333(1KB page) 48 MTB (6ns) 262 */ 263 pdimm->trrd_ps = spd->trrd_min * mtb_ps; 264 265 /* 266 * min row precharge delay time 267 * eg: trp_min = 268 * DDR3-800D 100 MTB (12.5ns) 269 * DDR3-1066F 105 MTB (13.125ns) 270 * DDR3-1333H 108 MTB (13.5ns) 271 * DDR3-1600H 90 MTB (11.25ns) 272 */ 273 pdimm->trp_ps = spd->trp_min * mtb_ps + 274 (spd->fine_trp_min * ftb_10th_ps) / 10; 275 276 /* min active to precharge delay time 277 * eg: tRAS_min = 278 * DDR3-800D 300 MTB (37.5ns) 279 * DDR3-1066F 300 MTB (37.5ns) 280 * DDR3-1333H 288 MTB (36ns) 281 * DDR3-1600H 280 MTB (35ns) 282 */ 283 pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb) 284 * mtb_ps; 285 /* 286 * min active to actice/refresh delay time 287 * eg: tRC_min = 288 * DDR3-800D 400 MTB (50ns) 289 * DDR3-1066F 405 MTB (50.625ns) 290 * DDR3-1333H 396 MTB (49.5ns) 291 * DDR3-1600H 370 MTB (46.25ns) 292 */ 293 pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb) 294 * mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10; 295 /* 296 * min refresh recovery delay time 297 * eg: tRFC_min = 298 * 512Mb 720 MTB (90ns) 299 * 1Gb 880 MTB (110ns) 300 * 2Gb 1280 MTB (160ns) 301 */ 302 pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb) 303 * mtb_ps; 304 /* 305 * min internal write to read command delay time 306 * eg: twtr_min = 40 MTB (7.5ns) - all speed bins. 307 * tWRT is at least 4 mclk independent of operating freq. 308 */ 309 pdimm->twtr_ps = spd->twtr_min * mtb_ps; 310 311 /* 312 * min internal read to precharge command delay time 313 * eg: trtp_min = 40 MTB (7.5ns) - all speed bins. 314 * tRTP is at least 4 mclk independent of operating freq. 315 */ 316 pdimm->trtp_ps = spd->trtp_min * mtb_ps; 317 318 /* 319 * Average periodic refresh interval 320 * tREFI = 7.8 us at normal temperature range 321 * = 3.9 us at ext temperature range 322 */ 323 pdimm->refresh_rate_ps = 7800000; 324 if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) { 325 pdimm->refresh_rate_ps = 3900000; 326 pdimm->extended_op_srt = 1; 327 } 328 329 /* 330 * min four active window delay time 331 * eg: tfaw_min = 332 * DDR3-800(1KB page) 320 MTB (40ns) 333 * DDR3-1066(1KB page) 300 MTB (37.5ns) 334 * DDR3-1333(1KB page) 240 MTB (30ns) 335 * DDR3-1600(1KB page) 240 MTB (30ns) 336 */ 337 pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) 338 * mtb_ps; 339 340 return 0; 341 } 342