1 /*
2  * Copyright 2008 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8 
9 #include <common.h>
10 #include <fsl_ddr_sdram.h>
11 
12 #include <fsl_ddr.h>
13 /*
14  * Calculate the Density of each Physical Rank.
15  * Returned size is in bytes.
16  *
17  * Study these table from Byte 31 of JEDEC SPD Spec.
18  *
19  *		DDR I	DDR II
20  *	Bit	Size	Size
21  *	---	-----	------
22  *	7 high	512MB	512MB
23  *	6	256MB	256MB
24  *	5	128MB	128MB
25  *	4	 64MB	 16GB
26  *	3	 32MB	  8GB
27  *	2	 16MB	  4GB
28  *	1	  2GB	  2GB
29  *	0 low	  1GB	  1GB
30  *
31  * Reorder Table to be linear by stripping the bottom
32  * 2 or 5 bits off and shifting them up to the top.
33  *
34  */
35 static unsigned long long
36 compute_ranksize(unsigned int mem_type, unsigned char row_dens)
37 {
38 	unsigned long long bsize;
39 
40 	/* Bottom 5 bits up to the top. */
41 	bsize = ((row_dens >> 5) | ((row_dens & 31) << 3));
42 	bsize <<= 27ULL;
43 	debug("DDR: DDR II rank density = 0x%16llx\n", bsize);
44 
45 	return bsize;
46 }
47 
48 /*
49  * Convert a two-nibble BCD value into a cycle time.
50  * While the spec calls for nano-seconds, picos are returned.
51  *
52  * This implements the tables for bytes 9, 23 and 25 for both
53  * DDR I and II.  No allowance for distinguishing the invalid
54  * fields absent for DDR I yet present in DDR II is made.
55  * (That is, cycle times of .25, .33, .66 and .75 ns are
56  * allowed for both DDR II and I.)
57  */
58 static unsigned int
59 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
60 {
61 	/* Table look up the lower nibble, allow DDR I & II. */
62 	unsigned int tenths_ps[16] = {
63 		0,
64 		100,
65 		200,
66 		300,
67 		400,
68 		500,
69 		600,
70 		700,
71 		800,
72 		900,
73 		250,	/* This and the next 3 entries valid ... */
74 		330,	/* ...  only for tCK calculations. */
75 		660,
76 		750,
77 		0,	/* undefined */
78 		0	/* undefined */
79 	};
80 
81 	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
82 	unsigned int tenth_ns = spd_val & 0x0F;
83 	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
84 
85 	return ps;
86 }
87 
88 static unsigned int
89 convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
90 {
91 	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
92 	unsigned int hundredth_ns = spd_val & 0x0F;
93 	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
94 
95 	return ps;
96 }
97 
98 static unsigned int byte40_table_ps[8] = {
99 	0,
100 	250,
101 	330,
102 	500,
103 	660,
104 	750,
105 	0,	/* supposed to be RFC, but not sure what that means */
106 	0	/* Undefined */
107 };
108 
109 static unsigned int
110 compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
111 {
112 	unsigned int trfc_ps;
113 
114 	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
115 		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
116 
117 	return trfc_ps;
118 }
119 
120 static unsigned int
121 compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
122 {
123 	unsigned int trc_ps;
124 
125 	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
126 
127 	return trc_ps;
128 }
129 
130 /*
131  * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
132  * Table from SPD Spec, Byte 12, converted to picoseconds and
133  * filled in with "default" normal values.
134  */
135 static unsigned int
136 determine_refresh_rate_ps(const unsigned int spd_refresh)
137 {
138 	unsigned int refresh_time_ps[8] = {
139 		15625000,	/* 0 Normal    1.00x */
140 		3900000,	/* 1 Reduced    .25x */
141 		7800000,	/* 2 Extended   .50x */
142 		31300000,	/* 3 Extended  2.00x */
143 		62500000,	/* 4 Extended  4.00x */
144 		125000000,	/* 5 Extended  8.00x */
145 		15625000,	/* 6 Normal    1.00x  filler */
146 		15625000,	/* 7 Normal    1.00x  filler */
147 	};
148 
149 	return refresh_time_ps[spd_refresh & 0x7];
150 }
151 
152 /*
153  * The purpose of this function is to compute a suitable
154  * CAS latency given the DRAM clock period.  The SPD only
155  * defines at most 3 CAS latencies.  Typically the slower in
156  * frequency the DIMM runs at, the shorter its CAS latency can.
157  * be.  If the DIMM is operating at a sufficiently low frequency,
158  * it may be able to run at a CAS latency shorter than the
159  * shortest SPD-defined CAS latency.
160  *
161  * If a CAS latency is not found, 0 is returned.
162  *
163  * Do this by finding in the standard speed bin table the longest
164  * tCKmin that doesn't exceed the value of mclk_ps (tCK).
165  *
166  * An assumption made is that the SDRAM device allows the
167  * CL to be programmed for a value that is lower than those
168  * advertised by the SPD.  This is not always the case,
169  * as those modes not defined in the SPD are optional.
170  *
171  * CAS latency de-rating based upon values JEDEC Standard No. 79-2C
172  * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS,
173  * and tRC for corresponding bin"
174  *
175  * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
176  * Not certain if any good value exists for CL=2
177  */
178 				 /* CL2   CL3   CL4   CL5   CL6  CL7*/
179 unsigned short ddr2_speed_bins[] = {   0, 5000, 3750, 3000, 2500, 1875 };
180 
181 unsigned int
182 compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
183 {
184 	const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins);
185 	unsigned int lowest_tCKmin_found = 0;
186 	unsigned int lowest_tCKmin_CL = 0;
187 	unsigned int i;
188 
189 	debug("mclk_ps = %u\n", mclk_ps);
190 
191 	for (i = 0; i < num_speed_bins; i++) {
192 		unsigned int x = ddr2_speed_bins[i];
193 		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
194 		      i, x, lowest_tCKmin_found);
195 		if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) {
196 			lowest_tCKmin_found = x;
197 			lowest_tCKmin_CL = i + 2;
198 		}
199 	}
200 
201 	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
202 
203 	return lowest_tCKmin_CL;
204 }
205 
206 /*
207  * ddr_compute_dimm_parameters for DDR2 SPD
208  *
209  * Compute DIMM parameters based upon the SPD information in spd.
210  * Writes the results to the dimm_params_t structure pointed by pdimm.
211  *
212  * FIXME: use #define for the retvals
213  */
214 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
215 					 const ddr2_spd_eeprom_t *spd,
216 					 dimm_params_t *pdimm,
217 					 unsigned int dimm_number)
218 {
219 	unsigned int retval;
220 
221 	if (spd->mem_type) {
222 		if (spd->mem_type != SPD_MEMTYPE_DDR2) {
223 			printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number);
224 			return 1;
225 		}
226 	} else {
227 		memset(pdimm, 0, sizeof(dimm_params_t));
228 		return 1;
229 	}
230 
231 	retval = ddr2_spd_check(spd);
232 	if (retval) {
233 		printf("DIMM %u: failed checksum\n", dimm_number);
234 		return 2;
235 	}
236 
237 	/*
238 	 * The part name in ASCII in the SPD EEPROM is not null terminated.
239 	 * Guarantee null termination here by presetting all bytes to 0
240 	 * and copying the part name in ASCII from the SPD onto it
241 	 */
242 	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
243 	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
244 
245 	/* DIMM organization parameters */
246 	pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1;
247 	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens);
248 	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
249 	pdimm->data_width = spd->dataw;
250 	pdimm->primary_sdram_width = spd->primw;
251 	pdimm->ec_sdram_width = spd->ecw;
252 
253 	/* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */
254 	switch (spd->dimm_type) {
255 	case DDR2_SPD_DIMMTYPE_RDIMM:
256 	case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM:
257 	case DDR2_SPD_DIMMTYPE_MINI_RDIMM:
258 		/* Registered/buffered DIMMs */
259 		pdimm->registered_dimm = 1;
260 		break;
261 
262 	case DDR2_SPD_DIMMTYPE_UDIMM:
263 	case DDR2_SPD_DIMMTYPE_SO_DIMM:
264 	case DDR2_SPD_DIMMTYPE_MICRO_DIMM:
265 	case DDR2_SPD_DIMMTYPE_MINI_UDIMM:
266 		/* Unbuffered DIMMs */
267 		pdimm->registered_dimm = 0;
268 		break;
269 
270 	case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM:
271 	default:
272 		printf("unknown dimm_type 0x%02X\n", spd->dimm_type);
273 		return 1;
274 	}
275 
276 	/* SDRAM device parameters */
277 	pdimm->n_row_addr = spd->nrow_addr;
278 	pdimm->n_col_addr = spd->ncol_addr;
279 	pdimm->n_banks_per_sdram_device = spd->nbanks;
280 	pdimm->edc_config = spd->config;
281 	pdimm->burst_lengths_bitmask = spd->burstl;
282 	pdimm->row_density = spd->rank_dens;
283 
284 	/*
285 	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
286 	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
287 	 * nanoseconds and represented as BCD.
288 	 */
289 	pdimm->tckmin_x_ps
290 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
291 	pdimm->tckmin_x_minus_1_ps
292 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
293 	pdimm->tckmin_x_minus_2_ps
294 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
295 
296 	pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
297 
298 	/*
299 	 * Compute CAS latencies defined by SPD
300 	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
301 	 *
302 	 * If cas_lat after masking is 0, the __ilog2 function returns
303 	 * 255 into the variable.   This behavior is abused once.
304 	 */
305 	pdimm->caslat_x  = __ilog2(spd->cas_lat);
306 	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
307 					  & ~(1 << pdimm->caslat_x));
308 	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
309 					  & ~(1 << pdimm->caslat_x)
310 					  & ~(1 << pdimm->caslat_x_minus_1));
311 
312 	/* Compute CAS latencies below that defined by SPD */
313 	pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency(
314 					get_memory_clk_period_ps(ctrl_num));
315 
316 	/* Compute timing parameters */
317 	pdimm->trcd_ps = spd->trcd * 250;
318 	pdimm->trp_ps = spd->trp * 250;
319 	pdimm->tras_ps = spd->tras * 1000;
320 
321 	pdimm->twr_ps = spd->twr * 250;
322 	pdimm->twtr_ps = spd->twtr * 250;
323 	pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
324 
325 	pdimm->trrd_ps = spd->trrd * 250;
326 	pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
327 
328 	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
329 
330 	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
331 	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
332 	pdimm->tds_ps
333 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
334 	pdimm->tdh_ps
335 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
336 
337 	pdimm->trtp_ps = spd->trtp * 250;
338 	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
339 	pdimm->tqhs_ps = spd->tqhs * 10;
340 
341 	return 0;
342 }
343