1 /*
2  * Copyright 2008 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8 
9 #include <common.h>
10 #include <fsl_ddr_sdram.h>
11 
12 #include <fsl_ddr.h>
13 
14 /*
15  * Calculate the Density of each Physical Rank.
16  * Returned size is in bytes.
17  *
18  * Study these table from Byte 31 of JEDEC SPD Spec.
19  *
20  *		DDR I	DDR II
21  *	Bit	Size	Size
22  *	---	-----	------
23  *	7 high	512MB	512MB
24  *	6	256MB	256MB
25  *	5	128MB	128MB
26  *	4	 64MB	 16GB
27  *	3	 32MB	  8GB
28  *	2	 16MB	  4GB
29  *	1	  2GB	  2GB
30  *	0 low	  1GB	  1GB
31  *
32  * Reorder Table to be linear by stripping the bottom
33  * 2 or 5 bits off and shifting them up to the top.
34  */
35 
36 static unsigned long long
37 compute_ranksize(unsigned int mem_type, unsigned char row_dens)
38 {
39 	unsigned long long bsize;
40 
41 	/* Bottom 2 bits up to the top. */
42 	bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
43 	bsize <<= 24ULL;
44 	debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
45 
46 	return bsize;
47 }
48 
49 /*
50  * Convert a two-nibble BCD value into a cycle time.
51  * While the spec calls for nano-seconds, picos are returned.
52  *
53  * This implements the tables for bytes 9, 23 and 25 for both
54  * DDR I and II.  No allowance for distinguishing the invalid
55  * fields absent for DDR I yet present in DDR II is made.
56  * (That is, cycle times of .25, .33, .66 and .75 ns are
57  * allowed for both DDR II and I.)
58  */
59 static unsigned int
60 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
61 {
62 	/* Table look up the lower nibble, allow DDR I & II. */
63 	unsigned int tenths_ps[16] = {
64 		0,
65 		100,
66 		200,
67 		300,
68 		400,
69 		500,
70 		600,
71 		700,
72 		800,
73 		900,
74 		250,	/* This and the next 3 entries valid ... */
75 		330,	/* ...  only for tCK calculations. */
76 		660,
77 		750,
78 		0,	/* undefined */
79 		0	/* undefined */
80 	};
81 
82 	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
83 	unsigned int tenth_ns = spd_val & 0x0F;
84 	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
85 
86 	return ps;
87 }
88 
89 static unsigned int
90 convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
91 {
92 	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
93 	unsigned int hundredth_ns = spd_val & 0x0F;
94 	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
95 
96 	return ps;
97 }
98 
99 static unsigned int byte40_table_ps[8] = {
100 	0,
101 	250,
102 	330,
103 	500,
104 	660,
105 	750,
106 	0,	/* supposed to be RFC, but not sure what that means */
107 	0	/* Undefined */
108 };
109 
110 static unsigned int
111 compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
112 {
113 	unsigned int trfc_ps;
114 
115 	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
116 		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
117 
118 	return trfc_ps;
119 }
120 
121 static unsigned int
122 compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
123 {
124 	unsigned int trc_ps;
125 
126 	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
127 
128 	return trc_ps;
129 }
130 
131 /*
132  * tCKmax from DDR I SPD Byte 43
133  *
134  * Bits 7:2 == whole ns
135  * Bits 1:0 == quarter ns
136  *    00    == 0.00 ns
137  *    01    == 0.25 ns
138  *    10    == 0.50 ns
139  *    11    == 0.75 ns
140  *
141  * Returns picoseconds.
142  */
143 static unsigned int
144 compute_tckmax_from_spd_ps(unsigned int byte43)
145 {
146 	return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
147 }
148 
149 /*
150  * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
151  * Table from SPD Spec, Byte 12, converted to picoseconds and
152  * filled in with "default" normal values.
153  */
154 static unsigned int
155 determine_refresh_rate_ps(const unsigned int spd_refresh)
156 {
157 	unsigned int refresh_time_ps[8] = {
158 		15625000,	/* 0 Normal    1.00x */
159 		3900000,	/* 1 Reduced    .25x */
160 		7800000,	/* 2 Extended   .50x */
161 		31300000,	/* 3 Extended  2.00x */
162 		62500000,	/* 4 Extended  4.00x */
163 		125000000,	/* 5 Extended  8.00x */
164 		15625000,	/* 6 Normal    1.00x  filler */
165 		15625000,	/* 7 Normal    1.00x  filler */
166 	};
167 
168 	return refresh_time_ps[spd_refresh & 0x7];
169 }
170 
171 /*
172  * The purpose of this function is to compute a suitable
173  * CAS latency given the DRAM clock period.  The SPD only
174  * defines at most 3 CAS latencies.  Typically the slower in
175  * frequency the DIMM runs at, the shorter its CAS latency can be.
176  * If the DIMM is operating at a sufficiently low frequency,
177  * it may be able to run at a CAS latency shorter than the
178  * shortest SPD-defined CAS latency.
179  *
180  * If a CAS latency is not found, 0 is returned.
181  *
182  * Do this by finding in the standard speed bin table the longest
183  * tCKmin that doesn't exceed the value of mclk_ps (tCK).
184  *
185  * An assumption made is that the SDRAM device allows the
186  * CL to be programmed for a value that is lower than those
187  * advertised by the SPD.  This is not always the case,
188  * as those modes not defined in the SPD are optional.
189  *
190  * CAS latency de-rating based upon values JEDEC Standard No. 79-E
191  * Table 11.
192  *
193  * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
194  */
195 				  /*   CL2.0 CL2.5 CL3.0  */
196 unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };
197 
198 unsigned int
199 compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
200 {
201 	const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
202 	unsigned int lowest_tCKmin_found = 0;
203 	unsigned int lowest_tCKmin_CL = 0;
204 	unsigned int i;
205 
206 	debug("mclk_ps = %u\n", mclk_ps);
207 
208 	for (i = 0; i < num_speed_bins; i++) {
209 		unsigned int x = ddr1_speed_bins[i];
210 		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
211 		      i, x, lowest_tCKmin_found);
212 		if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
213 			lowest_tCKmin_found = x;
214 			lowest_tCKmin_CL = i + 1;
215 		}
216 	}
217 
218 	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
219 
220 	return lowest_tCKmin_CL;
221 }
222 
223 /*
224  * ddr_compute_dimm_parameters for DDR1 SPD
225  *
226  * Compute DIMM parameters based upon the SPD information in spd.
227  * Writes the results to the dimm_params_t structure pointed by pdimm.
228  *
229  * FIXME: use #define for the retvals
230  */
231 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
232 					 const ddr1_spd_eeprom_t *spd,
233 					 dimm_params_t *pdimm,
234 					 unsigned int dimm_number)
235 {
236 	unsigned int retval;
237 
238 	if (spd->mem_type) {
239 		if (spd->mem_type != SPD_MEMTYPE_DDR) {
240 			printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
241 			return 1;
242 		}
243 	} else {
244 		memset(pdimm, 0, sizeof(dimm_params_t));
245 		return 1;
246 	}
247 
248 	retval = ddr1_spd_check(spd);
249 	if (retval) {
250 		printf("DIMM %u: failed checksum\n", dimm_number);
251 		return 2;
252 	}
253 
254 	/*
255 	 * The part name in ASCII in the SPD EEPROM is not null terminated.
256 	 * Guarantee null termination here by presetting all bytes to 0
257 	 * and copying the part name in ASCII from the SPD onto it
258 	 */
259 	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
260 	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
261 
262 	/* DIMM organization parameters */
263 	pdimm->n_ranks = spd->nrows;
264 	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
265 	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
266 	pdimm->data_width = spd->dataw_lsb;
267 	pdimm->primary_sdram_width = spd->primw;
268 	pdimm->ec_sdram_width = spd->ecw;
269 
270 	/*
271 	 * FIXME: Need to determine registered_dimm status.
272 	 *     1 == register buffered
273 	 *     0 == unbuffered
274 	 */
275 	pdimm->registered_dimm = 0;	/* unbuffered */
276 
277 	/* SDRAM device parameters */
278 	pdimm->n_row_addr = spd->nrow_addr;
279 	pdimm->n_col_addr = spd->ncol_addr;
280 	pdimm->n_banks_per_sdram_device = spd->nbanks;
281 	pdimm->edc_config = spd->config;
282 	pdimm->burst_lengths_bitmask = spd->burstl;
283 	pdimm->row_density = spd->bank_dens;
284 
285 	/*
286 	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
287 	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
288 	 * nanoseconds and represented as BCD.
289 	 */
290 	pdimm->tckmin_x_ps
291 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
292 	pdimm->tckmin_x_minus_1_ps
293 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
294 	pdimm->tckmin_x_minus_2_ps
295 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
296 
297 	pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
298 
299 	/*
300 	 * Compute CAS latencies defined by SPD
301 	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
302 	 *
303 	 * If cas_lat after masking is 0, the __ilog2 function returns
304 	 * 255 into the variable.   This behavior is abused once.
305 	 */
306 	pdimm->caslat_x  = __ilog2(spd->cas_lat);
307 	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
308 					  & ~(1 << pdimm->caslat_x));
309 	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
310 					  & ~(1 << pdimm->caslat_x)
311 					  & ~(1 << pdimm->caslat_x_minus_1));
312 
313 	/* Compute CAS latencies below that defined by SPD */
314 	pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
315 					get_memory_clk_period_ps(ctrl_num));
316 
317 	/* Compute timing parameters */
318 	pdimm->trcd_ps = spd->trcd * 250;
319 	pdimm->trp_ps = spd->trp * 250;
320 	pdimm->tras_ps = spd->tras * 1000;
321 
322 	pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
323 	pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
324 	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
325 
326 	pdimm->trrd_ps = spd->trrd * 250;
327 	pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
328 
329 	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
330 
331 	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
332 	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
333 	pdimm->tds_ps
334 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
335 	pdimm->tdh_ps
336 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
337 
338 	pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2);	/* By the book. */
339 	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
340 	pdimm->tqhs_ps = spd->tqhs * 10;
341 
342 	return 0;
343 }
344