1 /*
2  * Copyright 2008 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0
5  */
6 
7 #include <common.h>
8 #include <fsl_ddr_sdram.h>
9 
10 #include <fsl_ddr.h>
11 
12 /*
13  * Calculate the Density of each Physical Rank.
14  * Returned size is in bytes.
15  *
16  * Study these table from Byte 31 of JEDEC SPD Spec.
17  *
18  *		DDR I	DDR II
19  *	Bit	Size	Size
20  *	---	-----	------
21  *	7 high	512MB	512MB
22  *	6	256MB	256MB
23  *	5	128MB	128MB
24  *	4	 64MB	 16GB
25  *	3	 32MB	  8GB
26  *	2	 16MB	  4GB
27  *	1	  2GB	  2GB
28  *	0 low	  1GB	  1GB
29  *
30  * Reorder Table to be linear by stripping the bottom
31  * 2 or 5 bits off and shifting them up to the top.
32  */
33 
34 static unsigned long long
35 compute_ranksize(unsigned int mem_type, unsigned char row_dens)
36 {
37 	unsigned long long bsize;
38 
39 	/* Bottom 2 bits up to the top. */
40 	bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
41 	bsize <<= 24ULL;
42 	debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
43 
44 	return bsize;
45 }
46 
47 /*
48  * Convert a two-nibble BCD value into a cycle time.
49  * While the spec calls for nano-seconds, picos are returned.
50  *
51  * This implements the tables for bytes 9, 23 and 25 for both
52  * DDR I and II.  No allowance for distinguishing the invalid
53  * fields absent for DDR I yet present in DDR II is made.
54  * (That is, cycle times of .25, .33, .66 and .75 ns are
55  * allowed for both DDR II and I.)
56  */
57 static unsigned int
58 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
59 {
60 	/* Table look up the lower nibble, allow DDR I & II. */
61 	unsigned int tenths_ps[16] = {
62 		0,
63 		100,
64 		200,
65 		300,
66 		400,
67 		500,
68 		600,
69 		700,
70 		800,
71 		900,
72 		250,	/* This and the next 3 entries valid ... */
73 		330,	/* ...  only for tCK calculations. */
74 		660,
75 		750,
76 		0,	/* undefined */
77 		0	/* undefined */
78 	};
79 
80 	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
81 	unsigned int tenth_ns = spd_val & 0x0F;
82 	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
83 
84 	return ps;
85 }
86 
87 static unsigned int
88 convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
89 {
90 	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
91 	unsigned int hundredth_ns = spd_val & 0x0F;
92 	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
93 
94 	return ps;
95 }
96 
97 static unsigned int byte40_table_ps[8] = {
98 	0,
99 	250,
100 	330,
101 	500,
102 	660,
103 	750,
104 	0,	/* supposed to be RFC, but not sure what that means */
105 	0	/* Undefined */
106 };
107 
108 static unsigned int
109 compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
110 {
111 	unsigned int trfc_ps;
112 
113 	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
114 		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
115 
116 	return trfc_ps;
117 }
118 
119 static unsigned int
120 compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
121 {
122 	unsigned int trc_ps;
123 
124 	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
125 
126 	return trc_ps;
127 }
128 
129 /*
130  * tCKmax from DDR I SPD Byte 43
131  *
132  * Bits 7:2 == whole ns
133  * Bits 1:0 == quarter ns
134  *    00    == 0.00 ns
135  *    01    == 0.25 ns
136  *    10    == 0.50 ns
137  *    11    == 0.75 ns
138  *
139  * Returns picoseconds.
140  */
141 static unsigned int
142 compute_tckmax_from_spd_ps(unsigned int byte43)
143 {
144 	return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
145 }
146 
147 /*
148  * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
149  * Table from SPD Spec, Byte 12, converted to picoseconds and
150  * filled in with "default" normal values.
151  */
152 static unsigned int
153 determine_refresh_rate_ps(const unsigned int spd_refresh)
154 {
155 	unsigned int refresh_time_ps[8] = {
156 		15625000,	/* 0 Normal    1.00x */
157 		3900000,	/* 1 Reduced    .25x */
158 		7800000,	/* 2 Extended   .50x */
159 		31300000,	/* 3 Extended  2.00x */
160 		62500000,	/* 4 Extended  4.00x */
161 		125000000,	/* 5 Extended  8.00x */
162 		15625000,	/* 6 Normal    1.00x  filler */
163 		15625000,	/* 7 Normal    1.00x  filler */
164 	};
165 
166 	return refresh_time_ps[spd_refresh & 0x7];
167 }
168 
169 /*
170  * The purpose of this function is to compute a suitable
171  * CAS latency given the DRAM clock period.  The SPD only
172  * defines at most 3 CAS latencies.  Typically the slower in
173  * frequency the DIMM runs at, the shorter its CAS latency can be.
174  * If the DIMM is operating at a sufficiently low frequency,
175  * it may be able to run at a CAS latency shorter than the
176  * shortest SPD-defined CAS latency.
177  *
178  * If a CAS latency is not found, 0 is returned.
179  *
180  * Do this by finding in the standard speed bin table the longest
181  * tCKmin that doesn't exceed the value of mclk_ps (tCK).
182  *
183  * An assumption made is that the SDRAM device allows the
184  * CL to be programmed for a value that is lower than those
185  * advertised by the SPD.  This is not always the case,
186  * as those modes not defined in the SPD are optional.
187  *
188  * CAS latency de-rating based upon values JEDEC Standard No. 79-E
189  * Table 11.
190  *
191  * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
192  */
193 				  /*   CL2.0 CL2.5 CL3.0  */
194 unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };
195 
196 unsigned int
197 compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
198 {
199 	const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
200 	unsigned int lowest_tCKmin_found = 0;
201 	unsigned int lowest_tCKmin_CL = 0;
202 	unsigned int i;
203 
204 	debug("mclk_ps = %u\n", mclk_ps);
205 
206 	for (i = 0; i < num_speed_bins; i++) {
207 		unsigned int x = ddr1_speed_bins[i];
208 		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
209 		      i, x, lowest_tCKmin_found);
210 		if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
211 			lowest_tCKmin_found = x;
212 			lowest_tCKmin_CL = i + 1;
213 		}
214 	}
215 
216 	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
217 
218 	return lowest_tCKmin_CL;
219 }
220 
221 /*
222  * ddr_compute_dimm_parameters for DDR1 SPD
223  *
224  * Compute DIMM parameters based upon the SPD information in spd.
225  * Writes the results to the dimm_params_t structure pointed by pdimm.
226  *
227  * FIXME: use #define for the retvals
228  */
229 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
230 					 const ddr1_spd_eeprom_t *spd,
231 					 dimm_params_t *pdimm,
232 					 unsigned int dimm_number)
233 {
234 	unsigned int retval;
235 
236 	if (spd->mem_type) {
237 		if (spd->mem_type != SPD_MEMTYPE_DDR) {
238 			printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
239 			return 1;
240 		}
241 	} else {
242 		memset(pdimm, 0, sizeof(dimm_params_t));
243 		return 1;
244 	}
245 
246 	retval = ddr1_spd_check(spd);
247 	if (retval) {
248 		printf("DIMM %u: failed checksum\n", dimm_number);
249 		return 2;
250 	}
251 
252 	/*
253 	 * The part name in ASCII in the SPD EEPROM is not null terminated.
254 	 * Guarantee null termination here by presetting all bytes to 0
255 	 * and copying the part name in ASCII from the SPD onto it
256 	 */
257 	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
258 	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
259 
260 	/* DIMM organization parameters */
261 	pdimm->n_ranks = spd->nrows;
262 	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
263 	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
264 	pdimm->data_width = spd->dataw_lsb;
265 	pdimm->primary_sdram_width = spd->primw;
266 	pdimm->ec_sdram_width = spd->ecw;
267 
268 	/*
269 	 * FIXME: Need to determine registered_dimm status.
270 	 *     1 == register buffered
271 	 *     0 == unbuffered
272 	 */
273 	pdimm->registered_dimm = 0;	/* unbuffered */
274 
275 	/* SDRAM device parameters */
276 	pdimm->n_row_addr = spd->nrow_addr;
277 	pdimm->n_col_addr = spd->ncol_addr;
278 	pdimm->n_banks_per_sdram_device = spd->nbanks;
279 	pdimm->edc_config = spd->config;
280 	pdimm->burst_lengths_bitmask = spd->burstl;
281 	pdimm->row_density = spd->bank_dens;
282 
283 	/*
284 	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
285 	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
286 	 * nanoseconds and represented as BCD.
287 	 */
288 	pdimm->tckmin_x_ps
289 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
290 	pdimm->tckmin_x_minus_1_ps
291 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
292 	pdimm->tckmin_x_minus_2_ps
293 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
294 
295 	pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
296 
297 	/*
298 	 * Compute CAS latencies defined by SPD
299 	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
300 	 *
301 	 * If cas_lat after masking is 0, the __ilog2 function returns
302 	 * 255 into the variable.   This behavior is abused once.
303 	 */
304 	pdimm->caslat_x  = __ilog2(spd->cas_lat);
305 	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
306 					  & ~(1 << pdimm->caslat_x));
307 	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
308 					  & ~(1 << pdimm->caslat_x)
309 					  & ~(1 << pdimm->caslat_x_minus_1));
310 
311 	/* Compute CAS latencies below that defined by SPD */
312 	pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
313 					get_memory_clk_period_ps(ctrl_num));
314 
315 	/* Compute timing parameters */
316 	pdimm->trcd_ps = spd->trcd * 250;
317 	pdimm->trp_ps = spd->trp * 250;
318 	pdimm->tras_ps = spd->tras * 1000;
319 
320 	pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
321 	pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
322 	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
323 
324 	pdimm->trrd_ps = spd->trrd * 250;
325 	pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
326 
327 	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
328 
329 	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
330 	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
331 	pdimm->tds_ps
332 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
333 	pdimm->tdh_ps
334 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
335 
336 	pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2);	/* By the book. */
337 	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
338 	pdimm->tqhs_ps = spd->tqhs * 10;
339 
340 	return 0;
341 }
342