1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. 9 * Based on code from spd_sdram.c 10 * Author: James Yang [at freescale.com] 11 */ 12 13 #include <common.h> 14 #include <fsl_ddr_sdram.h> 15 16 #include <fsl_ddr.h> 17 #include <fsl_immap.h> 18 #include <asm/io.h> 19 20 unsigned int picos_to_mclk(unsigned int picos); 21 22 /* 23 * Determine Rtt value. 24 * 25 * This should likely be either board or controller specific. 26 * 27 * Rtt(nominal) - DDR2: 28 * 0 = Rtt disabled 29 * 1 = 75 ohm 30 * 2 = 150 ohm 31 * 3 = 50 ohm 32 * Rtt(nominal) - DDR3: 33 * 0 = Rtt disabled 34 * 1 = 60 ohm 35 * 2 = 120 ohm 36 * 3 = 40 ohm 37 * 4 = 20 ohm 38 * 5 = 30 ohm 39 * 40 * FIXME: Apparently 8641 needs a value of 2 41 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 42 * 43 * FIXME: There was some effort down this line earlier: 44 * 45 * unsigned int i; 46 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { 47 * if (popts->dimmslot[i].num_valid_cs 48 * && (popts->cs_local_opts[2*i].odt_rd_cfg 49 * || popts->cs_local_opts[2*i].odt_wr_cfg)) { 50 * rtt = 2; 51 * break; 52 * } 53 * } 54 */ 55 static inline int fsl_ddr_get_rtt(void) 56 { 57 int rtt; 58 59 #if defined(CONFIG_SYS_FSL_DDR1) 60 rtt = 0; 61 #elif defined(CONFIG_SYS_FSL_DDR2) 62 rtt = 3; 63 #else 64 rtt = 0; 65 #endif 66 67 return rtt; 68 } 69 70 #ifdef CONFIG_SYS_FSL_DDR4 71 /* 72 * compute CAS write latency according to DDR4 spec 73 * CWL = 9 for <= 1600MT/s 74 * 10 for <= 1866MT/s 75 * 11 for <= 2133MT/s 76 * 12 for <= 2400MT/s 77 * 14 for <= 2667MT/s 78 * 16 for <= 2933MT/s 79 * 18 for higher 80 */ 81 static inline unsigned int compute_cas_write_latency(void) 82 { 83 unsigned int cwl; 84 const unsigned int mclk_ps = get_memory_clk_period_ps(); 85 if (mclk_ps >= 1250) 86 cwl = 9; 87 else if (mclk_ps >= 1070) 88 cwl = 10; 89 else if (mclk_ps >= 935) 90 cwl = 11; 91 else if (mclk_ps >= 833) 92 cwl = 12; 93 else if (mclk_ps >= 750) 94 cwl = 14; 95 else if (mclk_ps >= 681) 96 cwl = 16; 97 else 98 cwl = 18; 99 100 return cwl; 101 } 102 #else 103 /* 104 * compute the CAS write latency according to DDR3 spec 105 * CWL = 5 if tCK >= 2.5ns 106 * 6 if 2.5ns > tCK >= 1.875ns 107 * 7 if 1.875ns > tCK >= 1.5ns 108 * 8 if 1.5ns > tCK >= 1.25ns 109 * 9 if 1.25ns > tCK >= 1.07ns 110 * 10 if 1.07ns > tCK >= 0.935ns 111 * 11 if 0.935ns > tCK >= 0.833ns 112 * 12 if 0.833ns > tCK >= 0.75ns 113 */ 114 static inline unsigned int compute_cas_write_latency(void) 115 { 116 unsigned int cwl; 117 const unsigned int mclk_ps = get_memory_clk_period_ps(); 118 119 if (mclk_ps >= 2500) 120 cwl = 5; 121 else if (mclk_ps >= 1875) 122 cwl = 6; 123 else if (mclk_ps >= 1500) 124 cwl = 7; 125 else if (mclk_ps >= 1250) 126 cwl = 8; 127 else if (mclk_ps >= 1070) 128 cwl = 9; 129 else if (mclk_ps >= 935) 130 cwl = 10; 131 else if (mclk_ps >= 833) 132 cwl = 11; 133 else if (mclk_ps >= 750) 134 cwl = 12; 135 else { 136 cwl = 12; 137 printf("Warning: CWL is out of range\n"); 138 } 139 return cwl; 140 } 141 #endif 142 143 /* Chip Select Configuration (CSn_CONFIG) */ 144 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, 145 const memctl_options_t *popts, 146 const dimm_params_t *dimm_params) 147 { 148 unsigned int cs_n_en = 0; /* Chip Select enable */ 149 unsigned int intlv_en = 0; /* Memory controller interleave enable */ 150 unsigned int intlv_ctl = 0; /* Interleaving control */ 151 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ 152 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ 153 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ 154 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ 155 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ 156 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ 157 int go_config = 0; 158 #ifdef CONFIG_SYS_FSL_DDR4 159 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */ 160 #else 161 unsigned int n_banks_per_sdram_device; 162 #endif 163 164 /* Compute CS_CONFIG only for existing ranks of each DIMM. */ 165 switch (i) { 166 case 0: 167 if (dimm_params[dimm_number].n_ranks > 0) { 168 go_config = 1; 169 /* These fields only available in CS0_CONFIG */ 170 if (!popts->memctl_interleaving) 171 break; 172 switch (popts->memctl_interleaving_mode) { 173 case FSL_DDR_256B_INTERLEAVING: 174 case FSL_DDR_CACHE_LINE_INTERLEAVING: 175 case FSL_DDR_PAGE_INTERLEAVING: 176 case FSL_DDR_BANK_INTERLEAVING: 177 case FSL_DDR_SUPERBANK_INTERLEAVING: 178 intlv_en = popts->memctl_interleaving; 179 intlv_ctl = popts->memctl_interleaving_mode; 180 break; 181 default: 182 break; 183 } 184 } 185 break; 186 case 1: 187 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ 188 (dimm_number == 1 && dimm_params[1].n_ranks > 0)) 189 go_config = 1; 190 break; 191 case 2: 192 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ 193 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) 194 go_config = 1; 195 break; 196 case 3: 197 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ 198 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \ 199 (dimm_number == 3 && dimm_params[3].n_ranks > 0)) 200 go_config = 1; 201 break; 202 default: 203 break; 204 } 205 if (go_config) { 206 cs_n_en = 1; 207 ap_n_en = popts->cs_local_opts[i].auto_precharge; 208 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; 209 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; 210 #ifdef CONFIG_SYS_FSL_DDR4 211 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits; 212 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits; 213 #else 214 n_banks_per_sdram_device 215 = dimm_params[dimm_number].n_banks_per_sdram_device; 216 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; 217 #endif 218 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; 219 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; 220 } 221 ddr->cs[i].config = (0 222 | ((cs_n_en & 0x1) << 31) 223 | ((intlv_en & 0x3) << 29) 224 | ((intlv_ctl & 0xf) << 24) 225 | ((ap_n_en & 0x1) << 23) 226 227 /* XXX: some implementation only have 1 bit starting at left */ 228 | ((odt_rd_cfg & 0x7) << 20) 229 230 /* XXX: Some implementation only have 1 bit starting at left */ 231 | ((odt_wr_cfg & 0x7) << 16) 232 233 | ((ba_bits_cs_n & 0x3) << 14) 234 | ((row_bits_cs_n & 0x7) << 8) 235 #ifdef CONFIG_SYS_FSL_DDR4 236 | ((bg_bits_cs_n & 0x3) << 4) 237 #endif 238 | ((col_bits_cs_n & 0x7) << 0) 239 ); 240 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); 241 } 242 243 /* Chip Select Configuration 2 (CSn_CONFIG_2) */ 244 /* FIXME: 8572 */ 245 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) 246 { 247 unsigned int pasr_cfg = 0; /* Partial array self refresh config */ 248 249 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); 250 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); 251 } 252 253 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ 254 255 #if !defined(CONFIG_SYS_FSL_DDR1) 256 /* 257 * Check DIMM configuration, return 2 if quad-rank or two dual-rank 258 * Return 1 if other two slots configuration. Return 0 if single slot. 259 */ 260 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) 261 { 262 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1 263 if (dimm_params[0].n_ranks == 4) 264 return 2; 265 #endif 266 267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2 268 if ((dimm_params[0].n_ranks == 2) && 269 (dimm_params[1].n_ranks == 2)) 270 return 2; 271 272 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 273 if (dimm_params[0].n_ranks == 4) 274 return 2; 275 #endif 276 277 if ((dimm_params[0].n_ranks != 0) && 278 (dimm_params[2].n_ranks != 0)) 279 return 1; 280 #endif 281 return 0; 282 } 283 284 /* 285 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) 286 * 287 * Avoid writing for DDR I. The new PQ38 DDR controller 288 * dreams up non-zero default values to be backwards compatible. 289 */ 290 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, 291 const memctl_options_t *popts, 292 const dimm_params_t *dimm_params) 293 { 294 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ 295 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ 296 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ 297 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ 298 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ 299 300 /* Active powerdown exit timing (tXARD and tXARDS). */ 301 unsigned char act_pd_exit_mclk; 302 /* Precharge powerdown exit timing (tXP). */ 303 unsigned char pre_pd_exit_mclk; 304 /* ODT powerdown exit timing (tAXPD). */ 305 unsigned char taxpd_mclk = 0; 306 /* Mode register set cycle time (tMRD). */ 307 unsigned char tmrd_mclk; 308 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3) 309 const unsigned int mclk_ps = get_memory_clk_period_ps(); 310 #endif 311 312 #ifdef CONFIG_SYS_FSL_DDR4 313 /* tXP=max(4nCK, 6ns) */ 314 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */ 315 trwt_mclk = 2; 316 twrt_mclk = 1; 317 act_pd_exit_mclk = picos_to_mclk(txp); 318 pre_pd_exit_mclk = act_pd_exit_mclk; 319 /* 320 * MRS_CYC = max(tMRD, tMOD) 321 * tMRD = 8nCK, tMOD = max(24nCK, 15ns) 322 */ 323 tmrd_mclk = max(24U, picos_to_mclk(15000)); 324 #elif defined(CONFIG_SYS_FSL_DDR3) 325 unsigned int data_rate = get_ddr_freq(0); 326 int txp; 327 int odt_overlap; 328 /* 329 * (tXARD and tXARDS). Empirical? 330 * The DDR3 spec has not tXARD, 331 * we use the tXP instead of it. 332 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066 333 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133 334 * spec has not the tAXPD, we use 335 * tAXPD=1, need design to confirm. 336 */ 337 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000)); 338 339 tmrd_mclk = 4; 340 /* set the turnaround time */ 341 342 /* 343 * for single quad-rank DIMM and two-slot DIMMs 344 * to avoid ODT overlap 345 */ 346 odt_overlap = avoid_odt_overlap(dimm_params); 347 switch (odt_overlap) { 348 case 2: 349 twwt_mclk = 2; 350 trrt_mclk = 1; 351 break; 352 case 1: 353 twwt_mclk = 1; 354 trrt_mclk = 0; 355 break; 356 default: 357 break; 358 } 359 360 /* for faster clock, need more time for data setup */ 361 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; 362 363 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) 364 twrt_mclk = 1; 365 366 if (popts->dynamic_power == 0) { /* powerdown is not used */ 367 act_pd_exit_mclk = 1; 368 pre_pd_exit_mclk = 1; 369 taxpd_mclk = 1; 370 } else { 371 /* act_pd_exit_mclk = tXARD, see above */ 372 act_pd_exit_mclk = picos_to_mclk(txp); 373 /* Mode register MR0[A12] is '1' - fast exit */ 374 pre_pd_exit_mclk = act_pd_exit_mclk; 375 taxpd_mclk = 1; 376 } 377 #else /* CONFIG_SYS_FSL_DDR2 */ 378 /* 379 * (tXARD and tXARDS). Empirical? 380 * tXARD = 2 for DDR2 381 * tXP=2 382 * tAXPD=8 383 */ 384 act_pd_exit_mclk = 2; 385 pre_pd_exit_mclk = 2; 386 taxpd_mclk = 8; 387 tmrd_mclk = 2; 388 #endif 389 390 if (popts->trwt_override) 391 trwt_mclk = popts->trwt; 392 393 ddr->timing_cfg_0 = (0 394 | ((trwt_mclk & 0x3) << 30) /* RWT */ 395 | ((twrt_mclk & 0x3) << 28) /* WRT */ 396 | ((trrt_mclk & 0x3) << 26) /* RRT */ 397 | ((twwt_mclk & 0x3) << 24) /* WWT */ 398 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */ 399 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ 400 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ 401 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */ 402 ); 403 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); 404 } 405 #endif /* !defined(CONFIG_SYS_FSL_DDR1) */ 406 407 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ 408 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, 409 const memctl_options_t *popts, 410 const common_timing_params_t *common_dimm, 411 unsigned int cas_latency, 412 unsigned int additive_latency) 413 { 414 /* Extended precharge to activate interval (tRP) */ 415 unsigned int ext_pretoact = 0; 416 /* Extended Activate to precharge interval (tRAS) */ 417 unsigned int ext_acttopre = 0; 418 /* Extended activate to read/write interval (tRCD) */ 419 unsigned int ext_acttorw = 0; 420 /* Extended refresh recovery time (tRFC) */ 421 unsigned int ext_refrec; 422 /* Extended MCAS latency from READ cmd */ 423 unsigned int ext_caslat = 0; 424 /* Extended additive latency */ 425 unsigned int ext_add_lat = 0; 426 /* Extended last data to precharge interval (tWR) */ 427 unsigned int ext_wrrec = 0; 428 /* Control Adjust */ 429 unsigned int cntl_adj = 0; 430 431 ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4; 432 ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4; 433 ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4; 434 ext_caslat = (2 * cas_latency - 1) >> 4; 435 ext_add_lat = additive_latency >> 4; 436 #ifdef CONFIG_SYS_FSL_DDR4 437 ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4; 438 #else 439 ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4; 440 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ 441 #endif 442 ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) + 443 (popts->otf_burst_chop_en ? 2 : 0)) >> 4; 444 445 ddr->timing_cfg_3 = (0 446 | ((ext_pretoact & 0x1) << 28) 447 | ((ext_acttopre & 0x3) << 24) 448 | ((ext_acttorw & 0x1) << 22) 449 | ((ext_refrec & 0x1F) << 16) 450 | ((ext_caslat & 0x3) << 12) 451 | ((ext_add_lat & 0x1) << 10) 452 | ((ext_wrrec & 0x1) << 8) 453 | ((cntl_adj & 0x7) << 0) 454 ); 455 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); 456 } 457 458 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ 459 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, 460 const memctl_options_t *popts, 461 const common_timing_params_t *common_dimm, 462 unsigned int cas_latency) 463 { 464 /* Precharge-to-activate interval (tRP) */ 465 unsigned char pretoact_mclk; 466 /* Activate to precharge interval (tRAS) */ 467 unsigned char acttopre_mclk; 468 /* Activate to read/write interval (tRCD) */ 469 unsigned char acttorw_mclk; 470 /* CASLAT */ 471 unsigned char caslat_ctrl; 472 /* Refresh recovery time (tRFC) ; trfc_low */ 473 unsigned char refrec_ctrl; 474 /* Last data to precharge minimum interval (tWR) */ 475 unsigned char wrrec_mclk; 476 /* Activate-to-activate interval (tRRD) */ 477 unsigned char acttoact_mclk; 478 /* Last write data pair to read command issue interval (tWTR) */ 479 unsigned char wrtord_mclk; 480 #ifdef CONFIG_SYS_FSL_DDR4 481 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */ 482 static const u8 wrrec_table[] = { 483 10, 10, 10, 10, 10, 484 10, 10, 10, 10, 10, 485 12, 12, 14, 14, 16, 486 16, 18, 18, 20, 20, 487 24, 24, 24, 24}; 488 #else 489 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ 490 static const u8 wrrec_table[] = { 491 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; 492 #endif 493 494 pretoact_mclk = picos_to_mclk(common_dimm->trp_ps); 495 acttopre_mclk = picos_to_mclk(common_dimm->tras_ps); 496 acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps); 497 498 /* 499 * Translate CAS Latency to a DDR controller field value: 500 * 501 * CAS Lat DDR I DDR II Ctrl 502 * Clocks SPD Bit SPD Bit Value 503 * ------- ------- ------- ----- 504 * 1.0 0 0001 505 * 1.5 1 0010 506 * 2.0 2 2 0011 507 * 2.5 3 0100 508 * 3.0 4 3 0101 509 * 3.5 5 0110 510 * 4.0 4 0111 511 * 4.5 1000 512 * 5.0 5 1001 513 */ 514 #if defined(CONFIG_SYS_FSL_DDR1) 515 caslat_ctrl = (cas_latency + 1) & 0x07; 516 #elif defined(CONFIG_SYS_FSL_DDR2) 517 caslat_ctrl = 2 * cas_latency - 1; 518 #else 519 /* 520 * if the CAS latency more than 8 cycle, 521 * we need set extend bit for it at 522 * TIMING_CFG_3[EXT_CASLAT] 523 */ 524 if (fsl_ddr_get_version() <= 0x40400) 525 caslat_ctrl = 2 * cas_latency - 1; 526 else 527 caslat_ctrl = (cas_latency - 1) << 1; 528 #endif 529 530 #ifdef CONFIG_SYS_FSL_DDR4 531 refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8; 532 wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); 533 acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U); 534 wrtord_mclk = max(2U, picos_to_mclk(2500)); 535 if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) 536 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); 537 else 538 wrrec_mclk = wrrec_table[wrrec_mclk - 1]; 539 #else 540 refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8; 541 wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); 542 acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); 543 wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); 544 if ((wrrec_mclk < 1) || (wrrec_mclk > 16)) 545 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); 546 else 547 wrrec_mclk = wrrec_table[wrrec_mclk - 1]; 548 #endif 549 if (popts->otf_burst_chop_en) 550 wrrec_mclk += 2; 551 552 /* 553 * JEDEC has min requirement for tRRD 554 */ 555 #if defined(CONFIG_SYS_FSL_DDR3) 556 if (acttoact_mclk < 4) 557 acttoact_mclk = 4; 558 #endif 559 /* 560 * JEDEC has some min requirements for tWTR 561 */ 562 #if defined(CONFIG_SYS_FSL_DDR2) 563 if (wrtord_mclk < 2) 564 wrtord_mclk = 2; 565 #elif defined(CONFIG_SYS_FSL_DDR3) 566 if (wrtord_mclk < 4) 567 wrtord_mclk = 4; 568 #endif 569 if (popts->otf_burst_chop_en) 570 wrtord_mclk += 2; 571 572 ddr->timing_cfg_1 = (0 573 | ((pretoact_mclk & 0x0F) << 28) 574 | ((acttopre_mclk & 0x0F) << 24) 575 | ((acttorw_mclk & 0xF) << 20) 576 | ((caslat_ctrl & 0xF) << 16) 577 | ((refrec_ctrl & 0xF) << 12) 578 | ((wrrec_mclk & 0x0F) << 8) 579 | ((acttoact_mclk & 0x0F) << 4) 580 | ((wrtord_mclk & 0x0F) << 0) 581 ); 582 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); 583 } 584 585 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ 586 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, 587 const memctl_options_t *popts, 588 const common_timing_params_t *common_dimm, 589 unsigned int cas_latency, 590 unsigned int additive_latency) 591 { 592 /* Additive latency */ 593 unsigned char add_lat_mclk; 594 /* CAS-to-preamble override */ 595 unsigned short cpo; 596 /* Write latency */ 597 unsigned char wr_lat; 598 /* Read to precharge (tRTP) */ 599 unsigned char rd_to_pre; 600 /* Write command to write data strobe timing adjustment */ 601 unsigned char wr_data_delay; 602 /* Minimum CKE pulse width (tCKE) */ 603 unsigned char cke_pls; 604 /* Window for four activates (tFAW) */ 605 unsigned short four_act; 606 #ifdef CONFIG_SYS_FSL_DDR3 607 const unsigned int mclk_ps = get_memory_clk_period_ps(); 608 #endif 609 610 /* FIXME add check that this must be less than acttorw_mclk */ 611 add_lat_mclk = additive_latency; 612 cpo = popts->cpo_override; 613 614 #if defined(CONFIG_SYS_FSL_DDR1) 615 /* 616 * This is a lie. It should really be 1, but if it is 617 * set to 1, bits overlap into the old controller's 618 * otherwise unused ACSM field. If we leave it 0, then 619 * the HW will magically treat it as 1 for DDR 1. Oh Yea. 620 */ 621 wr_lat = 0; 622 #elif defined(CONFIG_SYS_FSL_DDR2) 623 wr_lat = cas_latency - 1; 624 #else 625 wr_lat = compute_cas_write_latency(); 626 #endif 627 628 #ifdef CONFIG_SYS_FSL_DDR4 629 rd_to_pre = picos_to_mclk(7500); 630 #else 631 rd_to_pre = picos_to_mclk(common_dimm->trtp_ps); 632 #endif 633 /* 634 * JEDEC has some min requirements for tRTP 635 */ 636 #if defined(CONFIG_SYS_FSL_DDR2) 637 if (rd_to_pre < 2) 638 rd_to_pre = 2; 639 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 640 if (rd_to_pre < 4) 641 rd_to_pre = 4; 642 #endif 643 if (popts->otf_burst_chop_en) 644 rd_to_pre += 2; /* according to UM */ 645 646 wr_data_delay = popts->write_data_delay; 647 #ifdef CONFIG_SYS_FSL_DDR4 648 cpo = 0; 649 cke_pls = max(3U, picos_to_mclk(5000)); 650 #elif defined(CONFIG_SYS_FSL_DDR3) 651 /* 652 * cke pulse = max(3nCK, 7.5ns) for DDR3-800 653 * max(3nCK, 5.625ns) for DDR3-1066, 1333 654 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133 655 */ 656 cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 : 657 (mclk_ps > 1245 ? 5625 : 5000))); 658 #else 659 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR; 660 #endif 661 four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps); 662 663 ddr->timing_cfg_2 = (0 664 | ((add_lat_mclk & 0xf) << 28) 665 | ((cpo & 0x1f) << 23) 666 | ((wr_lat & 0xf) << 19) 667 | ((wr_lat & 0x10) << 14) 668 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) 669 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) 670 | ((cke_pls & 0x7) << 6) 671 | ((four_act & 0x3f) << 0) 672 ); 673 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); 674 } 675 676 /* DDR SDRAM Register Control Word */ 677 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, 678 const memctl_options_t *popts, 679 const common_timing_params_t *common_dimm) 680 { 681 if (common_dimm->all_dimms_registered && 682 !common_dimm->all_dimms_unbuffered) { 683 if (popts->rcw_override) { 684 ddr->ddr_sdram_rcw_1 = popts->rcw_1; 685 ddr->ddr_sdram_rcw_2 = popts->rcw_2; 686 } else { 687 ddr->ddr_sdram_rcw_1 = 688 common_dimm->rcw[0] << 28 | \ 689 common_dimm->rcw[1] << 24 | \ 690 common_dimm->rcw[2] << 20 | \ 691 common_dimm->rcw[3] << 16 | \ 692 common_dimm->rcw[4] << 12 | \ 693 common_dimm->rcw[5] << 8 | \ 694 common_dimm->rcw[6] << 4 | \ 695 common_dimm->rcw[7]; 696 ddr->ddr_sdram_rcw_2 = 697 common_dimm->rcw[8] << 28 | \ 698 common_dimm->rcw[9] << 24 | \ 699 common_dimm->rcw[10] << 20 | \ 700 common_dimm->rcw[11] << 16 | \ 701 common_dimm->rcw[12] << 12 | \ 702 common_dimm->rcw[13] << 8 | \ 703 common_dimm->rcw[14] << 4 | \ 704 common_dimm->rcw[15]; 705 } 706 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); 707 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); 708 } 709 } 710 711 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ 712 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, 713 const memctl_options_t *popts, 714 const common_timing_params_t *common_dimm) 715 { 716 unsigned int mem_en; /* DDR SDRAM interface logic enable */ 717 unsigned int sren; /* Self refresh enable (during sleep) */ 718 unsigned int ecc_en; /* ECC enable. */ 719 unsigned int rd_en; /* Registered DIMM enable */ 720 unsigned int sdram_type; /* Type of SDRAM */ 721 unsigned int dyn_pwr; /* Dynamic power management mode */ 722 unsigned int dbw; /* DRAM dta bus width */ 723 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ 724 unsigned int ncap = 0; /* Non-concurrent auto-precharge */ 725 unsigned int threet_en; /* Enable 3T timing */ 726 unsigned int twot_en; /* Enable 2T timing */ 727 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ 728 unsigned int x32_en = 0; /* x32 enable */ 729 unsigned int pchb8 = 0; /* precharge bit 8 enable */ 730 unsigned int hse; /* Global half strength override */ 731 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */ 732 unsigned int mem_halt = 0; /* memory controller halt */ 733 unsigned int bi = 0; /* Bypass initialization */ 734 735 mem_en = 1; 736 sren = popts->self_refresh_in_sleep; 737 if (common_dimm->all_dimms_ecc_capable) { 738 /* Allow setting of ECC only if all DIMMs are ECC. */ 739 ecc_en = popts->ecc_mode; 740 } else { 741 ecc_en = 0; 742 } 743 744 if (common_dimm->all_dimms_registered && 745 !common_dimm->all_dimms_unbuffered) { 746 rd_en = 1; 747 twot_en = 0; 748 } else { 749 rd_en = 0; 750 twot_en = popts->twot_en; 751 } 752 753 sdram_type = CONFIG_FSL_SDRAM_TYPE; 754 755 dyn_pwr = popts->dynamic_power; 756 dbw = popts->data_bus_width; 757 /* 8-beat burst enable DDR-III case 758 * we must clear it when use the on-the-fly mode, 759 * must set it when use the 32-bits bus mode. 760 */ 761 if ((sdram_type == SDRAM_TYPE_DDR3) || 762 (sdram_type == SDRAM_TYPE_DDR4)) { 763 if (popts->burst_length == DDR_BL8) 764 eight_be = 1; 765 if (popts->burst_length == DDR_OTF) 766 eight_be = 0; 767 if (dbw == 0x1) 768 eight_be = 1; 769 } 770 771 threet_en = popts->threet_en; 772 ba_intlv_ctl = popts->ba_intlv_ctl; 773 hse = popts->half_strength_driver_enable; 774 775 /* set when ddr bus width < 64 */ 776 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0; 777 778 ddr->ddr_sdram_cfg = (0 779 | ((mem_en & 0x1) << 31) 780 | ((sren & 0x1) << 30) 781 | ((ecc_en & 0x1) << 29) 782 | ((rd_en & 0x1) << 28) 783 | ((sdram_type & 0x7) << 24) 784 | ((dyn_pwr & 0x1) << 21) 785 | ((dbw & 0x3) << 19) 786 | ((eight_be & 0x1) << 18) 787 | ((ncap & 0x1) << 17) 788 | ((threet_en & 0x1) << 16) 789 | ((twot_en & 0x1) << 15) 790 | ((ba_intlv_ctl & 0x7F) << 8) 791 | ((x32_en & 0x1) << 5) 792 | ((pchb8 & 0x1) << 4) 793 | ((hse & 0x1) << 3) 794 | ((acc_ecc_en & 0x1) << 2) 795 | ((mem_halt & 0x1) << 1) 796 | ((bi & 0x1) << 0) 797 ); 798 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); 799 } 800 801 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ 802 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, 803 const memctl_options_t *popts, 804 const unsigned int unq_mrs_en) 805 { 806 unsigned int frc_sr = 0; /* Force self refresh */ 807 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ 808 unsigned int odt_cfg = 0; /* ODT configuration */ 809 unsigned int num_pr; /* Number of posted refreshes */ 810 unsigned int slow = 0; /* DDR will be run less than 1250 */ 811 unsigned int x4_en = 0; /* x4 DRAM enable */ 812 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ 813 unsigned int ap_en; /* Address Parity Enable */ 814 unsigned int d_init; /* DRAM data initialization */ 815 unsigned int rcw_en = 0; /* Register Control Word Enable */ 816 unsigned int md_en = 0; /* Mirrored DIMM Enable */ 817 unsigned int qd_en = 0; /* quad-rank DIMM Enable */ 818 int i; 819 #ifndef CONFIG_SYS_FSL_DDR4 820 unsigned int dll_rst_dis = 1; /* DLL reset disable */ 821 unsigned int dqs_cfg; /* DQS configuration */ 822 823 dqs_cfg = popts->dqs_config; 824 #endif 825 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 826 if (popts->cs_local_opts[i].odt_rd_cfg 827 || popts->cs_local_opts[i].odt_wr_cfg) { 828 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; 829 break; 830 } 831 } 832 833 num_pr = 1; /* Make this configurable */ 834 835 /* 836 * 8572 manual says 837 * {TIMING_CFG_1[PRETOACT] 838 * + [DDR_SDRAM_CFG_2[NUM_PR] 839 * * ({EXT_REFREC || REFREC} + 8 + 2)]} 840 * << DDR_SDRAM_INTERVAL[REFINT] 841 */ 842 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 843 obc_cfg = popts->otf_burst_chop_en; 844 #else 845 obc_cfg = 0; 846 #endif 847 848 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) 849 slow = get_ddr_freq(0) < 1249000000; 850 #endif 851 852 if (popts->registered_dimm_en) { 853 rcw_en = 1; 854 ap_en = popts->ap_en; 855 } else { 856 ap_en = 0; 857 } 858 859 x4_en = popts->x4_en ? 1 : 0; 860 861 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 862 /* Use the DDR controller to auto initialize memory. */ 863 d_init = popts->ecc_init_using_memctl; 864 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; 865 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); 866 #else 867 /* Memory will be initialized via DMA, or not at all. */ 868 d_init = 0; 869 #endif 870 871 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 872 md_en = popts->mirrored_dimm; 873 #endif 874 qd_en = popts->quad_rank_present ? 1 : 0; 875 ddr->ddr_sdram_cfg_2 = (0 876 | ((frc_sr & 0x1) << 31) 877 | ((sr_ie & 0x1) << 30) 878 #ifndef CONFIG_SYS_FSL_DDR4 879 | ((dll_rst_dis & 0x1) << 29) 880 | ((dqs_cfg & 0x3) << 26) 881 #endif 882 | ((odt_cfg & 0x3) << 21) 883 | ((num_pr & 0xf) << 12) 884 | ((slow & 1) << 11) 885 | (x4_en << 10) 886 | (qd_en << 9) 887 | (unq_mrs_en << 8) 888 | ((obc_cfg & 0x1) << 6) 889 | ((ap_en & 0x1) << 5) 890 | ((d_init & 0x1) << 4) 891 | ((rcw_en & 0x1) << 2) 892 | ((md_en & 0x1) << 0) 893 ); 894 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); 895 } 896 897 #ifdef CONFIG_SYS_FSL_DDR4 898 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ 899 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, 900 const memctl_options_t *popts, 901 const common_timing_params_t *common_dimm, 902 const unsigned int unq_mrs_en) 903 { 904 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ 905 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ 906 int i; 907 unsigned int wr_crc = 0; /* Disable */ 908 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ 909 unsigned int srt = 0; /* self-refresh temerature, normal range */ 910 unsigned int cwl = compute_cas_write_latency() - 9; 911 unsigned int mpr = 0; /* serial */ 912 unsigned int wc_lat; 913 const unsigned int mclk_ps = get_memory_clk_period_ps(); 914 915 if (popts->rtt_override) 916 rtt_wr = popts->rtt_wr_override_value; 917 else 918 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; 919 920 if (common_dimm->extended_op_srt) 921 srt = common_dimm->extended_op_srt; 922 923 esdmode2 = (0 924 | ((wr_crc & 0x1) << 12) 925 | ((rtt_wr & 0x3) << 9) 926 | ((srt & 0x3) << 6) 927 | ((cwl & 0x7) << 3)); 928 929 if (mclk_ps >= 1250) 930 wc_lat = 0; 931 else if (mclk_ps >= 833) 932 wc_lat = 1; 933 else 934 wc_lat = 2; 935 936 esdmode3 = (0 937 | ((mpr & 0x3) << 11) 938 | ((wc_lat & 0x3) << 9)); 939 940 ddr->ddr_sdram_mode_2 = (0 941 | ((esdmode2 & 0xFFFF) << 16) 942 | ((esdmode3 & 0xFFFF) << 0) 943 ); 944 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); 945 946 if (unq_mrs_en) { /* unique mode registers are supported */ 947 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 948 if (popts->rtt_override) 949 rtt_wr = popts->rtt_wr_override_value; 950 else 951 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; 952 953 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ 954 esdmode2 |= (rtt_wr & 0x3) << 9; 955 switch (i) { 956 case 1: 957 ddr->ddr_sdram_mode_4 = (0 958 | ((esdmode2 & 0xFFFF) << 16) 959 | ((esdmode3 & 0xFFFF) << 0) 960 ); 961 break; 962 case 2: 963 ddr->ddr_sdram_mode_6 = (0 964 | ((esdmode2 & 0xFFFF) << 16) 965 | ((esdmode3 & 0xFFFF) << 0) 966 ); 967 break; 968 case 3: 969 ddr->ddr_sdram_mode_8 = (0 970 | ((esdmode2 & 0xFFFF) << 16) 971 | ((esdmode3 & 0xFFFF) << 0) 972 ); 973 break; 974 } 975 } 976 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", 977 ddr->ddr_sdram_mode_4); 978 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", 979 ddr->ddr_sdram_mode_6); 980 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", 981 ddr->ddr_sdram_mode_8); 982 } 983 } 984 #elif defined(CONFIG_SYS_FSL_DDR3) 985 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ 986 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, 987 const memctl_options_t *popts, 988 const common_timing_params_t *common_dimm, 989 const unsigned int unq_mrs_en) 990 { 991 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ 992 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ 993 int i; 994 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ 995 unsigned int srt = 0; /* self-refresh temerature, normal range */ 996 unsigned int asr = 0; /* auto self-refresh disable */ 997 unsigned int cwl = compute_cas_write_latency() - 5; 998 unsigned int pasr = 0; /* partial array self refresh disable */ 999 1000 if (popts->rtt_override) 1001 rtt_wr = popts->rtt_wr_override_value; 1002 else 1003 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; 1004 1005 if (common_dimm->extended_op_srt) 1006 srt = common_dimm->extended_op_srt; 1007 1008 esdmode2 = (0 1009 | ((rtt_wr & 0x3) << 9) 1010 | ((srt & 0x1) << 7) 1011 | ((asr & 0x1) << 6) 1012 | ((cwl & 0x7) << 3) 1013 | ((pasr & 0x7) << 0)); 1014 ddr->ddr_sdram_mode_2 = (0 1015 | ((esdmode2 & 0xFFFF) << 16) 1016 | ((esdmode3 & 0xFFFF) << 0) 1017 ); 1018 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); 1019 1020 if (unq_mrs_en) { /* unique mode registers are supported */ 1021 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1022 if (popts->rtt_override) 1023 rtt_wr = popts->rtt_wr_override_value; 1024 else 1025 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; 1026 1027 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ 1028 esdmode2 |= (rtt_wr & 0x3) << 9; 1029 switch (i) { 1030 case 1: 1031 ddr->ddr_sdram_mode_4 = (0 1032 | ((esdmode2 & 0xFFFF) << 16) 1033 | ((esdmode3 & 0xFFFF) << 0) 1034 ); 1035 break; 1036 case 2: 1037 ddr->ddr_sdram_mode_6 = (0 1038 | ((esdmode2 & 0xFFFF) << 16) 1039 | ((esdmode3 & 0xFFFF) << 0) 1040 ); 1041 break; 1042 case 3: 1043 ddr->ddr_sdram_mode_8 = (0 1044 | ((esdmode2 & 0xFFFF) << 16) 1045 | ((esdmode3 & 0xFFFF) << 0) 1046 ); 1047 break; 1048 } 1049 } 1050 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", 1051 ddr->ddr_sdram_mode_4); 1052 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", 1053 ddr->ddr_sdram_mode_6); 1054 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", 1055 ddr->ddr_sdram_mode_8); 1056 } 1057 } 1058 1059 #else /* for DDR2 and DDR1 */ 1060 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ 1061 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, 1062 const memctl_options_t *popts, 1063 const common_timing_params_t *common_dimm, 1064 const unsigned int unq_mrs_en) 1065 { 1066 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ 1067 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ 1068 1069 ddr->ddr_sdram_mode_2 = (0 1070 | ((esdmode2 & 0xFFFF) << 16) 1071 | ((esdmode3 & 0xFFFF) << 0) 1072 ); 1073 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); 1074 } 1075 #endif 1076 1077 #ifdef CONFIG_SYS_FSL_DDR4 1078 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */ 1079 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, 1080 const memctl_options_t *popts, 1081 const common_timing_params_t *common_dimm, 1082 const unsigned int unq_mrs_en) 1083 { 1084 int i; 1085 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */ 1086 unsigned short esdmode5; /* Extended SDRAM mode 5 */ 1087 1088 esdmode5 = 0x00000400; /* Data mask enabled */ 1089 1090 ddr->ddr_sdram_mode_9 = (0 1091 | ((esdmode4 & 0xffff) << 16) 1092 | ((esdmode5 & 0xffff) << 0) 1093 ); 1094 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9); 1095 if (unq_mrs_en) { /* unique mode registers are supported */ 1096 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1097 switch (i) { 1098 case 1: 1099 ddr->ddr_sdram_mode_11 = (0 1100 | ((esdmode4 & 0xFFFF) << 16) 1101 | ((esdmode5 & 0xFFFF) << 0) 1102 ); 1103 break; 1104 case 2: 1105 ddr->ddr_sdram_mode_13 = (0 1106 | ((esdmode4 & 0xFFFF) << 16) 1107 | ((esdmode5 & 0xFFFF) << 0) 1108 ); 1109 break; 1110 case 3: 1111 ddr->ddr_sdram_mode_15 = (0 1112 | ((esdmode4 & 0xFFFF) << 16) 1113 | ((esdmode5 & 0xFFFF) << 0) 1114 ); 1115 break; 1116 } 1117 } 1118 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n", 1119 ddr->ddr_sdram_mode_11); 1120 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n", 1121 ddr->ddr_sdram_mode_13); 1122 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n", 1123 ddr->ddr_sdram_mode_15); 1124 } 1125 } 1126 1127 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */ 1128 static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr, 1129 const memctl_options_t *popts, 1130 const common_timing_params_t *common_dimm, 1131 const unsigned int unq_mrs_en) 1132 { 1133 int i; 1134 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */ 1135 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */ 1136 unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps); 1137 1138 esdmode6 = ((tccdl_min - 4) & 0x7) << 10; 1139 1140 ddr->ddr_sdram_mode_10 = (0 1141 | ((esdmode6 & 0xffff) << 16) 1142 | ((esdmode7 & 0xffff) << 0) 1143 ); 1144 debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10); 1145 if (unq_mrs_en) { /* unique mode registers are supported */ 1146 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1147 switch (i) { 1148 case 1: 1149 ddr->ddr_sdram_mode_12 = (0 1150 | ((esdmode6 & 0xFFFF) << 16) 1151 | ((esdmode7 & 0xFFFF) << 0) 1152 ); 1153 break; 1154 case 2: 1155 ddr->ddr_sdram_mode_14 = (0 1156 | ((esdmode6 & 0xFFFF) << 16) 1157 | ((esdmode7 & 0xFFFF) << 0) 1158 ); 1159 break; 1160 case 3: 1161 ddr->ddr_sdram_mode_16 = (0 1162 | ((esdmode6 & 0xFFFF) << 16) 1163 | ((esdmode7 & 0xFFFF) << 0) 1164 ); 1165 break; 1166 } 1167 } 1168 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n", 1169 ddr->ddr_sdram_mode_12); 1170 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n", 1171 ddr->ddr_sdram_mode_14); 1172 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n", 1173 ddr->ddr_sdram_mode_16); 1174 } 1175 } 1176 1177 #endif 1178 1179 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ 1180 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, 1181 const memctl_options_t *popts, 1182 const common_timing_params_t *common_dimm) 1183 { 1184 unsigned int refint; /* Refresh interval */ 1185 unsigned int bstopre; /* Precharge interval */ 1186 1187 refint = picos_to_mclk(common_dimm->refresh_rate_ps); 1188 1189 bstopre = popts->bstopre; 1190 1191 /* refint field used 0x3FFF in earlier controllers */ 1192 ddr->ddr_sdram_interval = (0 1193 | ((refint & 0xFFFF) << 16) 1194 | ((bstopre & 0x3FFF) << 0) 1195 ); 1196 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); 1197 } 1198 1199 #ifdef CONFIG_SYS_FSL_DDR4 1200 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ 1201 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, 1202 const memctl_options_t *popts, 1203 const common_timing_params_t *common_dimm, 1204 unsigned int cas_latency, 1205 unsigned int additive_latency, 1206 const unsigned int unq_mrs_en) 1207 { 1208 int i; 1209 unsigned short esdmode; /* Extended SDRAM mode */ 1210 unsigned short sdmode; /* SDRAM mode */ 1211 1212 /* Mode Register - MR1 */ 1213 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ 1214 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ 1215 unsigned int rtt; 1216 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ 1217 unsigned int al = 0; /* Posted CAS# additive latency (AL) */ 1218 unsigned int dic = 0; /* Output driver impedance, 40ohm */ 1219 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal), 1220 0=Disable (Test/Debug) */ 1221 1222 /* Mode Register - MR0 */ 1223 unsigned int wr = 0; /* Write Recovery */ 1224 unsigned int dll_rst; /* DLL Reset */ 1225 unsigned int mode; /* Normal=0 or Test=1 */ 1226 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ 1227 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ 1228 unsigned int bt; 1229 unsigned int bl; /* BL: Burst Length */ 1230 1231 unsigned int wr_mclk; 1232 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */ 1233 static const u8 wr_table[] = { 1234 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6}; 1235 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */ 1236 static const u8 cas_latency_table[] = { 1237 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 1238 9, 9, 10, 10, 11, 11}; 1239 1240 if (popts->rtt_override) 1241 rtt = popts->rtt_override_value; 1242 else 1243 rtt = popts->cs_local_opts[0].odt_rtt_norm; 1244 1245 if (additive_latency == (cas_latency - 1)) 1246 al = 1; 1247 if (additive_latency == (cas_latency - 2)) 1248 al = 2; 1249 1250 if (popts->quad_rank_present) 1251 dic = 1; /* output driver impedance 240/7 ohm */ 1252 1253 /* 1254 * The esdmode value will also be used for writing 1255 * MR1 during write leveling for DDR3, although the 1256 * bits specifically related to the write leveling 1257 * scheme will be handled automatically by the DDR 1258 * controller. so we set the wrlvl_en = 0 here. 1259 */ 1260 esdmode = (0 1261 | ((qoff & 0x1) << 12) 1262 | ((tdqs_en & 0x1) << 11) 1263 | ((rtt & 0x7) << 8) 1264 | ((wrlvl_en & 0x1) << 7) 1265 | ((al & 0x3) << 3) 1266 | ((dic & 0x3) << 1) /* DIC field is split */ 1267 | ((dll_en & 0x1) << 0) 1268 ); 1269 1270 /* 1271 * DLL control for precharge PD 1272 * 0=slow exit DLL off (tXPDLL) 1273 * 1=fast exit DLL on (tXP) 1274 */ 1275 1276 wr_mclk = picos_to_mclk(common_dimm->twr_ps); 1277 if (wr_mclk <= 24) { 1278 wr = wr_table[wr_mclk - 10]; 1279 } else { 1280 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n", 1281 wr_mclk); 1282 } 1283 1284 dll_rst = 0; /* dll no reset */ 1285 mode = 0; /* normal mode */ 1286 1287 /* look up table to get the cas latency bits */ 1288 if (cas_latency >= 9 && cas_latency <= 24) 1289 caslat = cas_latency_table[cas_latency - 9]; 1290 else 1291 printf("Error: unsupported cas latency for mode register\n"); 1292 1293 bt = 0; /* Nibble sequential */ 1294 1295 switch (popts->burst_length) { 1296 case DDR_BL8: 1297 bl = 0; 1298 break; 1299 case DDR_OTF: 1300 bl = 1; 1301 break; 1302 case DDR_BC4: 1303 bl = 2; 1304 break; 1305 default: 1306 printf("Error: invalid burst length of %u specified. ", 1307 popts->burst_length); 1308 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n"); 1309 bl = 1; 1310 break; 1311 } 1312 1313 sdmode = (0 1314 | ((wr & 0x7) << 9) 1315 | ((dll_rst & 0x1) << 8) 1316 | ((mode & 0x1) << 7) 1317 | (((caslat >> 1) & 0x7) << 4) 1318 | ((bt & 0x1) << 3) 1319 | ((caslat & 1) << 2) 1320 | ((bl & 0x3) << 0) 1321 ); 1322 1323 ddr->ddr_sdram_mode = (0 1324 | ((esdmode & 0xFFFF) << 16) 1325 | ((sdmode & 0xFFFF) << 0) 1326 ); 1327 1328 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); 1329 1330 if (unq_mrs_en) { /* unique mode registers are supported */ 1331 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1332 if (popts->rtt_override) 1333 rtt = popts->rtt_override_value; 1334 else 1335 rtt = popts->cs_local_opts[i].odt_rtt_norm; 1336 1337 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */ 1338 esdmode |= (rtt & 0x7) << 8; 1339 switch (i) { 1340 case 1: 1341 ddr->ddr_sdram_mode_3 = (0 1342 | ((esdmode & 0xFFFF) << 16) 1343 | ((sdmode & 0xFFFF) << 0) 1344 ); 1345 break; 1346 case 2: 1347 ddr->ddr_sdram_mode_5 = (0 1348 | ((esdmode & 0xFFFF) << 16) 1349 | ((sdmode & 0xFFFF) << 0) 1350 ); 1351 break; 1352 case 3: 1353 ddr->ddr_sdram_mode_7 = (0 1354 | ((esdmode & 0xFFFF) << 16) 1355 | ((sdmode & 0xFFFF) << 0) 1356 ); 1357 break; 1358 } 1359 } 1360 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", 1361 ddr->ddr_sdram_mode_3); 1362 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", 1363 ddr->ddr_sdram_mode_5); 1364 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", 1365 ddr->ddr_sdram_mode_5); 1366 } 1367 } 1368 1369 #elif defined(CONFIG_SYS_FSL_DDR3) 1370 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ 1371 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, 1372 const memctl_options_t *popts, 1373 const common_timing_params_t *common_dimm, 1374 unsigned int cas_latency, 1375 unsigned int additive_latency, 1376 const unsigned int unq_mrs_en) 1377 { 1378 int i; 1379 unsigned short esdmode; /* Extended SDRAM mode */ 1380 unsigned short sdmode; /* SDRAM mode */ 1381 1382 /* Mode Register - MR1 */ 1383 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ 1384 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ 1385 unsigned int rtt; 1386 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ 1387 unsigned int al = 0; /* Posted CAS# additive latency (AL) */ 1388 unsigned int dic = 0; /* Output driver impedance, 40ohm */ 1389 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), 1390 1=Disable (Test/Debug) */ 1391 1392 /* Mode Register - MR0 */ 1393 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ 1394 unsigned int wr = 0; /* Write Recovery */ 1395 unsigned int dll_rst; /* DLL Reset */ 1396 unsigned int mode; /* Normal=0 or Test=1 */ 1397 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ 1398 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ 1399 unsigned int bt; 1400 unsigned int bl; /* BL: Burst Length */ 1401 1402 unsigned int wr_mclk; 1403 /* 1404 * DDR_SDRAM_MODE doesn't support 9,11,13,15 1405 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 1406 * for this table 1407 */ 1408 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; 1409 1410 if (popts->rtt_override) 1411 rtt = popts->rtt_override_value; 1412 else 1413 rtt = popts->cs_local_opts[0].odt_rtt_norm; 1414 1415 if (additive_latency == (cas_latency - 1)) 1416 al = 1; 1417 if (additive_latency == (cas_latency - 2)) 1418 al = 2; 1419 1420 if (popts->quad_rank_present) 1421 dic = 1; /* output driver impedance 240/7 ohm */ 1422 1423 /* 1424 * The esdmode value will also be used for writing 1425 * MR1 during write leveling for DDR3, although the 1426 * bits specifically related to the write leveling 1427 * scheme will be handled automatically by the DDR 1428 * controller. so we set the wrlvl_en = 0 here. 1429 */ 1430 esdmode = (0 1431 | ((qoff & 0x1) << 12) 1432 | ((tdqs_en & 0x1) << 11) 1433 | ((rtt & 0x4) << 7) /* rtt field is split */ 1434 | ((wrlvl_en & 0x1) << 7) 1435 | ((rtt & 0x2) << 5) /* rtt field is split */ 1436 | ((dic & 0x2) << 4) /* DIC field is split */ 1437 | ((al & 0x3) << 3) 1438 | ((rtt & 0x1) << 2) /* rtt field is split */ 1439 | ((dic & 0x1) << 1) /* DIC field is split */ 1440 | ((dll_en & 0x1) << 0) 1441 ); 1442 1443 /* 1444 * DLL control for precharge PD 1445 * 0=slow exit DLL off (tXPDLL) 1446 * 1=fast exit DLL on (tXP) 1447 */ 1448 dll_on = 1; 1449 1450 wr_mclk = picos_to_mclk(common_dimm->twr_ps); 1451 if (wr_mclk <= 16) { 1452 wr = wr_table[wr_mclk - 5]; 1453 } else { 1454 printf("Error: unsupported write recovery for mode register " 1455 "wr_mclk = %d\n", wr_mclk); 1456 } 1457 1458 dll_rst = 0; /* dll no reset */ 1459 mode = 0; /* normal mode */ 1460 1461 /* look up table to get the cas latency bits */ 1462 if (cas_latency >= 5 && cas_latency <= 16) { 1463 unsigned char cas_latency_table[] = { 1464 0x2, /* 5 clocks */ 1465 0x4, /* 6 clocks */ 1466 0x6, /* 7 clocks */ 1467 0x8, /* 8 clocks */ 1468 0xa, /* 9 clocks */ 1469 0xc, /* 10 clocks */ 1470 0xe, /* 11 clocks */ 1471 0x1, /* 12 clocks */ 1472 0x3, /* 13 clocks */ 1473 0x5, /* 14 clocks */ 1474 0x7, /* 15 clocks */ 1475 0x9, /* 16 clocks */ 1476 }; 1477 caslat = cas_latency_table[cas_latency - 5]; 1478 } else { 1479 printf("Error: unsupported cas latency for mode register\n"); 1480 } 1481 1482 bt = 0; /* Nibble sequential */ 1483 1484 switch (popts->burst_length) { 1485 case DDR_BL8: 1486 bl = 0; 1487 break; 1488 case DDR_OTF: 1489 bl = 1; 1490 break; 1491 case DDR_BC4: 1492 bl = 2; 1493 break; 1494 default: 1495 printf("Error: invalid burst length of %u specified. " 1496 " Defaulting to on-the-fly BC4 or BL8 beats.\n", 1497 popts->burst_length); 1498 bl = 1; 1499 break; 1500 } 1501 1502 sdmode = (0 1503 | ((dll_on & 0x1) << 12) 1504 | ((wr & 0x7) << 9) 1505 | ((dll_rst & 0x1) << 8) 1506 | ((mode & 0x1) << 7) 1507 | (((caslat >> 1) & 0x7) << 4) 1508 | ((bt & 0x1) << 3) 1509 | ((caslat & 1) << 2) 1510 | ((bl & 0x3) << 0) 1511 ); 1512 1513 ddr->ddr_sdram_mode = (0 1514 | ((esdmode & 0xFFFF) << 16) 1515 | ((sdmode & 0xFFFF) << 0) 1516 ); 1517 1518 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); 1519 1520 if (unq_mrs_en) { /* unique mode registers are supported */ 1521 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1522 if (popts->rtt_override) 1523 rtt = popts->rtt_override_value; 1524 else 1525 rtt = popts->cs_local_opts[i].odt_rtt_norm; 1526 1527 esdmode &= 0xFDBB; /* clear bit 9,6,2 */ 1528 esdmode |= (0 1529 | ((rtt & 0x4) << 7) /* rtt field is split */ 1530 | ((rtt & 0x2) << 5) /* rtt field is split */ 1531 | ((rtt & 0x1) << 2) /* rtt field is split */ 1532 ); 1533 switch (i) { 1534 case 1: 1535 ddr->ddr_sdram_mode_3 = (0 1536 | ((esdmode & 0xFFFF) << 16) 1537 | ((sdmode & 0xFFFF) << 0) 1538 ); 1539 break; 1540 case 2: 1541 ddr->ddr_sdram_mode_5 = (0 1542 | ((esdmode & 0xFFFF) << 16) 1543 | ((sdmode & 0xFFFF) << 0) 1544 ); 1545 break; 1546 case 3: 1547 ddr->ddr_sdram_mode_7 = (0 1548 | ((esdmode & 0xFFFF) << 16) 1549 | ((sdmode & 0xFFFF) << 0) 1550 ); 1551 break; 1552 } 1553 } 1554 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", 1555 ddr->ddr_sdram_mode_3); 1556 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", 1557 ddr->ddr_sdram_mode_5); 1558 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", 1559 ddr->ddr_sdram_mode_5); 1560 } 1561 } 1562 1563 #else /* !CONFIG_SYS_FSL_DDR3 */ 1564 1565 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ 1566 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, 1567 const memctl_options_t *popts, 1568 const common_timing_params_t *common_dimm, 1569 unsigned int cas_latency, 1570 unsigned int additive_latency, 1571 const unsigned int unq_mrs_en) 1572 { 1573 unsigned short esdmode; /* Extended SDRAM mode */ 1574 unsigned short sdmode; /* SDRAM mode */ 1575 1576 /* 1577 * FIXME: This ought to be pre-calculated in a 1578 * technology-specific routine, 1579 * e.g. compute_DDR2_mode_register(), and then the 1580 * sdmode and esdmode passed in as part of common_dimm. 1581 */ 1582 1583 /* Extended Mode Register */ 1584 unsigned int mrs = 0; /* Mode Register Set */ 1585 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ 1586 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ 1587 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ 1588 unsigned int ocd = 0; /* 0x0=OCD not supported, 1589 0x7=OCD default state */ 1590 unsigned int rtt; 1591 unsigned int al; /* Posted CAS# additive latency (AL) */ 1592 unsigned int ods = 0; /* Output Drive Strength: 1593 0 = Full strength (18ohm) 1594 1 = Reduced strength (4ohm) */ 1595 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), 1596 1=Disable (Test/Debug) */ 1597 1598 /* Mode Register (MR) */ 1599 unsigned int mr; /* Mode Register Definition */ 1600 unsigned int pd; /* Power-Down Mode */ 1601 unsigned int wr; /* Write Recovery */ 1602 unsigned int dll_res; /* DLL Reset */ 1603 unsigned int mode; /* Normal=0 or Test=1 */ 1604 unsigned int caslat = 0;/* CAS# latency */ 1605 /* BT: Burst Type (0=Sequential, 1=Interleaved) */ 1606 unsigned int bt; 1607 unsigned int bl; /* BL: Burst Length */ 1608 1609 dqs_en = !popts->dqs_config; 1610 rtt = fsl_ddr_get_rtt(); 1611 1612 al = additive_latency; 1613 1614 esdmode = (0 1615 | ((mrs & 0x3) << 14) 1616 | ((outputs & 0x1) << 12) 1617 | ((rdqs_en & 0x1) << 11) 1618 | ((dqs_en & 0x1) << 10) 1619 | ((ocd & 0x7) << 7) 1620 | ((rtt & 0x2) << 5) /* rtt field is split */ 1621 | ((al & 0x7) << 3) 1622 | ((rtt & 0x1) << 2) /* rtt field is split */ 1623 | ((ods & 0x1) << 1) 1624 | ((dll_en & 0x1) << 0) 1625 ); 1626 1627 mr = 0; /* FIXME: CHECKME */ 1628 1629 /* 1630 * 0 = Fast Exit (Normal) 1631 * 1 = Slow Exit (Low Power) 1632 */ 1633 pd = 0; 1634 1635 #if defined(CONFIG_SYS_FSL_DDR1) 1636 wr = 0; /* Historical */ 1637 #elif defined(CONFIG_SYS_FSL_DDR2) 1638 wr = picos_to_mclk(common_dimm->twr_ps); 1639 #endif 1640 dll_res = 0; 1641 mode = 0; 1642 1643 #if defined(CONFIG_SYS_FSL_DDR1) 1644 if (1 <= cas_latency && cas_latency <= 4) { 1645 unsigned char mode_caslat_table[4] = { 1646 0x5, /* 1.5 clocks */ 1647 0x2, /* 2.0 clocks */ 1648 0x6, /* 2.5 clocks */ 1649 0x3 /* 3.0 clocks */ 1650 }; 1651 caslat = mode_caslat_table[cas_latency - 1]; 1652 } else { 1653 printf("Warning: unknown cas_latency %d\n", cas_latency); 1654 } 1655 #elif defined(CONFIG_SYS_FSL_DDR2) 1656 caslat = cas_latency; 1657 #endif 1658 bt = 0; 1659 1660 switch (popts->burst_length) { 1661 case DDR_BL4: 1662 bl = 2; 1663 break; 1664 case DDR_BL8: 1665 bl = 3; 1666 break; 1667 default: 1668 printf("Error: invalid burst length of %u specified. " 1669 " Defaulting to 4 beats.\n", 1670 popts->burst_length); 1671 bl = 2; 1672 break; 1673 } 1674 1675 sdmode = (0 1676 | ((mr & 0x3) << 14) 1677 | ((pd & 0x1) << 12) 1678 | ((wr & 0x7) << 9) 1679 | ((dll_res & 0x1) << 8) 1680 | ((mode & 0x1) << 7) 1681 | ((caslat & 0x7) << 4) 1682 | ((bt & 0x1) << 3) 1683 | ((bl & 0x7) << 0) 1684 ); 1685 1686 ddr->ddr_sdram_mode = (0 1687 | ((esdmode & 0xFFFF) << 16) 1688 | ((sdmode & 0xFFFF) << 0) 1689 ); 1690 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); 1691 } 1692 #endif 1693 1694 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ 1695 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) 1696 { 1697 unsigned int init_value; /* Initialization value */ 1698 1699 #ifdef CONFIG_MEM_INIT_VALUE 1700 init_value = CONFIG_MEM_INIT_VALUE; 1701 #else 1702 init_value = 0xDEADBEEF; 1703 #endif 1704 ddr->ddr_data_init = init_value; 1705 } 1706 1707 /* 1708 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) 1709 * The old controller on the 8540/60 doesn't have this register. 1710 * Hope it's OK to set it (to 0) anyway. 1711 */ 1712 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, 1713 const memctl_options_t *popts) 1714 { 1715 unsigned int clk_adjust; /* Clock adjust */ 1716 1717 clk_adjust = popts->clk_adjust; 1718 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; 1719 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); 1720 } 1721 1722 /* DDR Initialization Address (DDR_INIT_ADDR) */ 1723 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) 1724 { 1725 unsigned int init_addr = 0; /* Initialization address */ 1726 1727 ddr->ddr_init_addr = init_addr; 1728 } 1729 1730 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ 1731 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) 1732 { 1733 unsigned int uia = 0; /* Use initialization address */ 1734 unsigned int init_ext_addr = 0; /* Initialization address */ 1735 1736 ddr->ddr_init_ext_addr = (0 1737 | ((uia & 0x1) << 31) 1738 | (init_ext_addr & 0xF) 1739 ); 1740 } 1741 1742 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ 1743 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, 1744 const memctl_options_t *popts) 1745 { 1746 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ 1747 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ 1748 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ 1749 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ 1750 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ 1751 1752 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 1753 if (popts->burst_length == DDR_BL8) { 1754 /* We set BL/2 for fixed BL8 */ 1755 rrt = 0; /* BL/2 clocks */ 1756 wwt = 0; /* BL/2 clocks */ 1757 } else { 1758 /* We need to set BL/2 + 2 to BC4 and OTF */ 1759 rrt = 2; /* BL/2 + 2 clocks */ 1760 wwt = 2; /* BL/2 + 2 clocks */ 1761 } 1762 #endif 1763 1764 #ifdef CONFIG_SYS_FSL_DDR4 1765 dll_lock = 2; /* tDLLK = 1024 clocks */ 1766 #elif defined(CONFIG_SYS_FSL_DDR3) 1767 dll_lock = 1; /* tDLLK = 512 clocks from spec */ 1768 #endif 1769 ddr->timing_cfg_4 = (0 1770 | ((rwt & 0xf) << 28) 1771 | ((wrt & 0xf) << 24) 1772 | ((rrt & 0xf) << 20) 1773 | ((wwt & 0xf) << 16) 1774 | (dll_lock & 0x3) 1775 ); 1776 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); 1777 } 1778 1779 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ 1780 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) 1781 { 1782 unsigned int rodt_on = 0; /* Read to ODT on */ 1783 unsigned int rodt_off = 0; /* Read to ODT off */ 1784 unsigned int wodt_on = 0; /* Write to ODT on */ 1785 unsigned int wodt_off = 0; /* Write to ODT off */ 1786 1787 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 1788 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1789 ((ddr->timing_cfg_2 & 0x00040000) >> 14); 1790 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ 1791 if (cas_latency >= wr_lat) 1792 rodt_on = cas_latency - wr_lat + 1; 1793 rodt_off = 4; /* 4 clocks */ 1794 wodt_on = 1; /* 1 clocks */ 1795 wodt_off = 4; /* 4 clocks */ 1796 #endif 1797 1798 ddr->timing_cfg_5 = (0 1799 | ((rodt_on & 0x1f) << 24) 1800 | ((rodt_off & 0x7) << 20) 1801 | ((wodt_on & 0x1f) << 12) 1802 | ((wodt_off & 0x7) << 8) 1803 ); 1804 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); 1805 } 1806 1807 #ifdef CONFIG_SYS_FSL_DDR4 1808 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) 1809 { 1810 unsigned int hs_caslat = 0; 1811 unsigned int hs_wrlat = 0; 1812 unsigned int hs_wrrec = 0; 1813 unsigned int hs_clkadj = 0; 1814 unsigned int hs_wrlvl_start = 0; 1815 1816 ddr->timing_cfg_6 = (0 1817 | ((hs_caslat & 0x1f) << 24) 1818 | ((hs_wrlat & 0x1f) << 19) 1819 | ((hs_wrrec & 0x1f) << 12) 1820 | ((hs_clkadj & 0x1f) << 6) 1821 | ((hs_wrlvl_start & 0x1f) << 0) 1822 ); 1823 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); 1824 } 1825 1826 static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr, 1827 const common_timing_params_t *common_dimm) 1828 { 1829 unsigned int txpr, tcksre, tcksrx; 1830 unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd; 1831 1832 txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000)); 1833 tcksre = max(5U, picos_to_mclk(10000)); 1834 tcksrx = max(5U, picos_to_mclk(10000)); 1835 par_lat = 0; 1836 cs_to_cmd = 0; 1837 1838 if (txpr <= 200) 1839 cke_rst = 0; 1840 else if (txpr <= 256) 1841 cke_rst = 1; 1842 else if (txpr <= 512) 1843 cke_rst = 2; 1844 else 1845 cke_rst = 3; 1846 1847 if (tcksre <= 19) 1848 cksre = tcksre - 5; 1849 else 1850 cksre = 15; 1851 1852 if (tcksrx <= 19) 1853 cksrx = tcksrx - 5; 1854 else 1855 cksrx = 15; 1856 1857 ddr->timing_cfg_7 = (0 1858 | ((cke_rst & 0x3) << 28) 1859 | ((cksre & 0xf) << 24) 1860 | ((cksrx & 0xf) << 20) 1861 | ((par_lat & 0xf) << 16) 1862 | ((cs_to_cmd & 0xf) << 4) 1863 ); 1864 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); 1865 } 1866 1867 static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, 1868 const memctl_options_t *popts, 1869 const common_timing_params_t *common_dimm, 1870 unsigned int cas_latency) 1871 { 1872 unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg; 1873 unsigned int acttoact_bg, wrtord_bg, pre_all_rec; 1874 unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps); 1875 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1876 ((ddr->timing_cfg_2 & 0x00040000) >> 14); 1877 1878 rwt_bg = cas_latency + 2 + 4 - wr_lat; 1879 if (rwt_bg < tccdl) 1880 rwt_bg = tccdl - rwt_bg; 1881 else 1882 rwt_bg = 0; 1883 1884 wrt_bg = wr_lat + 4 + 1 - cas_latency; 1885 if (wrt_bg < tccdl) 1886 wrt_bg = tccdl - wrt_bg; 1887 else 1888 wrt_bg = 0; 1889 1890 if (popts->burst_length == DDR_BL8) { 1891 rrt_bg = tccdl - 4; 1892 wwt_bg = tccdl - 4; 1893 } else { 1894 rrt_bg = tccdl - 2; 1895 wwt_bg = tccdl - 4; 1896 } 1897 1898 acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps); 1899 wrtord_bg = max(4U, picos_to_mclk(7500)); 1900 if (popts->otf_burst_chop_en) 1901 wrtord_bg += 2; 1902 1903 pre_all_rec = 0; 1904 1905 ddr->timing_cfg_8 = (0 1906 | ((rwt_bg & 0xf) << 28) 1907 | ((wrt_bg & 0xf) << 24) 1908 | ((rrt_bg & 0xf) << 20) 1909 | ((wwt_bg & 0xf) << 16) 1910 | ((acttoact_bg & 0xf) << 12) 1911 | ((wrtord_bg & 0xf) << 8) 1912 | ((pre_all_rec & 0x1f) << 0) 1913 ); 1914 1915 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); 1916 } 1917 1918 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr) 1919 { 1920 ddr->timing_cfg_9 = 0; 1921 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); 1922 } 1923 1924 /* This function needs to be called after set_ddr_sdram_cfg() is called */ 1925 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr, 1926 const dimm_params_t *dimm_params) 1927 { 1928 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1; 1929 1930 ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) | 1931 ((dimm_params->dq_mapping[1] & 0x3F) << 20) | 1932 ((dimm_params->dq_mapping[2] & 0x3F) << 14) | 1933 ((dimm_params->dq_mapping[3] & 0x3F) << 8) | 1934 ((dimm_params->dq_mapping[4] & 0x3F) << 2); 1935 1936 ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) | 1937 ((dimm_params->dq_mapping[6] & 0x3F) << 20) | 1938 ((dimm_params->dq_mapping[7] & 0x3F) << 14) | 1939 ((dimm_params->dq_mapping[10] & 0x3F) << 8) | 1940 ((dimm_params->dq_mapping[11] & 0x3F) << 2); 1941 1942 ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) | 1943 ((dimm_params->dq_mapping[13] & 0x3F) << 20) | 1944 ((dimm_params->dq_mapping[14] & 0x3F) << 14) | 1945 ((dimm_params->dq_mapping[15] & 0x3F) << 8) | 1946 ((dimm_params->dq_mapping[16] & 0x3F) << 2); 1947 1948 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */ 1949 ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) | 1950 ((dimm_params->dq_mapping[8] & 0x3F) << 20) | 1951 (acc_ecc_en ? 0 : 1952 (dimm_params->dq_mapping[9] & 0x3F) << 14) | 1953 dimm_params->dq_mapping_ors; 1954 1955 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0); 1956 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1); 1957 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2); 1958 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3); 1959 } 1960 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr, 1961 const memctl_options_t *popts) 1962 { 1963 int rd_pre; 1964 1965 rd_pre = popts->quad_rank_present ? 1 : 0; 1966 1967 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; 1968 1969 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); 1970 } 1971 #endif /* CONFIG_SYS_FSL_DDR4 */ 1972 1973 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ 1974 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) 1975 { 1976 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ 1977 /* Normal Operation Full Calibration Time (tZQoper) */ 1978 unsigned int zqoper = 0; 1979 /* Normal Operation Short Calibration Time (tZQCS) */ 1980 unsigned int zqcs = 0; 1981 #ifdef CONFIG_SYS_FSL_DDR4 1982 unsigned int zqcs_init; 1983 #endif 1984 1985 if (zq_en) { 1986 #ifdef CONFIG_SYS_FSL_DDR4 1987 zqinit = 10; /* 1024 clocks */ 1988 zqoper = 9; /* 512 clocks */ 1989 zqcs = 7; /* 128 clocks */ 1990 zqcs_init = 5; /* 1024 refresh sequences */ 1991 #else 1992 zqinit = 9; /* 512 clocks */ 1993 zqoper = 8; /* 256 clocks */ 1994 zqcs = 6; /* 64 clocks */ 1995 #endif 1996 } 1997 1998 ddr->ddr_zq_cntl = (0 1999 | ((zq_en & 0x1) << 31) 2000 | ((zqinit & 0xF) << 24) 2001 | ((zqoper & 0xF) << 16) 2002 | ((zqcs & 0xF) << 8) 2003 #ifdef CONFIG_SYS_FSL_DDR4 2004 | ((zqcs_init & 0xF) << 0) 2005 #endif 2006 ); 2007 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); 2008 } 2009 2010 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ 2011 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, 2012 const memctl_options_t *popts) 2013 { 2014 /* 2015 * First DQS pulse rising edge after margining mode 2016 * is programmed (tWL_MRD) 2017 */ 2018 unsigned int wrlvl_mrd = 0; 2019 /* ODT delay after margining mode is programmed (tWL_ODTEN) */ 2020 unsigned int wrlvl_odten = 0; 2021 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ 2022 unsigned int wrlvl_dqsen = 0; 2023 /* WRLVL_SMPL: Write leveling sample time */ 2024 unsigned int wrlvl_smpl = 0; 2025 /* WRLVL_WLR: Write leveling repeition time */ 2026 unsigned int wrlvl_wlr = 0; 2027 /* WRLVL_START: Write leveling start time */ 2028 unsigned int wrlvl_start = 0; 2029 2030 /* suggest enable write leveling for DDR3 due to fly-by topology */ 2031 if (wrlvl_en) { 2032 /* tWL_MRD min = 40 nCK, we set it 64 */ 2033 wrlvl_mrd = 0x6; 2034 /* tWL_ODTEN 128 */ 2035 wrlvl_odten = 0x7; 2036 /* tWL_DQSEN min = 25 nCK, we set it 32 */ 2037 wrlvl_dqsen = 0x5; 2038 /* 2039 * Write leveling sample time at least need 6 clocks 2040 * higher than tWLO to allow enough time for progagation 2041 * delay and sampling the prime data bits. 2042 */ 2043 wrlvl_smpl = 0xf; 2044 /* 2045 * Write leveling repetition time 2046 * at least tWLO + 6 clocks clocks 2047 * we set it 64 2048 */ 2049 wrlvl_wlr = 0x6; 2050 /* 2051 * Write leveling start time 2052 * The value use for the DQS_ADJUST for the first sample 2053 * when write leveling is enabled. It probably needs to be 2054 * overriden per platform. 2055 */ 2056 wrlvl_start = 0x8; 2057 /* 2058 * Override the write leveling sample and start time 2059 * according to specific board 2060 */ 2061 if (popts->wrlvl_override) { 2062 wrlvl_smpl = popts->wrlvl_sample; 2063 wrlvl_start = popts->wrlvl_start; 2064 } 2065 } 2066 2067 ddr->ddr_wrlvl_cntl = (0 2068 | ((wrlvl_en & 0x1) << 31) 2069 | ((wrlvl_mrd & 0x7) << 24) 2070 | ((wrlvl_odten & 0x7) << 20) 2071 | ((wrlvl_dqsen & 0x7) << 16) 2072 | ((wrlvl_smpl & 0xf) << 12) 2073 | ((wrlvl_wlr & 0x7) << 8) 2074 | ((wrlvl_start & 0x1F) << 0) 2075 ); 2076 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); 2077 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; 2078 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); 2079 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; 2080 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); 2081 2082 } 2083 2084 /* DDR Self Refresh Counter (DDR_SR_CNTR) */ 2085 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) 2086 { 2087 /* Self Refresh Idle Threshold */ 2088 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; 2089 } 2090 2091 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) 2092 { 2093 if (popts->addr_hash) { 2094 ddr->ddr_eor = 0x40000000; /* address hash enable */ 2095 puts("Address hashing enabled.\n"); 2096 } 2097 } 2098 2099 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) 2100 { 2101 ddr->ddr_cdr1 = popts->ddr_cdr1; 2102 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); 2103 } 2104 2105 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) 2106 { 2107 ddr->ddr_cdr2 = popts->ddr_cdr2; 2108 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); 2109 } 2110 2111 unsigned int 2112 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) 2113 { 2114 unsigned int res = 0; 2115 2116 /* 2117 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are 2118 * not set at the same time. 2119 */ 2120 if (ddr->ddr_sdram_cfg & 0x10000000 2121 && ddr->ddr_sdram_cfg & 0x00008000) { 2122 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " 2123 " should not be set at the same time.\n"); 2124 res++; 2125 } 2126 2127 return res; 2128 } 2129 2130 unsigned int 2131 compute_fsl_memctl_config_regs(const memctl_options_t *popts, 2132 fsl_ddr_cfg_regs_t *ddr, 2133 const common_timing_params_t *common_dimm, 2134 const dimm_params_t *dimm_params, 2135 unsigned int dbw_cap_adj, 2136 unsigned int size_only) 2137 { 2138 unsigned int i; 2139 unsigned int cas_latency; 2140 unsigned int additive_latency; 2141 unsigned int sr_it; 2142 unsigned int zq_en; 2143 unsigned int wrlvl_en; 2144 unsigned int ip_rev = 0; 2145 unsigned int unq_mrs_en = 0; 2146 int cs_en = 1; 2147 2148 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); 2149 2150 if (common_dimm == NULL) { 2151 printf("Error: subset DIMM params struct null pointer\n"); 2152 return 1; 2153 } 2154 2155 /* 2156 * Process overrides first. 2157 * 2158 * FIXME: somehow add dereated caslat to this 2159 */ 2160 cas_latency = (popts->cas_latency_override) 2161 ? popts->cas_latency_override_value 2162 : common_dimm->lowest_common_spd_caslat; 2163 2164 additive_latency = (popts->additive_latency_override) 2165 ? popts->additive_latency_override_value 2166 : common_dimm->additive_latency; 2167 2168 sr_it = (popts->auto_self_refresh_en) 2169 ? popts->sr_it 2170 : 0; 2171 /* ZQ calibration */ 2172 zq_en = (popts->zq_en) ? 1 : 0; 2173 /* write leveling */ 2174 wrlvl_en = (popts->wrlvl_en) ? 1 : 0; 2175 2176 /* Chip Select Memory Bounds (CSn_BNDS) */ 2177 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 2178 unsigned long long ea, sa; 2179 unsigned int cs_per_dimm 2180 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR; 2181 unsigned int dimm_number 2182 = i / cs_per_dimm; 2183 unsigned long long rank_density 2184 = dimm_params[dimm_number].rank_density >> dbw_cap_adj; 2185 2186 if (dimm_params[dimm_number].n_ranks == 0) { 2187 debug("Skipping setup of CS%u " 2188 "because n_ranks on DIMM %u is 0\n", i, dimm_number); 2189 continue; 2190 } 2191 if (popts->memctl_interleaving) { 2192 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { 2193 case FSL_DDR_CS0_CS1_CS2_CS3: 2194 break; 2195 case FSL_DDR_CS0_CS1: 2196 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 2197 if (i > 1) 2198 cs_en = 0; 2199 break; 2200 case FSL_DDR_CS2_CS3: 2201 default: 2202 if (i > 0) 2203 cs_en = 0; 2204 break; 2205 } 2206 sa = common_dimm->base_address; 2207 ea = sa + common_dimm->total_mem - 1; 2208 } else if (!popts->memctl_interleaving) { 2209 /* 2210 * If memory interleaving between controllers is NOT 2211 * enabled, the starting address for each memory 2212 * controller is distinct. However, because rank 2213 * interleaving is enabled, the starting and ending 2214 * addresses of the total memory on that memory 2215 * controller needs to be programmed into its 2216 * respective CS0_BNDS. 2217 */ 2218 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { 2219 case FSL_DDR_CS0_CS1_CS2_CS3: 2220 sa = common_dimm->base_address; 2221 ea = sa + common_dimm->total_mem - 1; 2222 break; 2223 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 2224 if ((i >= 2) && (dimm_number == 0)) { 2225 sa = dimm_params[dimm_number].base_address + 2226 2 * rank_density; 2227 ea = sa + 2 * rank_density - 1; 2228 } else { 2229 sa = dimm_params[dimm_number].base_address; 2230 ea = sa + 2 * rank_density - 1; 2231 } 2232 break; 2233 case FSL_DDR_CS0_CS1: 2234 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { 2235 sa = dimm_params[dimm_number].base_address; 2236 ea = sa + rank_density - 1; 2237 if (i != 1) 2238 sa += (i % cs_per_dimm) * rank_density; 2239 ea += (i % cs_per_dimm) * rank_density; 2240 } else { 2241 sa = 0; 2242 ea = 0; 2243 } 2244 if (i == 0) 2245 ea += rank_density; 2246 break; 2247 case FSL_DDR_CS2_CS3: 2248 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { 2249 sa = dimm_params[dimm_number].base_address; 2250 ea = sa + rank_density - 1; 2251 if (i != 3) 2252 sa += (i % cs_per_dimm) * rank_density; 2253 ea += (i % cs_per_dimm) * rank_density; 2254 } else { 2255 sa = 0; 2256 ea = 0; 2257 } 2258 if (i == 2) 2259 ea += (rank_density >> dbw_cap_adj); 2260 break; 2261 default: /* No bank(chip-select) interleaving */ 2262 sa = dimm_params[dimm_number].base_address; 2263 ea = sa + rank_density - 1; 2264 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { 2265 sa += (i % cs_per_dimm) * rank_density; 2266 ea += (i % cs_per_dimm) * rank_density; 2267 } else { 2268 sa = 0; 2269 ea = 0; 2270 } 2271 break; 2272 } 2273 } 2274 2275 sa >>= 24; 2276 ea >>= 24; 2277 2278 if (cs_en) { 2279 ddr->cs[i].bnds = (0 2280 | ((sa & 0xffff) << 16) /* starting address */ 2281 | ((ea & 0xffff) << 0) /* ending address */ 2282 ); 2283 } else { 2284 /* setting bnds to 0xffffffff for inactive CS */ 2285 ddr->cs[i].bnds = 0xffffffff; 2286 } 2287 2288 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); 2289 set_csn_config(dimm_number, i, ddr, popts, dimm_params); 2290 set_csn_config_2(i, ddr); 2291 } 2292 2293 /* 2294 * In the case we only need to compute the ddr sdram size, we only need 2295 * to set csn registers, so return from here. 2296 */ 2297 if (size_only) 2298 return 0; 2299 2300 set_ddr_eor(ddr, popts); 2301 2302 #if !defined(CONFIG_SYS_FSL_DDR1) 2303 set_timing_cfg_0(ddr, popts, dimm_params); 2304 #endif 2305 2306 set_timing_cfg_3(ddr, popts, common_dimm, cas_latency, 2307 additive_latency); 2308 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); 2309 set_timing_cfg_2(ddr, popts, common_dimm, 2310 cas_latency, additive_latency); 2311 2312 set_ddr_cdr1(ddr, popts); 2313 set_ddr_cdr2(ddr, popts); 2314 set_ddr_sdram_cfg(ddr, popts, common_dimm); 2315 ip_rev = fsl_ddr_get_version(); 2316 if (ip_rev > 0x40400) 2317 unq_mrs_en = 1; 2318 2319 if ((ip_rev > 0x40700) && (popts->cswl_override != 0)) 2320 ddr->debug[18] = popts->cswl_override; 2321 2322 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); 2323 set_ddr_sdram_mode(ddr, popts, common_dimm, 2324 cas_latency, additive_latency, unq_mrs_en); 2325 set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en); 2326 #ifdef CONFIG_SYS_FSL_DDR4 2327 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en); 2328 set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en); 2329 #endif 2330 set_ddr_sdram_interval(ddr, popts, common_dimm); 2331 set_ddr_data_init(ddr); 2332 set_ddr_sdram_clk_cntl(ddr, popts); 2333 set_ddr_init_addr(ddr); 2334 set_ddr_init_ext_addr(ddr); 2335 set_timing_cfg_4(ddr, popts); 2336 set_timing_cfg_5(ddr, cas_latency); 2337 #ifdef CONFIG_SYS_FSL_DDR4 2338 set_ddr_sdram_cfg_3(ddr, popts); 2339 set_timing_cfg_6(ddr); 2340 set_timing_cfg_7(ddr, common_dimm); 2341 set_timing_cfg_8(ddr, popts, common_dimm, cas_latency); 2342 set_timing_cfg_9(ddr); 2343 set_ddr_dq_mapping(ddr, dimm_params); 2344 #endif 2345 2346 set_ddr_zq_cntl(ddr, zq_en); 2347 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); 2348 2349 set_ddr_sr_cntr(ddr, sr_it); 2350 2351 set_ddr_sdram_rcw(ddr, popts, common_dimm); 2352 2353 #ifdef CONFIG_SYS_FSL_DDR_EMU 2354 /* disble DDR training for emulator */ 2355 ddr->debug[2] = 0x00000400; 2356 ddr->debug[4] = 0xff800000; 2357 #endif 2358 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508 2359 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400)) 2360 ddr->debug[2] |= 0x00000200; /* set bit 22 */ 2361 #endif 2362 2363 return check_fsl_memctl_config_regs(ddr); 2364 } 2365