1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Derived from mpc85xx_ddr_gen3.c, removed all workarounds 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <fsl_ddr_sdram.h> 12 #include <asm/processor.h> 13 #include <fsl_immap.h> 14 #include <fsl_ddr.h> 15 16 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 17 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 18 #endif 19 20 21 /* 22 * regs has the to-be-set values for DDR controller registers 23 * ctrl_num is the DDR controller number 24 * step: 0 goes through the initialization in one pass 25 * 1 sets registers and returns before enabling controller 26 * 2 resumes from step 1 and continues to initialize 27 * Dividing the initialization to two steps to deassert DDR reset signal 28 * to comply with JEDEC specs for RDIMMs. 29 */ 30 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 31 unsigned int ctrl_num, int step) 32 { 33 unsigned int i, bus_width; 34 struct ccsr_ddr __iomem *ddr; 35 u32 temp_sdram_cfg; 36 u32 total_gb_size_per_controller; 37 int timeout; 38 39 switch (ctrl_num) { 40 case 0: 41 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 42 break; 43 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) 44 case 1: 45 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 46 break; 47 #endif 48 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) 49 case 2: 50 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 51 break; 52 #endif 53 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) 54 case 3: 55 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 56 break; 57 #endif 58 default: 59 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 60 return; 61 } 62 63 if (step == 2) 64 goto step2; 65 66 if (regs->ddr_eor) 67 ddr_out32(&ddr->eor, regs->ddr_eor); 68 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 69 if (i == 0) { 70 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 71 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 72 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 73 74 } else if (i == 1) { 75 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 76 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 77 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 78 79 } else if (i == 2) { 80 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 81 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 82 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 83 84 } else if (i == 3) { 85 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 86 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 87 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 88 } 89 } 90 91 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 92 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 93 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 94 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 95 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 96 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 97 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 98 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 99 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 100 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 101 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 102 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 103 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 104 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 105 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 106 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 107 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 108 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 109 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 110 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 111 #ifndef CONFIG_SYS_FSL_DDR_EMU 112 /* 113 * Skip these two registers if running on emulator 114 * because emulator doesn't have skew between bytes. 115 */ 116 117 if (regs->ddr_wrlvl_cntl_2) 118 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 119 if (regs->ddr_wrlvl_cntl_3) 120 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 121 #endif 122 123 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 124 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 125 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 126 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 127 #ifdef CONFIG_DEEP_SLEEP 128 if (is_warm_boot()) { 129 ddr_out32(&ddr->sdram_cfg_2, 130 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 131 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 132 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 133 134 /* DRAM VRef will not be trained */ 135 ddr_out32(&ddr->ddr_cdr2, 136 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 137 } else 138 #endif 139 { 140 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 141 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 142 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 143 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 144 } 145 ddr_out32(&ddr->err_disable, regs->err_disable); 146 ddr_out32(&ddr->err_int_en, regs->err_int_en); 147 for (i = 0; i < 32; i++) { 148 if (regs->debug[i]) { 149 debug("Write to debug_%d as %08x\n", i + 1, 150 regs->debug[i]); 151 ddr_out32(&ddr->debug[i], regs->debug[i]); 152 } 153 } 154 155 /* 156 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 157 * deasserted. Clocks start when any chip select is enabled and clock 158 * control register is set. Because all DDR components are connected to 159 * one reset signal, this needs to be done in two steps. Step 1 is to 160 * get the clocks started. Step 2 resumes after reset signal is 161 * deasserted. 162 */ 163 if (step == 1) { 164 udelay(200); 165 return; 166 } 167 168 step2: 169 /* Set, but do not enable the memory */ 170 temp_sdram_cfg = regs->ddr_sdram_cfg; 171 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 172 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); 173 174 /* 175 * 500 painful micro-seconds must elapse between 176 * the DDR clock setup and the DDR config enable. 177 * DDR2 need 200 us, and DDR3 need 500 us from spec, 178 * we choose the max, that is 500 us for all of case. 179 */ 180 udelay(500); 181 asm volatile("dsb sy;isb"); 182 183 #ifdef CONFIG_DEEP_SLEEP 184 if (is_warm_boot()) { 185 /* enter self-refresh */ 186 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 187 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 188 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 189 /* do board specific memory setup */ 190 board_mem_sleep_setup(); 191 192 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 193 } else 194 #endif 195 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 196 /* Let the controller go */ 197 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 198 asm volatile("dsb sy;isb"); 199 200 total_gb_size_per_controller = 0; 201 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 202 if (!(regs->cs[i].config & 0x80000000)) 203 continue; 204 total_gb_size_per_controller += 1 << ( 205 ((regs->cs[i].config >> 14) & 0x3) + 2 + 206 ((regs->cs[i].config >> 8) & 0x7) + 12 + 207 ((regs->cs[i].config >> 0) & 0x7) + 8 + 208 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 209 26); /* minus 26 (count of 64M) */ 210 } 211 if (regs->cs[0].config & 0x20000000) { 212 /* 2-way interleaving */ 213 total_gb_size_per_controller <<= 1; 214 } 215 /* 216 * total memory / bus width = transactions needed 217 * transactions needed / data rate = seconds 218 * to add plenty of buffer, double the time 219 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 220 * Let's wait for 800ms 221 */ 222 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 223 >> SDRAM_CFG_DBW_SHIFT); 224 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 225 (get_ddr_freq(ctrl_num) >> 20)) << 1; 226 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 227 debug("total %d GB\n", total_gb_size_per_controller); 228 debug("Need to wait up to %d * 10ms\n", timeout); 229 230 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 231 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 232 (timeout >= 0)) { 233 udelay(10000); /* throttle polling rate */ 234 timeout--; 235 } 236 237 if (timeout <= 0) 238 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 239 #ifdef CONFIG_DEEP_SLEEP 240 if (is_warm_boot()) { 241 /* exit self-refresh */ 242 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 243 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 244 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 245 } 246 #endif 247 } 248