1 /* 2 * Copyright Altera Corporation (C) 2012-2015 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _SEQUENCER_H_ 8 #define _SEQUENCER_H_ 9 10 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \ 11 / rwcfg->mem_if_write_dqs_width) 12 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \ 13 / rwcfg->mem_if_write_dqs_width) 14 15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \ 16 / rwcfg->mem_if_write_dqs_width) 17 #define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS) 18 19 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0 20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400 21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000 22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400 23 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800 24 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00 25 26 #define NUM_SHADOW_REGS 1 27 28 #define RW_MGR_RANK_NONE 0xFF 29 #define RW_MGR_RANK_ALL 0x00 30 31 #define RW_MGR_ODT_MODE_OFF 0 32 #define RW_MGR_ODT_MODE_READ_WRITE 1 33 34 #define NUM_CALIB_REPEAT 1 35 36 #define NUM_READ_TESTS 7 37 #define NUM_READ_PB_TESTS 7 38 #define NUM_WRITE_TESTS 15 39 #define NUM_WRITE_PB_TESTS 31 40 41 #define PASS_ALL_BITS 1 42 #define PASS_ONE_BIT 0 43 44 /* calibration stages */ 45 #define CAL_STAGE_NIL 0 46 #define CAL_STAGE_VFIFO 1 47 #define CAL_STAGE_WLEVEL 2 48 #define CAL_STAGE_LFIFO 3 49 #define CAL_STAGE_WRITES 4 50 #define CAL_STAGE_FULLTEST 5 51 #define CAL_STAGE_REFRESH 6 52 #define CAL_STAGE_CAL_SKIPPED 7 53 #define CAL_STAGE_CAL_ABORTED 8 54 #define CAL_STAGE_VFIFO_AFTER_WRITES 9 55 56 /* calibration substages */ 57 #define CAL_SUBSTAGE_NIL 0 58 #define CAL_SUBSTAGE_GUARANTEED_READ 1 59 #define CAL_SUBSTAGE_DQS_EN_PHASE 2 60 #define CAL_SUBSTAGE_VFIFO_CENTER 3 61 #define CAL_SUBSTAGE_WORKING_DELAY 1 62 #define CAL_SUBSTAGE_LAST_WORKING_DELAY 2 63 #define CAL_SUBSTAGE_WLEVEL_COPY 3 64 #define CAL_SUBSTAGE_WRITES_CENTER 1 65 #define CAL_SUBSTAGE_READ_LATENCY 1 66 #define CAL_SUBSTAGE_REFRESH 1 67 68 #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000 69 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100 70 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200 71 #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300 72 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400 73 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500 74 #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700 75 #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900 76 77 /* HHP-HPS-specific versions of some commands */ 78 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600 79 #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800 80 #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00 81 #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00 82 #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00 83 84 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0) 85 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000) 86 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000) 87 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000) 88 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800) 89 90 #define PHY_MGR_CAL_RESET (0) 91 #define PHY_MGR_CAL_SUCCESS (1) 92 #define PHY_MGR_CAL_FAIL (2) 93 94 #define CALIB_SKIP_DELAY_LOOPS (1 << 0) 95 #define CALIB_SKIP_ALL_BITS_CHK (1 << 1) 96 #define CALIB_SKIP_DELAY_SWEEPS (1 << 2) 97 #define CALIB_SKIP_VFIFO (1 << 3) 98 #define CALIB_SKIP_LFIFO (1 << 4) 99 #define CALIB_SKIP_WLEVEL (1 << 5) 100 #define CALIB_SKIP_WRITES (1 << 6) 101 #define CALIB_SKIP_FULL_TEST (1 << 7) 102 #define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \ 103 CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \ 104 CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST) 105 #define CALIB_IN_RTL_SIM (1 << 8) 106 107 /* Scan chain manager command addresses */ 108 #define READ_SCC_OCT_OUT2_DELAY 0 109 #define READ_SCC_DQ_OUT2_DELAY 0 110 #define READ_SCC_DQS_IO_OUT2_DELAY 0 111 #define READ_SCC_DM_IO_OUT2_DELAY 0 112 113 /* HHP-HPS-specific values */ 114 #define SCC_MGR_HHP_EXTRAS_OFFSET 0 115 #define SCC_MGR_HHP_DQSE_MAP_OFFSET 1 116 117 /* PHY Debug mode flag constants */ 118 #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001 119 #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002 120 #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004 121 #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008 122 #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010 123 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020 124 125 /* Init and Reset delay constants - Only use if defined by sequencer_defines.h, 126 * otherwise, revert to defaults 127 * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = 128 * 200.75us @ 266MHz 129 */ 130 #ifdef TINIT_CNTR0_VAL 131 #define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL 132 #else 133 #define SEQ_TINIT_CNTR0_VAL 0 134 #endif 135 136 #ifdef TINIT_CNTR1_VAL 137 #define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL 138 #else 139 #define SEQ_TINIT_CNTR1_VAL 202 140 #endif 141 142 #ifdef TINIT_CNTR2_VAL 143 #define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL 144 #else 145 #define SEQ_TINIT_CNTR2_VAL 131 146 #endif 147 148 149 /* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = 150 * 500.86us @ 266MHz 151 */ 152 #ifdef TRESET_CNTR0_VAL 153 #define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL 154 #else 155 #define SEQ_TRESET_CNTR0_VAL 2 156 #endif 157 158 #ifdef TRESET_CNTR1_VAL 159 #define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL 160 #else 161 #define SEQ_TRESET_CNTR1_VAL 252 162 #endif 163 164 #ifdef TRESET_CNTR2_VAL 165 #define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL 166 #else 167 #define SEQ_TRESET_CNTR2_VAL 131 168 #endif 169 170 struct socfpga_sdr_rw_load_manager { 171 u32 load_cntr0; 172 u32 load_cntr1; 173 u32 load_cntr2; 174 u32 load_cntr3; 175 }; 176 177 struct socfpga_sdr_rw_load_jump_manager { 178 u32 load_jump_add0; 179 u32 load_jump_add1; 180 u32 load_jump_add2; 181 u32 load_jump_add3; 182 }; 183 184 struct socfpga_sdr_reg_file { 185 u32 signature; 186 u32 debug_data_addr; 187 u32 cur_stage; 188 u32 fom; 189 u32 failing_stage; 190 u32 debug1; 191 u32 debug2; 192 u32 dtaps_per_ptap; 193 u32 trk_sample_count; 194 u32 trk_longidle; 195 u32 delays; 196 u32 trk_rw_mgr_addr; 197 u32 trk_read_dqs_width; 198 u32 trk_rfsh; 199 }; 200 201 /* parameter variable holder */ 202 struct param_type { 203 u32 read_correct_mask; 204 u32 read_correct_mask_vg; 205 u32 write_correct_mask; 206 u32 write_correct_mask_vg; 207 }; 208 209 210 /* global variable holder */ 211 struct gbl_type { 212 uint32_t phy_debug_mode_flags; 213 214 /* current read latency */ 215 216 uint32_t curr_read_lat; 217 218 /* error code */ 219 220 uint32_t error_substage; 221 uint32_t error_stage; 222 uint32_t error_group; 223 224 /* figure-of-merit in, figure-of-merit out */ 225 226 uint32_t fom_in; 227 uint32_t fom_out; 228 229 /*USER Number of RW Mgr NOP cycles between 230 write command and write data */ 231 uint32_t rw_wl_nop_cycles; 232 }; 233 234 struct socfpga_sdr_scc_mgr { 235 u32 dqs_ena; 236 u32 dqs_io_ena; 237 u32 dq_ena; 238 u32 dm_ena; 239 u32 __padding1[4]; 240 u32 update; 241 u32 __padding2[7]; 242 u32 active_rank; 243 }; 244 245 /* PHY manager configuration registers. */ 246 struct socfpga_phy_mgr_cfg { 247 u32 phy_rlat; 248 u32 reset_mem_stbl; 249 u32 mux_sel; 250 u32 cal_status; 251 u32 cal_debug_info; 252 u32 vfifo_rd_en_ovrd; 253 u32 afi_wlat; 254 u32 afi_rlat; 255 }; 256 257 /* PHY manager command addresses. */ 258 struct socfpga_phy_mgr_cmd { 259 u32 inc_vfifo_fr; 260 u32 inc_vfifo_hard_phy; 261 u32 fifo_reset; 262 u32 inc_vfifo_fr_hr; 263 u32 inc_vfifo_qr; 264 }; 265 266 struct socfpga_data_mgr { 267 u32 __padding1; 268 u32 t_wl_add; 269 u32 mem_t_add; 270 u32 t_rl_add; 271 }; 272 #endif /* _SEQUENCER_H_ */ 273