1 /* 2 * Copyright Altera Corporation (C) 2012-2015 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _SEQUENCER_H_ 8 #define _SEQUENCER_H_ 9 10 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \ 11 / rwcfg->mem_if_write_dqs_width) 12 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \ 13 / rwcfg->mem_if_write_dqs_width) 14 15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \ 16 / rwcfg->mem_if_write_dqs_width) 17 #define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS) 18 19 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0 20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400 21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000 22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400 23 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800 24 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00 25 26 #define NUM_SHADOW_REGS 1 27 28 #define RW_MGR_RANK_NONE 0xFF 29 #define RW_MGR_RANK_ALL 0x00 30 31 #define RW_MGR_ODT_MODE_OFF 0 32 #define RW_MGR_ODT_MODE_READ_WRITE 1 33 34 #define NUM_CALIB_REPEAT 1 35 36 #define NUM_READ_TESTS 7 37 #define NUM_READ_PB_TESTS 7 38 #define NUM_WRITE_TESTS 15 39 #define NUM_WRITE_PB_TESTS 31 40 41 #define PASS_ALL_BITS 1 42 #define PASS_ONE_BIT 0 43 44 /* calibration stages */ 45 #define CAL_STAGE_NIL 0 46 #define CAL_STAGE_VFIFO 1 47 #define CAL_STAGE_WLEVEL 2 48 #define CAL_STAGE_LFIFO 3 49 #define CAL_STAGE_WRITES 4 50 #define CAL_STAGE_FULLTEST 5 51 #define CAL_STAGE_REFRESH 6 52 #define CAL_STAGE_CAL_SKIPPED 7 53 #define CAL_STAGE_CAL_ABORTED 8 54 #define CAL_STAGE_VFIFO_AFTER_WRITES 9 55 56 /* calibration substages */ 57 #define CAL_SUBSTAGE_NIL 0 58 #define CAL_SUBSTAGE_GUARANTEED_READ 1 59 #define CAL_SUBSTAGE_DQS_EN_PHASE 2 60 #define CAL_SUBSTAGE_VFIFO_CENTER 3 61 #define CAL_SUBSTAGE_WORKING_DELAY 1 62 #define CAL_SUBSTAGE_LAST_WORKING_DELAY 2 63 #define CAL_SUBSTAGE_WLEVEL_COPY 3 64 #define CAL_SUBSTAGE_WRITES_CENTER 1 65 #define CAL_SUBSTAGE_READ_LATENCY 1 66 #define CAL_SUBSTAGE_REFRESH 1 67 68 #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000 69 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100 70 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200 71 #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300 72 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400 73 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500 74 #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700 75 #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900 76 77 /* HHP-HPS-specific versions of some commands */ 78 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600 79 #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800 80 #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00 81 #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00 82 #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00 83 84 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0) 85 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000) 86 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000) 87 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000) 88 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800) 89 90 #define PHY_MGR_CAL_RESET (0) 91 #define PHY_MGR_CAL_SUCCESS (1) 92 #define PHY_MGR_CAL_FAIL (2) 93 94 #define CALIB_SKIP_DELAY_LOOPS (1 << 0) 95 #define CALIB_SKIP_ALL_BITS_CHK (1 << 1) 96 #define CALIB_SKIP_DELAY_SWEEPS (1 << 2) 97 #define CALIB_SKIP_VFIFO (1 << 3) 98 #define CALIB_SKIP_LFIFO (1 << 4) 99 #define CALIB_SKIP_WLEVEL (1 << 5) 100 #define CALIB_SKIP_WRITES (1 << 6) 101 #define CALIB_SKIP_FULL_TEST (1 << 7) 102 #define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \ 103 CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \ 104 CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST) 105 #define CALIB_IN_RTL_SIM (1 << 8) 106 107 /* Scan chain manager command addresses */ 108 #define READ_SCC_OCT_OUT2_DELAY 0 109 #define READ_SCC_DQ_OUT2_DELAY 0 110 #define READ_SCC_DQS_IO_OUT2_DELAY 0 111 #define READ_SCC_DM_IO_OUT2_DELAY 0 112 113 /* HHP-HPS-specific values */ 114 #define SCC_MGR_HHP_EXTRAS_OFFSET 0 115 #define SCC_MGR_HHP_DQSE_MAP_OFFSET 1 116 117 /* PHY Debug mode flag constants */ 118 #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001 119 #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002 120 #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004 121 #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008 122 #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010 123 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020 124 125 struct socfpga_sdr_rw_load_manager { 126 u32 load_cntr0; 127 u32 load_cntr1; 128 u32 load_cntr2; 129 u32 load_cntr3; 130 }; 131 132 struct socfpga_sdr_rw_load_jump_manager { 133 u32 load_jump_add0; 134 u32 load_jump_add1; 135 u32 load_jump_add2; 136 u32 load_jump_add3; 137 }; 138 139 struct socfpga_sdr_reg_file { 140 u32 signature; 141 u32 debug_data_addr; 142 u32 cur_stage; 143 u32 fom; 144 u32 failing_stage; 145 u32 debug1; 146 u32 debug2; 147 u32 dtaps_per_ptap; 148 u32 trk_sample_count; 149 u32 trk_longidle; 150 u32 delays; 151 u32 trk_rw_mgr_addr; 152 u32 trk_read_dqs_width; 153 u32 trk_rfsh; 154 }; 155 156 /* parameter variable holder */ 157 struct param_type { 158 u32 read_correct_mask; 159 u32 read_correct_mask_vg; 160 u32 write_correct_mask; 161 u32 write_correct_mask_vg; 162 }; 163 164 165 /* global variable holder */ 166 struct gbl_type { 167 uint32_t phy_debug_mode_flags; 168 169 /* current read latency */ 170 171 uint32_t curr_read_lat; 172 173 /* error code */ 174 175 uint32_t error_substage; 176 uint32_t error_stage; 177 uint32_t error_group; 178 179 /* figure-of-merit in, figure-of-merit out */ 180 181 uint32_t fom_in; 182 uint32_t fom_out; 183 184 /*USER Number of RW Mgr NOP cycles between 185 write command and write data */ 186 uint32_t rw_wl_nop_cycles; 187 }; 188 189 struct socfpga_sdr_scc_mgr { 190 u32 dqs_ena; 191 u32 dqs_io_ena; 192 u32 dq_ena; 193 u32 dm_ena; 194 u32 __padding1[4]; 195 u32 update; 196 u32 __padding2[7]; 197 u32 active_rank; 198 }; 199 200 /* PHY manager configuration registers. */ 201 struct socfpga_phy_mgr_cfg { 202 u32 phy_rlat; 203 u32 reset_mem_stbl; 204 u32 mux_sel; 205 u32 cal_status; 206 u32 cal_debug_info; 207 u32 vfifo_rd_en_ovrd; 208 u32 afi_wlat; 209 u32 afi_rlat; 210 }; 211 212 /* PHY manager command addresses. */ 213 struct socfpga_phy_mgr_cmd { 214 u32 inc_vfifo_fr; 215 u32 inc_vfifo_hard_phy; 216 u32 fifo_reset; 217 u32 inc_vfifo_fr_hr; 218 u32 inc_vfifo_qr; 219 }; 220 221 struct socfpga_data_mgr { 222 u32 __padding1; 223 u32 t_wl_add; 224 u32 mem_t_add; 225 u32 t_rl_add; 226 }; 227 #endif /* _SEQUENCER_H_ */ 228