1 /* 2 * Copyright Altera Corporation (C) 2012-2015 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _SEQUENCER_H_ 8 #define _SEQUENCER_H_ 9 10 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \ 11 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) 12 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \ 13 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) 14 15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH \ 16 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) 17 #define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS) 18 19 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0 20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400 21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000 22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400 23 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800 24 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00 25 26 #define RW_MGR_MEM_NUMBER_OF_RANKS 1 27 #define NUM_SHADOW_REGS 1 28 29 #define RW_MGR_RANK_NONE 0xFF 30 #define RW_MGR_RANK_ALL 0x00 31 32 #define RW_MGR_ODT_MODE_OFF 0 33 #define RW_MGR_ODT_MODE_READ_WRITE 1 34 35 #define NUM_CALIB_REPEAT 1 36 37 #define NUM_READ_TESTS 7 38 #define NUM_READ_PB_TESTS 7 39 #define NUM_WRITE_TESTS 15 40 #define NUM_WRITE_PB_TESTS 31 41 42 #define PASS_ALL_BITS 1 43 #define PASS_ONE_BIT 0 44 45 /* calibration stages */ 46 #define CAL_STAGE_NIL 0 47 #define CAL_STAGE_VFIFO 1 48 #define CAL_STAGE_WLEVEL 2 49 #define CAL_STAGE_LFIFO 3 50 #define CAL_STAGE_WRITES 4 51 #define CAL_STAGE_FULLTEST 5 52 #define CAL_STAGE_REFRESH 6 53 #define CAL_STAGE_CAL_SKIPPED 7 54 #define CAL_STAGE_CAL_ABORTED 8 55 #define CAL_STAGE_VFIFO_AFTER_WRITES 9 56 57 /* calibration substages */ 58 #define CAL_SUBSTAGE_NIL 0 59 #define CAL_SUBSTAGE_GUARANTEED_READ 1 60 #define CAL_SUBSTAGE_DQS_EN_PHASE 2 61 #define CAL_SUBSTAGE_VFIFO_CENTER 3 62 #define CAL_SUBSTAGE_WORKING_DELAY 1 63 #define CAL_SUBSTAGE_LAST_WORKING_DELAY 2 64 #define CAL_SUBSTAGE_WLEVEL_COPY 3 65 #define CAL_SUBSTAGE_WRITES_CENTER 1 66 #define CAL_SUBSTAGE_READ_LATENCY 1 67 #define CAL_SUBSTAGE_REFRESH 1 68 69 #define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS) 70 #define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > \ 71 RW_MGR_MEM_IF_READ_DQS_WIDTH ? \ 72 RW_MGR_MEM_IF_WRITE_DQS_WIDTH : \ 73 RW_MGR_MEM_IF_READ_DQS_WIDTH) 74 #define MAX_DQ (RW_MGR_MEM_DATA_WIDTH) 75 #define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH) 76 77 /* length of VFIFO, from SW_MACROS */ 78 #define VFIFO_SIZE (READ_VALID_FIFO_SIZE) 79 80 #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000 81 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100 82 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200 83 #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300 84 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400 85 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500 86 #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700 87 #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900 88 89 /* HHP-HPS-specific versions of some commands */ 90 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600 91 #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800 92 #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00 93 #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00 94 #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00 95 96 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0) 97 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000) 98 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000) 99 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000) 100 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800) 101 102 #define PHY_MGR_CAL_RESET (0) 103 #define PHY_MGR_CAL_SUCCESS (1) 104 #define PHY_MGR_CAL_FAIL (2) 105 106 #define CALIB_SKIP_DELAY_LOOPS (1 << 0) 107 #define CALIB_SKIP_ALL_BITS_CHK (1 << 1) 108 #define CALIB_SKIP_DELAY_SWEEPS (1 << 2) 109 #define CALIB_SKIP_VFIFO (1 << 3) 110 #define CALIB_SKIP_LFIFO (1 << 4) 111 #define CALIB_SKIP_WLEVEL (1 << 5) 112 #define CALIB_SKIP_WRITES (1 << 6) 113 #define CALIB_SKIP_FULL_TEST (1 << 7) 114 #define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \ 115 CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \ 116 CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST) 117 #define CALIB_IN_RTL_SIM (1 << 8) 118 119 /* Scan chain manager command addresses */ 120 #define READ_SCC_OCT_OUT2_DELAY 0 121 #define READ_SCC_DQ_OUT2_DELAY 0 122 #define READ_SCC_DQS_IO_OUT2_DELAY 0 123 #define READ_SCC_DM_IO_OUT2_DELAY 0 124 125 /* HHP-HPS-specific values */ 126 #define SCC_MGR_HHP_EXTRAS_OFFSET 0 127 #define SCC_MGR_HHP_DQSE_MAP_OFFSET 1 128 129 /* PHY Debug mode flag constants */ 130 #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001 131 #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002 132 #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004 133 #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008 134 #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010 135 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020 136 137 /* Init and Reset delay constants - Only use if defined by sequencer_defines.h, 138 * otherwise, revert to defaults 139 * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = 140 * 200.75us @ 266MHz 141 */ 142 #ifdef TINIT_CNTR0_VAL 143 #define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL 144 #else 145 #define SEQ_TINIT_CNTR0_VAL 0 146 #endif 147 148 #ifdef TINIT_CNTR1_VAL 149 #define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL 150 #else 151 #define SEQ_TINIT_CNTR1_VAL 202 152 #endif 153 154 #ifdef TINIT_CNTR2_VAL 155 #define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL 156 #else 157 #define SEQ_TINIT_CNTR2_VAL 131 158 #endif 159 160 161 /* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = 162 * 500.86us @ 266MHz 163 */ 164 #ifdef TRESET_CNTR0_VAL 165 #define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL 166 #else 167 #define SEQ_TRESET_CNTR0_VAL 2 168 #endif 169 170 #ifdef TRESET_CNTR1_VAL 171 #define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL 172 #else 173 #define SEQ_TRESET_CNTR1_VAL 252 174 #endif 175 176 #ifdef TRESET_CNTR2_VAL 177 #define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL 178 #else 179 #define SEQ_TRESET_CNTR2_VAL 131 180 #endif 181 182 struct socfpga_sdr_rw_load_manager { 183 u32 load_cntr0; 184 u32 load_cntr1; 185 u32 load_cntr2; 186 u32 load_cntr3; 187 }; 188 189 struct socfpga_sdr_rw_load_jump_manager { 190 u32 load_jump_add0; 191 u32 load_jump_add1; 192 u32 load_jump_add2; 193 u32 load_jump_add3; 194 }; 195 196 struct socfpga_sdr_reg_file { 197 u32 signature; 198 u32 debug_data_addr; 199 u32 cur_stage; 200 u32 fom; 201 u32 failing_stage; 202 u32 debug1; 203 u32 debug2; 204 u32 dtaps_per_ptap; 205 u32 trk_sample_count; 206 u32 trk_longidle; 207 u32 delays; 208 u32 trk_rw_mgr_addr; 209 u32 trk_read_dqs_width; 210 u32 trk_rfsh; 211 }; 212 213 /* parameter variable holder */ 214 struct param_type { 215 uint32_t dm_correct_mask; 216 uint32_t read_correct_mask; 217 uint32_t read_correct_mask_vg; 218 uint32_t write_correct_mask; 219 uint32_t write_correct_mask_vg; 220 221 /* set a particular entry to 1 if we need to skip a particular rank */ 222 223 uint32_t skip_ranks[MAX_RANKS]; 224 225 /* set a particular entry to 1 if we need to skip a particular group */ 226 227 uint32_t skip_groups; 228 229 /* set a particular entry to 1 if the shadow register 230 (which represents a set of ranks) needs to be skipped */ 231 232 uint32_t skip_shadow_regs[NUM_SHADOW_REGS]; 233 234 }; 235 236 237 /* global variable holder */ 238 struct gbl_type { 239 uint32_t phy_debug_mode_flags; 240 241 /* current read latency */ 242 243 uint32_t curr_read_lat; 244 245 /* current write latency */ 246 247 uint32_t curr_write_lat; 248 249 /* error code */ 250 251 uint32_t error_substage; 252 uint32_t error_stage; 253 uint32_t error_group; 254 255 /* figure-of-merit in, figure-of-merit out */ 256 257 uint32_t fom_in; 258 uint32_t fom_out; 259 260 /*USER Number of RW Mgr NOP cycles between 261 write command and write data */ 262 uint32_t rw_wl_nop_cycles; 263 }; 264 265 struct socfpga_sdr_scc_mgr { 266 u32 dqs_ena; 267 u32 dqs_io_ena; 268 u32 dq_ena; 269 u32 dm_ena; 270 u32 __padding1[4]; 271 u32 update; 272 u32 __padding2[7]; 273 u32 active_rank; 274 }; 275 276 /* PHY manager configuration registers. */ 277 struct socfpga_phy_mgr_cfg { 278 u32 phy_rlat; 279 u32 reset_mem_stbl; 280 u32 mux_sel; 281 u32 cal_status; 282 u32 cal_debug_info; 283 u32 vfifo_rd_en_ovrd; 284 u32 afi_wlat; 285 u32 afi_rlat; 286 }; 287 288 /* PHY manager command addresses. */ 289 struct socfpga_phy_mgr_cmd { 290 u32 inc_vfifo_fr; 291 u32 inc_vfifo_hard_phy; 292 u32 fifo_reset; 293 u32 inc_vfifo_fr_hr; 294 u32 inc_vfifo_qr; 295 }; 296 297 struct socfpga_data_mgr { 298 u32 __padding1; 299 u32 t_wl_add; 300 u32 mem_t_add; 301 u32 t_rl_add; 302 }; 303 #endif /* _SEQUENCER_H_ */ 304