1 /* 2 * Copyright Altera Corporation (C) 2012-2015 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _SEQUENCER_H_ 8 #define _SEQUENCER_H_ 9 10 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \ 11 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) 12 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \ 13 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) 14 15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH \ 16 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) 17 #define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS) 18 19 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0 20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400 21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000 22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400 23 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800 24 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00 25 26 #define NUM_SHADOW_REGS 1 27 28 #define RW_MGR_RANK_NONE 0xFF 29 #define RW_MGR_RANK_ALL 0x00 30 31 #define RW_MGR_ODT_MODE_OFF 0 32 #define RW_MGR_ODT_MODE_READ_WRITE 1 33 34 #define NUM_CALIB_REPEAT 1 35 36 #define NUM_READ_TESTS 7 37 #define NUM_READ_PB_TESTS 7 38 #define NUM_WRITE_TESTS 15 39 #define NUM_WRITE_PB_TESTS 31 40 41 #define PASS_ALL_BITS 1 42 #define PASS_ONE_BIT 0 43 44 /* calibration stages */ 45 #define CAL_STAGE_NIL 0 46 #define CAL_STAGE_VFIFO 1 47 #define CAL_STAGE_WLEVEL 2 48 #define CAL_STAGE_LFIFO 3 49 #define CAL_STAGE_WRITES 4 50 #define CAL_STAGE_FULLTEST 5 51 #define CAL_STAGE_REFRESH 6 52 #define CAL_STAGE_CAL_SKIPPED 7 53 #define CAL_STAGE_CAL_ABORTED 8 54 #define CAL_STAGE_VFIFO_AFTER_WRITES 9 55 56 /* calibration substages */ 57 #define CAL_SUBSTAGE_NIL 0 58 #define CAL_SUBSTAGE_GUARANTEED_READ 1 59 #define CAL_SUBSTAGE_DQS_EN_PHASE 2 60 #define CAL_SUBSTAGE_VFIFO_CENTER 3 61 #define CAL_SUBSTAGE_WORKING_DELAY 1 62 #define CAL_SUBSTAGE_LAST_WORKING_DELAY 2 63 #define CAL_SUBSTAGE_WLEVEL_COPY 3 64 #define CAL_SUBSTAGE_WRITES_CENTER 1 65 #define CAL_SUBSTAGE_READ_LATENCY 1 66 #define CAL_SUBSTAGE_REFRESH 1 67 68 /* length of VFIFO, from SW_MACROS */ 69 #define VFIFO_SIZE (READ_VALID_FIFO_SIZE) 70 71 #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000 72 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100 73 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200 74 #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300 75 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400 76 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500 77 #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700 78 #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900 79 80 /* HHP-HPS-specific versions of some commands */ 81 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600 82 #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800 83 #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00 84 #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00 85 #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00 86 87 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0) 88 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000) 89 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000) 90 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000) 91 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800) 92 93 #define PHY_MGR_CAL_RESET (0) 94 #define PHY_MGR_CAL_SUCCESS (1) 95 #define PHY_MGR_CAL_FAIL (2) 96 97 #define CALIB_SKIP_DELAY_LOOPS (1 << 0) 98 #define CALIB_SKIP_ALL_BITS_CHK (1 << 1) 99 #define CALIB_SKIP_DELAY_SWEEPS (1 << 2) 100 #define CALIB_SKIP_VFIFO (1 << 3) 101 #define CALIB_SKIP_LFIFO (1 << 4) 102 #define CALIB_SKIP_WLEVEL (1 << 5) 103 #define CALIB_SKIP_WRITES (1 << 6) 104 #define CALIB_SKIP_FULL_TEST (1 << 7) 105 #define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \ 106 CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \ 107 CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST) 108 #define CALIB_IN_RTL_SIM (1 << 8) 109 110 /* Scan chain manager command addresses */ 111 #define READ_SCC_OCT_OUT2_DELAY 0 112 #define READ_SCC_DQ_OUT2_DELAY 0 113 #define READ_SCC_DQS_IO_OUT2_DELAY 0 114 #define READ_SCC_DM_IO_OUT2_DELAY 0 115 116 /* HHP-HPS-specific values */ 117 #define SCC_MGR_HHP_EXTRAS_OFFSET 0 118 #define SCC_MGR_HHP_DQSE_MAP_OFFSET 1 119 120 /* PHY Debug mode flag constants */ 121 #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001 122 #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002 123 #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004 124 #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008 125 #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010 126 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020 127 128 /* Init and Reset delay constants - Only use if defined by sequencer_defines.h, 129 * otherwise, revert to defaults 130 * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = 131 * 200.75us @ 266MHz 132 */ 133 #ifdef TINIT_CNTR0_VAL 134 #define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL 135 #else 136 #define SEQ_TINIT_CNTR0_VAL 0 137 #endif 138 139 #ifdef TINIT_CNTR1_VAL 140 #define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL 141 #else 142 #define SEQ_TINIT_CNTR1_VAL 202 143 #endif 144 145 #ifdef TINIT_CNTR2_VAL 146 #define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL 147 #else 148 #define SEQ_TINIT_CNTR2_VAL 131 149 #endif 150 151 152 /* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = 153 * 500.86us @ 266MHz 154 */ 155 #ifdef TRESET_CNTR0_VAL 156 #define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL 157 #else 158 #define SEQ_TRESET_CNTR0_VAL 2 159 #endif 160 161 #ifdef TRESET_CNTR1_VAL 162 #define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL 163 #else 164 #define SEQ_TRESET_CNTR1_VAL 252 165 #endif 166 167 #ifdef TRESET_CNTR2_VAL 168 #define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL 169 #else 170 #define SEQ_TRESET_CNTR2_VAL 131 171 #endif 172 173 struct socfpga_sdr_rw_load_manager { 174 u32 load_cntr0; 175 u32 load_cntr1; 176 u32 load_cntr2; 177 u32 load_cntr3; 178 }; 179 180 struct socfpga_sdr_rw_load_jump_manager { 181 u32 load_jump_add0; 182 u32 load_jump_add1; 183 u32 load_jump_add2; 184 u32 load_jump_add3; 185 }; 186 187 struct socfpga_sdr_reg_file { 188 u32 signature; 189 u32 debug_data_addr; 190 u32 cur_stage; 191 u32 fom; 192 u32 failing_stage; 193 u32 debug1; 194 u32 debug2; 195 u32 dtaps_per_ptap; 196 u32 trk_sample_count; 197 u32 trk_longidle; 198 u32 delays; 199 u32 trk_rw_mgr_addr; 200 u32 trk_read_dqs_width; 201 u32 trk_rfsh; 202 }; 203 204 /* parameter variable holder */ 205 struct param_type { 206 u32 read_correct_mask; 207 u32 read_correct_mask_vg; 208 u32 write_correct_mask; 209 u32 write_correct_mask_vg; 210 }; 211 212 213 /* global variable holder */ 214 struct gbl_type { 215 uint32_t phy_debug_mode_flags; 216 217 /* current read latency */ 218 219 uint32_t curr_read_lat; 220 221 /* error code */ 222 223 uint32_t error_substage; 224 uint32_t error_stage; 225 uint32_t error_group; 226 227 /* figure-of-merit in, figure-of-merit out */ 228 229 uint32_t fom_in; 230 uint32_t fom_out; 231 232 /*USER Number of RW Mgr NOP cycles between 233 write command and write data */ 234 uint32_t rw_wl_nop_cycles; 235 }; 236 237 struct socfpga_sdr_scc_mgr { 238 u32 dqs_ena; 239 u32 dqs_io_ena; 240 u32 dq_ena; 241 u32 dm_ena; 242 u32 __padding1[4]; 243 u32 update; 244 u32 __padding2[7]; 245 u32 active_rank; 246 }; 247 248 /* PHY manager configuration registers. */ 249 struct socfpga_phy_mgr_cfg { 250 u32 phy_rlat; 251 u32 reset_mem_stbl; 252 u32 mux_sel; 253 u32 cal_status; 254 u32 cal_debug_info; 255 u32 vfifo_rd_en_ovrd; 256 u32 afi_wlat; 257 u32 afi_rlat; 258 }; 259 260 /* PHY manager command addresses. */ 261 struct socfpga_phy_mgr_cmd { 262 u32 inc_vfifo_fr; 263 u32 inc_vfifo_hard_phy; 264 u32 fifo_reset; 265 u32 inc_vfifo_fr_hr; 266 u32 inc_vfifo_qr; 267 }; 268 269 struct socfpga_data_mgr { 270 u32 __padding1; 271 u32 t_wl_add; 272 u32 mem_t_add; 273 u32 t_rl_add; 274 }; 275 #endif /* _SEQUENCER_H_ */ 276