1 /* 2 * Copyright Altera Corporation (C) 2012-2015 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _SEQUENCER_H_ 8 #define _SEQUENCER_H_ 9 10 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \ 11 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) 12 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \ 13 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) 14 15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH \ 16 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) 17 #define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS) 18 19 #define RW_MGR_RUN_SINGLE_GROUP (BASE_RW_MGR) 20 #define RW_MGR_RUN_ALL_GROUPS (BASE_RW_MGR + 0x0400) 21 22 #define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0020) 23 24 #define RW_MGR_MEM_NUMBER_OF_RANKS 1 25 #define NUM_SHADOW_REGS 1 26 27 #define RW_MGR_RESET_READ_DATAPATH (BASE_RW_MGR + 0x1000) 28 #define RW_MGR_SET_CS_AND_ODT_MASK (BASE_RW_MGR + 0x1400) 29 30 #define RW_MGR_RANK_NONE 0xFF 31 #define RW_MGR_RANK_ALL 0x00 32 33 #define RW_MGR_ODT_MODE_OFF 0 34 #define RW_MGR_ODT_MODE_READ_WRITE 1 35 36 #define NUM_CALIB_REPEAT 1 37 38 #define NUM_READ_TESTS 7 39 #define NUM_READ_PB_TESTS 7 40 #define NUM_WRITE_TESTS 15 41 #define NUM_WRITE_PB_TESTS 31 42 43 #define PASS_ALL_BITS 1 44 #define PASS_ONE_BIT 0 45 46 /* calibration stages */ 47 #define CAL_STAGE_NIL 0 48 #define CAL_STAGE_VFIFO 1 49 #define CAL_STAGE_WLEVEL 2 50 #define CAL_STAGE_LFIFO 3 51 #define CAL_STAGE_WRITES 4 52 #define CAL_STAGE_FULLTEST 5 53 #define CAL_STAGE_REFRESH 6 54 #define CAL_STAGE_CAL_SKIPPED 7 55 #define CAL_STAGE_CAL_ABORTED 8 56 #define CAL_STAGE_VFIFO_AFTER_WRITES 9 57 58 /* calibration substages */ 59 #define CAL_SUBSTAGE_NIL 0 60 #define CAL_SUBSTAGE_GUARANTEED_READ 1 61 #define CAL_SUBSTAGE_DQS_EN_PHASE 2 62 #define CAL_SUBSTAGE_VFIFO_CENTER 3 63 #define CAL_SUBSTAGE_WORKING_DELAY 1 64 #define CAL_SUBSTAGE_LAST_WORKING_DELAY 2 65 #define CAL_SUBSTAGE_WLEVEL_COPY 3 66 #define CAL_SUBSTAGE_WRITES_CENTER 1 67 #define CAL_SUBSTAGE_READ_LATENCY 1 68 #define CAL_SUBSTAGE_REFRESH 1 69 70 #define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS) 71 #define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > \ 72 RW_MGR_MEM_IF_READ_DQS_WIDTH ? \ 73 RW_MGR_MEM_IF_WRITE_DQS_WIDTH : \ 74 RW_MGR_MEM_IF_READ_DQS_WIDTH) 75 #define MAX_DQ (RW_MGR_MEM_DATA_WIDTH) 76 #define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH) 77 78 /* length of VFIFO, from SW_MACROS */ 79 #define VFIFO_SIZE (READ_VALID_FIFO_SIZE) 80 81 /* MarkW: how should these base addresses be done for A-V? */ 82 #define BASE_PTR_MGR 0x00040000 83 #define BASE_SCC_MGR 0x00058000 84 #define BASE_REG_FILE 0x00070000 85 #define BASE_TIMER 0x00078000 86 #define BASE_PHY_MGR 0x00088000 87 #define BASE_RW_MGR 0x00090000 88 #define BASE_DATA_MGR 0x00098000 89 #define BASE_MMR 0x000C0000 90 #define BASE_TRK_MGR 0x000D0000 91 92 #define SCC_MGR_GROUP_COUNTER (BASE_SCC_MGR + 0x0000) 93 #define SCC_MGR_DQS_IN_DELAY (BASE_SCC_MGR + 0x0100) 94 #define SCC_MGR_DQS_EN_PHASE (BASE_SCC_MGR + 0x0200) 95 #define SCC_MGR_DQS_EN_DELAY (BASE_SCC_MGR + 0x0300) 96 #define SCC_MGR_DQDQS_OUT_PHASE (BASE_SCC_MGR + 0x0400) 97 #define SCC_MGR_OCT_OUT1_DELAY (BASE_SCC_MGR + 0x0500) 98 #define SCC_MGR_IO_OUT1_DELAY (BASE_SCC_MGR + 0x0700) 99 #define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900) 100 101 /* HHP-HPS-specific versions of some commands */ 102 #define SCC_MGR_DQS_EN_DELAY_GATE (BASE_SCC_MGR + 0x0600) 103 #define SCC_MGR_IO_OE_DELAY (BASE_SCC_MGR + 0x0800) 104 #define SCC_MGR_HHP_GLOBALS (BASE_SCC_MGR + 0x0A00) 105 #define SCC_MGR_HHP_RFILE (BASE_SCC_MGR + 0x0B00) 106 #define SCC_MGR_AFI_CAL_INIT (BASE_SCC_MGR + 0x0D00) 107 108 #define SDR_PHYGRP_SCCGRP_ADDRESS 0x0 109 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000 110 #define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000 111 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000 112 #define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800 113 114 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150 115 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154 116 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158 117 118 #define PHY_MGR_CAL_RESET (0) 119 #define PHY_MGR_CAL_SUCCESS (1) 120 #define PHY_MGR_CAL_FAIL (2) 121 122 #define CALIB_SKIP_DELAY_LOOPS (1 << 0) 123 #define CALIB_SKIP_ALL_BITS_CHK (1 << 1) 124 #define CALIB_SKIP_DELAY_SWEEPS (1 << 2) 125 #define CALIB_SKIP_VFIFO (1 << 3) 126 #define CALIB_SKIP_LFIFO (1 << 4) 127 #define CALIB_SKIP_WLEVEL (1 << 5) 128 #define CALIB_SKIP_WRITES (1 << 6) 129 #define CALIB_SKIP_FULL_TEST (1 << 7) 130 #define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \ 131 CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \ 132 CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST) 133 #define CALIB_IN_RTL_SIM (1 << 8) 134 135 /* Scan chain manager command addresses */ 136 #define READ_SCC_OCT_OUT2_DELAY 0 137 #define READ_SCC_DQ_OUT2_DELAY 0 138 #define READ_SCC_DQS_IO_OUT2_DELAY 0 139 #define READ_SCC_DM_IO_OUT2_DELAY 0 140 141 /* HHP-HPS-specific values */ 142 #define SCC_MGR_HHP_EXTRAS_OFFSET 0 143 #define SCC_MGR_HHP_DQSE_MAP_OFFSET 1 144 145 /* PHY Debug mode flag constants */ 146 #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001 147 #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002 148 #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004 149 #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008 150 #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010 151 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020 152 153 /* Init and Reset delay constants - Only use if defined by sequencer_defines.h, 154 * otherwise, revert to defaults 155 * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = 156 * 200.75us @ 266MHz 157 */ 158 #ifdef TINIT_CNTR0_VAL 159 #define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL 160 #else 161 #define SEQ_TINIT_CNTR0_VAL 0 162 #endif 163 164 #ifdef TINIT_CNTR1_VAL 165 #define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL 166 #else 167 #define SEQ_TINIT_CNTR1_VAL 202 168 #endif 169 170 #ifdef TINIT_CNTR2_VAL 171 #define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL 172 #else 173 #define SEQ_TINIT_CNTR2_VAL 131 174 #endif 175 176 177 /* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = 178 * 500.86us @ 266MHz 179 */ 180 #ifdef TRESET_CNTR0_VAL 181 #define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL 182 #else 183 #define SEQ_TRESET_CNTR0_VAL 2 184 #endif 185 186 #ifdef TRESET_CNTR1_VAL 187 #define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL 188 #else 189 #define SEQ_TRESET_CNTR1_VAL 252 190 #endif 191 192 #ifdef TRESET_CNTR2_VAL 193 #define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL 194 #else 195 #define SEQ_TRESET_CNTR2_VAL 131 196 #endif 197 198 #define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800 199 #define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00 200 201 struct socfpga_sdr_rw_load_manager { 202 u32 load_cntr0; 203 u32 load_cntr1; 204 u32 load_cntr2; 205 u32 load_cntr3; 206 }; 207 208 struct socfpga_sdr_rw_load_jump_manager { 209 u32 load_jump_add0; 210 u32 load_jump_add1; 211 u32 load_jump_add2; 212 u32 load_jump_add3; 213 }; 214 215 struct socfpga_sdr_reg_file { 216 u32 signature; 217 u32 debug_data_addr; 218 u32 cur_stage; 219 u32 fom; 220 u32 failing_stage; 221 u32 debug1; 222 u32 debug2; 223 u32 dtaps_per_ptap; 224 u32 trk_sample_count; 225 u32 trk_longidle; 226 u32 delays; 227 u32 trk_rw_mgr_addr; 228 u32 trk_read_dqs_width; 229 u32 trk_rfsh; 230 }; 231 232 /* parameter variable holder */ 233 struct param_type { 234 uint32_t dm_correct_mask; 235 uint32_t read_correct_mask; 236 uint32_t read_correct_mask_vg; 237 uint32_t write_correct_mask; 238 uint32_t write_correct_mask_vg; 239 240 /* set a particular entry to 1 if we need to skip a particular rank */ 241 242 uint32_t skip_ranks[MAX_RANKS]; 243 244 /* set a particular entry to 1 if we need to skip a particular group */ 245 246 uint32_t skip_groups; 247 248 /* set a particular entry to 1 if the shadow register 249 (which represents a set of ranks) needs to be skipped */ 250 251 uint32_t skip_shadow_regs[NUM_SHADOW_REGS]; 252 253 }; 254 255 256 /* global variable holder */ 257 struct gbl_type { 258 uint32_t phy_debug_mode_flags; 259 260 /* current read latency */ 261 262 uint32_t curr_read_lat; 263 264 /* current write latency */ 265 266 uint32_t curr_write_lat; 267 268 /* error code */ 269 270 uint32_t error_substage; 271 uint32_t error_stage; 272 uint32_t error_group; 273 274 /* figure-of-merit in, figure-of-merit out */ 275 276 uint32_t fom_in; 277 uint32_t fom_out; 278 279 /*USER Number of RW Mgr NOP cycles between 280 write command and write data */ 281 uint32_t rw_wl_nop_cycles; 282 }; 283 284 struct socfpga_sdr_scc_mgr { 285 u32 dqs_ena; 286 u32 dqs_io_ena; 287 u32 dq_ena; 288 u32 dm_ena; 289 u32 __padding1[4]; 290 u32 update; 291 u32 __padding2[7]; 292 u32 active_rank; 293 }; 294 295 /* PHY manager configuration registers. */ 296 struct socfpga_phy_mgr_cfg { 297 u32 phy_rlat; 298 u32 reset_mem_stbl; 299 u32 mux_sel; 300 u32 cal_status; 301 u32 cal_debug_info; 302 u32 vfifo_rd_en_ovrd; 303 u32 afi_wlat; 304 u32 afi_rlat; 305 }; 306 307 /* PHY manager command addresses. */ 308 struct socfpga_phy_mgr_cmd { 309 u32 inc_vfifo_fr; 310 u32 inc_vfifo_hard_phy; 311 u32 fifo_reset; 312 u32 inc_vfifo_fr_hr; 313 u32 inc_vfifo_qr; 314 }; 315 316 struct socfpga_data_mgr { 317 u32 __padding1; 318 u32 t_wl_add; 319 u32 mem_t_add; 320 u32 t_rl_add; 321 }; 322 #endif /* _SEQUENCER_H_ */ 323