1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 */ 7 8 #ifndef __JR_H 9 #define __JR_H 10 11 #include <linux/compiler.h> 12 13 #define JR_SIZE 4 14 /* Timeout currently defined as 90 sec */ 15 #define CONFIG_SEC_DEQ_TIMEOUT 90000000U 16 17 #define DEFAULT_JR_ID 0 18 #define DEFAULT_JR_LIODN 0 19 #define DEFAULT_IRQ 0 /* Interrupts not to be configured */ 20 21 #define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */ 22 #define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */ 23 #define MCFGR_PS_SHIFT 16 24 #define MCFGR_AWCACHE_SHIFT 8 25 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) 26 #define MCFGR_ARCACHE_SHIFT 12 27 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) 28 29 #define JR_INTMASK 0x00000001 30 #define JRCR_RESET 0x01 31 #define JRINT_ERR_HALT_INPROGRESS 0x4 32 #define JRINT_ERR_HALT_MASK 0xc 33 #define JRNSLIODN_SHIFT 16 34 #define JRNSLIODN_MASK 0x0fff0000 35 #define JRSLIODN_SHIFT 0 36 #define JRSLIODN_MASK 0x00000fff 37 #define JROWN_NS 0x00000008 38 #define JRMID_NS 0x00000001 39 40 #define JQ_DEQ_ERR -1 41 #define JQ_DEQ_TO_ERR -2 42 #define JQ_ENQ_ERR -3 43 44 #define RNG4_MAX_HANDLES 2 45 46 struct op_ring { 47 phys_addr_t desc; 48 uint32_t status; 49 } __packed; 50 51 struct jr_info { 52 void (*callback)(uint32_t status, void *arg); 53 phys_addr_t desc_phys_addr; 54 uint32_t desc_len; 55 uint32_t op_done; 56 void *arg; 57 }; 58 59 struct jobring { 60 int jq_id; 61 int irq; 62 int liodn; 63 /* Head is the index where software would enq the descriptor in 64 * the i/p ring 65 */ 66 int head; 67 /* Tail index would be used by s/w ehile enqueuing to determine if 68 * there is any space left in the s/w maintained i/p rings 69 */ 70 /* Also in case of deq tail will be incremented only in case of 71 * in-order job completion 72 */ 73 int tail; 74 /* Read index of the output ring. It may not match with tail in case 75 * of out of order completetion 76 */ 77 int read_idx; 78 /* Write index to input ring. Would be always equal to head */ 79 int write_idx; 80 /* Size of the rings. */ 81 int size; 82 /* Op ring size aligned to cache line size */ 83 int op_size; 84 /* The ip and output rings have to be accessed by SEC. So the 85 * pointers will ahve to point to the housekeeping region provided 86 * by SEC 87 */ 88 /*Circular Ring of i/p descriptors */ 89 dma_addr_t *input_ring; 90 /* Circular Ring of o/p descriptors */ 91 /* Circula Ring containing info regarding descriptors in i/p 92 * and o/p ring 93 */ 94 /* This ring can be on the stack */ 95 struct jr_info info[JR_SIZE]; 96 struct op_ring *output_ring; 97 /* Offset in CCSR to the SEC engine to which this JR belongs */ 98 uint32_t sec_offset; 99 100 }; 101 102 struct result { 103 int done; 104 uint32_t status; 105 }; 106 107 void caam_jr_strstatus(u32 status); 108 int run_descriptor_jr(uint32_t *desc); 109 110 #endif 111