1833508c0SBin Meng // SPDX-License-Identifier: GPL-2.0+
2833508c0SBin Meng /*
3833508c0SBin Meng * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4833508c0SBin Meng */
5833508c0SBin Meng
6833508c0SBin Meng #include <common.h>
7833508c0SBin Meng #include <cpu.h>
8833508c0SBin Meng #include <dm.h>
9833508c0SBin Meng #include <errno.h>
10833508c0SBin Meng #include <dm/device-internal.h>
11833508c0SBin Meng #include <dm/lists.h>
12833508c0SBin Meng
13*007056f4SAtish Patra DECLARE_GLOBAL_DATA_PTR;
14*007056f4SAtish Patra
riscv_cpu_get_desc(struct udevice * dev,char * buf,int size)15833508c0SBin Meng static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
16833508c0SBin Meng {
17833508c0SBin Meng const char *isa;
18833508c0SBin Meng
19833508c0SBin Meng isa = dev_read_string(dev, "riscv,isa");
20833508c0SBin Meng if (size < (strlen(isa) + 1))
21833508c0SBin Meng return -ENOSPC;
22833508c0SBin Meng
23833508c0SBin Meng strcpy(buf, isa);
24833508c0SBin Meng
25833508c0SBin Meng return 0;
26833508c0SBin Meng }
27833508c0SBin Meng
riscv_cpu_get_info(struct udevice * dev,struct cpu_info * info)28833508c0SBin Meng static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
29833508c0SBin Meng {
30833508c0SBin Meng const char *mmu;
31833508c0SBin Meng
32833508c0SBin Meng dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
33833508c0SBin Meng
34833508c0SBin Meng mmu = dev_read_string(dev, "mmu-type");
35833508c0SBin Meng if (!mmu)
36833508c0SBin Meng info->features |= BIT(CPU_FEAT_MMU);
37833508c0SBin Meng
38833508c0SBin Meng return 0;
39833508c0SBin Meng }
40833508c0SBin Meng
riscv_cpu_get_count(struct udevice * dev)41833508c0SBin Meng static int riscv_cpu_get_count(struct udevice *dev)
42833508c0SBin Meng {
43833508c0SBin Meng ofnode node;
44833508c0SBin Meng int num = 0;
45833508c0SBin Meng
46833508c0SBin Meng ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
47833508c0SBin Meng const char *device_type;
48833508c0SBin Meng
49833508c0SBin Meng device_type = ofnode_read_string(node, "device_type");
50833508c0SBin Meng if (!device_type)
51833508c0SBin Meng continue;
52833508c0SBin Meng if (strcmp(device_type, "cpu") == 0)
53833508c0SBin Meng num++;
54833508c0SBin Meng }
55833508c0SBin Meng
56833508c0SBin Meng return num;
57833508c0SBin Meng }
58833508c0SBin Meng
riscv_cpu_bind(struct udevice * dev)59833508c0SBin Meng static int riscv_cpu_bind(struct udevice *dev)
60833508c0SBin Meng {
61833508c0SBin Meng struct cpu_platdata *plat = dev_get_parent_platdata(dev);
62833508c0SBin Meng struct driver *drv;
63833508c0SBin Meng int ret;
64833508c0SBin Meng
65833508c0SBin Meng /* save the hart id */
66833508c0SBin Meng plat->cpu_id = dev_read_addr(dev);
67833508c0SBin Meng /* first examine the property in current cpu node */
68833508c0SBin Meng ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
69833508c0SBin Meng /* if not found, then look at the parent /cpus node */
70833508c0SBin Meng if (ret)
71833508c0SBin Meng dev_read_u32(dev->parent, "timebase-frequency",
72833508c0SBin Meng &plat->timebase_freq);
73833508c0SBin Meng
74833508c0SBin Meng /*
75*007056f4SAtish Patra * Bind riscv-timer driver on boot hart.
76833508c0SBin Meng *
77833508c0SBin Meng * We only instantiate one timer device which is enough for U-Boot.
78833508c0SBin Meng * Pass the "timebase-frequency" value as the driver data for the
79833508c0SBin Meng * timer device.
80833508c0SBin Meng *
81833508c0SBin Meng * Return value is not checked since it's possible that the timer
82833508c0SBin Meng * driver is not included.
83833508c0SBin Meng */
84*007056f4SAtish Patra if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
85833508c0SBin Meng drv = lists_driver_lookup_name("riscv_timer");
86833508c0SBin Meng if (!drv) {
87833508c0SBin Meng debug("Cannot find the timer driver, not included?\n");
88833508c0SBin Meng return 0;
89833508c0SBin Meng }
90833508c0SBin Meng
91833508c0SBin Meng device_bind_with_driver_data(dev, drv, "riscv_timer",
92833508c0SBin Meng plat->timebase_freq, ofnode_null(),
93833508c0SBin Meng NULL);
94833508c0SBin Meng }
95833508c0SBin Meng
96833508c0SBin Meng return 0;
97833508c0SBin Meng }
98833508c0SBin Meng
99833508c0SBin Meng static const struct cpu_ops riscv_cpu_ops = {
100833508c0SBin Meng .get_desc = riscv_cpu_get_desc,
101833508c0SBin Meng .get_info = riscv_cpu_get_info,
102833508c0SBin Meng .get_count = riscv_cpu_get_count,
103833508c0SBin Meng };
104833508c0SBin Meng
105833508c0SBin Meng static const struct udevice_id riscv_cpu_ids[] = {
106833508c0SBin Meng { .compatible = "riscv" },
107833508c0SBin Meng { }
108833508c0SBin Meng };
109833508c0SBin Meng
110833508c0SBin Meng U_BOOT_DRIVER(riscv_cpu) = {
111833508c0SBin Meng .name = "riscv_cpu",
112833508c0SBin Meng .id = UCLASS_CPU,
113833508c0SBin Meng .of_match = riscv_cpu_ids,
114833508c0SBin Meng .bind = riscv_cpu_bind,
115833508c0SBin Meng .ops = &riscv_cpu_ops,
116833508c0SBin Meng .flags = DM_FLAG_PRE_RELOC,
117833508c0SBin Meng };
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