xref: /openbmc/u-boot/drivers/cpu/bmips_cpu.c (revision e3f44f5c)
1 /*
2  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
3  *
4  * Derived from linux/arch/mips/bcm63xx/cpu.c:
5  *	Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
6  *	Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #include <common.h>
12 #include <cpu.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <asm/io.h>
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 #define REV_CHIPID_SHIFT		16
20 #define REV_CHIPID_MASK			(0xffff << REV_CHIPID_SHIFT)
21 #define REV_LONG_CHIPID_SHIFT		12
22 #define REV_LONG_CHIPID_MASK		(0xfffff << REV_LONG_CHIPID_SHIFT)
23 #define REV_REVID_SHIFT			0
24 #define REV_REVID_MASK			(0xff << REV_REVID_SHIFT)
25 
26 #define REG_BCM6328_OTP			0x62c
27 #define BCM6328_TP1_DISABLED		BIT(9)
28 
29 #define REG_BCM6328_MISC_STRAPBUS	0x1a40
30 #define STRAPBUS_6328_FCVO_SHIFT	7
31 #define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
32 
33 #define REG_BCM6348_PERF_MIPSPLLCFG	0x34
34 #define MIPSPLLCFG_6348_M1CPU_SHIFT	6
35 #define MIPSPLLCFG_6348_M1CPU_MASK	(0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
36 #define MIPSPLLCFG_6348_N2_SHIFT	15
37 #define MIPSPLLCFG_6348_N2_MASK		(0x1F << MIPSPLLCFG_6348_N2_SHIFT)
38 #define MIPSPLLCFG_6348_N1_SHIFT	20
39 #define MIPSPLLCFG_6348_N1_MASK		(0x7 << MIPSPLLCFG_6348_N1_SHIFT)
40 
41 #define REG_BCM6358_DDR_DMIPSPLLCFG	0x12b8
42 #define DMIPSPLLCFG_6358_M1_SHIFT	0
43 #define DMIPSPLLCFG_6358_M1_MASK	(0xff << DMIPSPLLCFG_6358_M1_SHIFT)
44 #define DMIPSPLLCFG_6358_N1_SHIFT	23
45 #define DMIPSPLLCFG_6358_N1_MASK	(0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
46 #define DMIPSPLLCFG_6358_N2_SHIFT	29
47 #define DMIPSPLLCFG_6358_N2_MASK	(0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
48 
49 #define REG_BCM63268_MISC_STRAPBUS	0x1814
50 #define STRAPBUS_63268_FCVO_SHIFT	21
51 #define STRAPBUS_63268_FCVO_MASK	(0xf << STRAPBUS_63268_FCVO_SHIFT)
52 
53 struct bmips_cpu_priv;
54 
55 struct bmips_cpu_hw {
56 	int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
57 	ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
58 	int (*get_cpu_count)(struct bmips_cpu_priv *);
59 };
60 
61 struct bmips_cpu_priv {
62 	void __iomem *regs;
63 	const struct bmips_cpu_hw *hw;
64 };
65 
66 /* Specific CPU Ops */
67 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
68 				int size)
69 {
70 	unsigned short cpu_id;
71 	unsigned char cpu_rev;
72 	u32 val;
73 
74 	val = readl_be(priv->regs);
75 	cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
76 	cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
77 
78 	snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
79 
80 	return 0;
81 }
82 
83 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
84 				int size)
85 {
86 	unsigned int cpu_id;
87 	unsigned char cpu_rev;
88 	u32 val;
89 
90 	val = readl_be(priv->regs);
91 	cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
92 	cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
93 
94 	snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
95 
96 	return 0;
97 }
98 
99 static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
100 {
101 	return 333000000;
102 }
103 
104 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
105 {
106 	unsigned int mips_pll_fcvo;
107 
108 	mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
109 	mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
110 			>> STRAPBUS_6328_FCVO_SHIFT;
111 
112 	switch (mips_pll_fcvo) {
113 	case 0x12:
114 	case 0x14:
115 	case 0x19:
116 		return 160000000;
117 	case 0x1c:
118 		return 192000000;
119 	case 0x13:
120 	case 0x15:
121 		return 200000000;
122 	case 0x1a:
123 		return 384000000;
124 	case 0x16:
125 		return 400000000;
126 	default:
127 		return 320000000;
128 	}
129 }
130 
131 static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv)
132 {
133 	return 240000000;
134 }
135 
136 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
137 {
138 	unsigned int tmp, n1, n2, m1;
139 
140 	tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
141 	n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
142 	n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
143 	m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
144 
145 	return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
146 }
147 
148 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
149 {
150 	unsigned int tmp, n1, n2, m1;
151 
152 	tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
153 	n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
154 	n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
155 	m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
156 
157 	return (16 * 1000000 * n1 * n2) / m1;
158 }
159 
160 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
161 {
162 	unsigned int mips_pll_fcvo;
163 
164 	mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
165 	mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
166 			>> STRAPBUS_63268_FCVO_SHIFT;
167 
168 	switch (mips_pll_fcvo) {
169 	case 0x3:
170 	case 0xe:
171 		return 320000000;
172 	case 0xa:
173 		return 333000000;
174 	case 0x2:
175 	case 0xb:
176 	case 0xf:
177 		return 400000000;
178 	default:
179 		return 0;
180 	}
181 }
182 
183 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
184 {
185 	u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
186 
187 	if (val & BCM6328_TP1_DISABLED)
188 		return 1;
189 	else
190 		return 2;
191 }
192 
193 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
194 {
195 	return 1;
196 }
197 
198 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
199 {
200 	return 2;
201 }
202 
203 static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
204 	.get_cpu_desc = bmips_short_cpu_desc,
205 	.get_cpu_freq = bcm3380_get_cpu_freq,
206 	.get_cpu_count = bcm6358_get_cpu_count,
207 };
208 
209 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
210 	.get_cpu_desc = bmips_long_cpu_desc,
211 	.get_cpu_freq = bcm6328_get_cpu_freq,
212 	.get_cpu_count = bcm6328_get_cpu_count,
213 };
214 
215 static const struct bmips_cpu_hw bmips_cpu_bcm6338 = {
216 	.get_cpu_desc = bmips_short_cpu_desc,
217 	.get_cpu_freq = bcm6338_get_cpu_freq,
218 	.get_cpu_count = bcm6345_get_cpu_count,
219 };
220 
221 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
222 	.get_cpu_desc = bmips_short_cpu_desc,
223 	.get_cpu_freq = bcm6348_get_cpu_freq,
224 	.get_cpu_count = bcm6345_get_cpu_count,
225 };
226 
227 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
228 	.get_cpu_desc = bmips_short_cpu_desc,
229 	.get_cpu_freq = bcm6358_get_cpu_freq,
230 	.get_cpu_count = bcm6358_get_cpu_count,
231 };
232 
233 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
234 	.get_cpu_desc = bmips_long_cpu_desc,
235 	.get_cpu_freq = bcm63268_get_cpu_freq,
236 	.get_cpu_count = bcm6358_get_cpu_count,
237 };
238 
239 /* Generic CPU Ops */
240 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
241 {
242 	struct bmips_cpu_priv *priv = dev_get_priv(dev);
243 	const struct bmips_cpu_hw *hw = priv->hw;
244 
245 	return hw->get_cpu_desc(priv, buf, size);
246 }
247 
248 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info)
249 {
250 	struct bmips_cpu_priv *priv = dev_get_priv(dev);
251 	const struct bmips_cpu_hw *hw = priv->hw;
252 
253 	info->cpu_freq = hw->get_cpu_freq(priv);
254 	info->features = BIT(CPU_FEAT_L1_CACHE);
255 	info->features |= BIT(CPU_FEAT_MMU);
256 	info->features |= BIT(CPU_FEAT_DEVICE_ID);
257 
258 	return 0;
259 }
260 
261 static int bmips_cpu_get_count(struct udevice *dev)
262 {
263 	struct bmips_cpu_priv *priv = dev_get_priv(dev);
264 	const struct bmips_cpu_hw *hw = priv->hw;
265 
266 	return hw->get_cpu_count(priv);
267 }
268 
269 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size)
270 {
271 	snprintf(buf, size, "Broadcom");
272 
273 	return 0;
274 }
275 
276 static const struct cpu_ops bmips_cpu_ops = {
277 	.get_desc = bmips_cpu_get_desc,
278 	.get_info = bmips_cpu_get_info,
279 	.get_count = bmips_cpu_get_count,
280 	.get_vendor = bmips_cpu_get_vendor,
281 };
282 
283 /* BMIPS CPU driver */
284 int bmips_cpu_bind(struct udevice *dev)
285 {
286 	struct cpu_platdata *plat = dev_get_parent_platdata(dev);
287 
288 	plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
289 		"reg", -1);
290 	plat->device_id = read_c0_prid();
291 
292 	return 0;
293 }
294 
295 int bmips_cpu_probe(struct udevice *dev)
296 {
297 	struct bmips_cpu_priv *priv = dev_get_priv(dev);
298 	const struct bmips_cpu_hw *hw =
299 		(const struct bmips_cpu_hw *)dev_get_driver_data(dev);
300 	fdt_addr_t addr;
301 	fdt_size_t size;
302 
303 	addr = devfdt_get_addr_size_index(dev_get_parent(dev), 0, &size);
304 	if (addr == FDT_ADDR_T_NONE)
305 		return -EINVAL;
306 
307 	priv->regs = ioremap(addr, size);
308 	priv->hw = hw;
309 
310 	return 0;
311 }
312 
313 static const struct udevice_id bmips_cpu_ids[] = {
314 	{
315 		.compatible = "brcm,bcm3380-cpu",
316 		.data = (ulong)&bmips_cpu_bcm3380,
317 	}, {
318 		.compatible = "brcm,bcm6328-cpu",
319 		.data = (ulong)&bmips_cpu_bcm6328,
320 	}, {
321 		.compatible = "brcm,bcm6338-cpu",
322 		.data = (ulong)&bmips_cpu_bcm6338,
323 	}, {
324 		.compatible = "brcm,bcm6348-cpu",
325 		.data = (ulong)&bmips_cpu_bcm6348,
326 	}, {
327 		.compatible = "brcm,bcm6358-cpu",
328 		.data = (ulong)&bmips_cpu_bcm6358,
329 	}, {
330 		.compatible = "brcm,bcm63268-cpu",
331 		.data = (ulong)&bmips_cpu_bcm63268,
332 	},
333 	{ /* sentinel */ }
334 };
335 
336 U_BOOT_DRIVER(bmips_cpu_drv) = {
337 	.name = "bmips_cpu",
338 	.id = UCLASS_CPU,
339 	.of_match = bmips_cpu_ids,
340 	.bind = bmips_cpu_bind,
341 	.probe = bmips_cpu_probe,
342 	.priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
343 	.ops = &bmips_cpu_ops,
344 	.flags = DM_FLAG_PRE_RELOC,
345 };
346 
347 #ifdef CONFIG_DISPLAY_CPUINFO
348 int print_cpuinfo(void)
349 {
350 	struct cpu_info cpu;
351 	struct udevice *dev;
352 	int err;
353 	char desc[100];
354 
355 	err = uclass_get_device(UCLASS_CPU, 0, &dev);
356 	if (err)
357 		return 0;
358 
359 	err = cpu_get_info(dev, &cpu);
360 	if (err)
361 		return 0;
362 
363 	err = cpu_get_desc(dev, desc, sizeof(desc));
364 	if (err)
365 		return 0;
366 
367 	printf("Chip ID: %s, MIPS: ", desc);
368 	print_freq(cpu.cpu_freq, "\n");
369 
370 	return 0;
371 }
372 #endif
373