1 /* 2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 3 * 4 * Derived from linux/arch/mips/bcm63xx/cpu.c: 5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 6 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <cpu.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <asm/io.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define REV_CHIPID_SHIFT 16 20 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) 21 #define REV_LONG_CHIPID_SHIFT 12 22 #define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) 23 #define REV_REVID_SHIFT 0 24 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) 25 26 #define REG_BCM6328_OTP 0x62c 27 #define BCM6328_TP1_DISABLED BIT(9) 28 29 #define REG_BCM6328_MISC_STRAPBUS 0x1a40 30 #define STRAPBUS_6328_FCVO_SHIFT 7 31 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) 32 33 #define REG_BCM6348_PERF_MIPSPLLCFG 0x34 34 #define MIPSPLLCFG_6348_M1CPU_SHIFT 6 35 #define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT) 36 #define MIPSPLLCFG_6348_N2_SHIFT 15 37 #define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT) 38 #define MIPSPLLCFG_6348_N1_SHIFT 20 39 #define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT) 40 41 #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8 42 #define DMIPSPLLCFG_6358_M1_SHIFT 0 43 #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT) 44 #define DMIPSPLLCFG_6358_N1_SHIFT 23 45 #define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT) 46 #define DMIPSPLLCFG_6358_N2_SHIFT 29 47 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT) 48 49 #define REG_BCM63268_MISC_STRAPBUS 0x1814 50 #define STRAPBUS_63268_FCVO_SHIFT 21 51 #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) 52 53 struct bmips_cpu_priv; 54 55 struct bmips_cpu_hw { 56 int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size); 57 ulong (*get_cpu_freq)(struct bmips_cpu_priv *); 58 int (*get_cpu_count)(struct bmips_cpu_priv *); 59 }; 60 61 struct bmips_cpu_priv { 62 void __iomem *regs; 63 const struct bmips_cpu_hw *hw; 64 }; 65 66 /* Specific CPU Ops */ 67 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf, 68 int size) 69 { 70 unsigned short cpu_id; 71 unsigned char cpu_rev; 72 u32 val; 73 74 val = readl_be(priv->regs); 75 cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; 76 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; 77 78 snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev); 79 80 return 0; 81 } 82 83 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf, 84 int size) 85 { 86 unsigned int cpu_id; 87 unsigned char cpu_rev; 88 u32 val; 89 90 val = readl_be(priv->regs); 91 cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT; 92 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; 93 94 snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev); 95 96 return 0; 97 } 98 99 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv) 100 { 101 unsigned int mips_pll_fcvo; 102 103 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS); 104 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK) 105 >> STRAPBUS_6328_FCVO_SHIFT; 106 107 switch (mips_pll_fcvo) { 108 case 0x12: 109 case 0x14: 110 case 0x19: 111 return 160000000; 112 case 0x1c: 113 return 192000000; 114 case 0x13: 115 case 0x15: 116 return 200000000; 117 case 0x1a: 118 return 384000000; 119 case 0x16: 120 return 400000000; 121 default: 122 return 320000000; 123 } 124 } 125 126 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv) 127 { 128 unsigned int tmp, n1, n2, m1; 129 130 tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG); 131 n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT; 132 n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT; 133 m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT; 134 135 return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1); 136 } 137 138 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv) 139 { 140 unsigned int tmp, n1, n2, m1; 141 142 tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG); 143 n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT; 144 n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT; 145 m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT; 146 147 return (16 * 1000000 * n1 * n2) / m1; 148 } 149 150 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv) 151 { 152 unsigned int mips_pll_fcvo; 153 154 mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS); 155 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK) 156 >> STRAPBUS_63268_FCVO_SHIFT; 157 158 switch (mips_pll_fcvo) { 159 case 0x3: 160 case 0xe: 161 return 320000000; 162 case 0xa: 163 return 333000000; 164 case 0x2: 165 case 0xb: 166 case 0xf: 167 return 400000000; 168 default: 169 return 0; 170 } 171 } 172 173 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv) 174 { 175 u32 val = readl_be(priv->regs + REG_BCM6328_OTP); 176 177 if (val & BCM6328_TP1_DISABLED) 178 return 1; 179 else 180 return 2; 181 } 182 183 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv) 184 { 185 return 1; 186 } 187 188 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv) 189 { 190 return 2; 191 } 192 193 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = { 194 .get_cpu_desc = bmips_long_cpu_desc, 195 .get_cpu_freq = bcm6328_get_cpu_freq, 196 .get_cpu_count = bcm6328_get_cpu_count, 197 }; 198 199 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = { 200 .get_cpu_desc = bmips_short_cpu_desc, 201 .get_cpu_freq = bcm6348_get_cpu_freq, 202 .get_cpu_count = bcm6345_get_cpu_count, 203 }; 204 205 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = { 206 .get_cpu_desc = bmips_short_cpu_desc, 207 .get_cpu_freq = bcm6358_get_cpu_freq, 208 .get_cpu_count = bcm6358_get_cpu_count, 209 }; 210 211 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = { 212 .get_cpu_desc = bmips_long_cpu_desc, 213 .get_cpu_freq = bcm63268_get_cpu_freq, 214 .get_cpu_count = bcm6358_get_cpu_count, 215 }; 216 217 /* Generic CPU Ops */ 218 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size) 219 { 220 struct bmips_cpu_priv *priv = dev_get_priv(dev); 221 const struct bmips_cpu_hw *hw = priv->hw; 222 223 return hw->get_cpu_desc(priv, buf, size); 224 } 225 226 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info) 227 { 228 struct bmips_cpu_priv *priv = dev_get_priv(dev); 229 const struct bmips_cpu_hw *hw = priv->hw; 230 231 info->cpu_freq = hw->get_cpu_freq(priv); 232 info->features = BIT(CPU_FEAT_L1_CACHE); 233 info->features |= BIT(CPU_FEAT_MMU); 234 info->features |= BIT(CPU_FEAT_DEVICE_ID); 235 236 return 0; 237 } 238 239 static int bmips_cpu_get_count(struct udevice *dev) 240 { 241 struct bmips_cpu_priv *priv = dev_get_priv(dev); 242 const struct bmips_cpu_hw *hw = priv->hw; 243 244 return hw->get_cpu_count(priv); 245 } 246 247 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size) 248 { 249 snprintf(buf, size, "Broadcom"); 250 251 return 0; 252 } 253 254 static const struct cpu_ops bmips_cpu_ops = { 255 .get_desc = bmips_cpu_get_desc, 256 .get_info = bmips_cpu_get_info, 257 .get_count = bmips_cpu_get_count, 258 .get_vendor = bmips_cpu_get_vendor, 259 }; 260 261 /* BMIPS CPU driver */ 262 int bmips_cpu_bind(struct udevice *dev) 263 { 264 struct cpu_platdata *plat = dev_get_parent_platdata(dev); 265 266 plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 267 "reg", -1); 268 plat->device_id = read_c0_prid(); 269 270 return 0; 271 } 272 273 int bmips_cpu_probe(struct udevice *dev) 274 { 275 struct bmips_cpu_priv *priv = dev_get_priv(dev); 276 const struct bmips_cpu_hw *hw = 277 (const struct bmips_cpu_hw *)dev_get_driver_data(dev); 278 fdt_addr_t addr; 279 fdt_size_t size; 280 281 addr = dev_get_addr_size_index(dev_get_parent(dev), 0, &size); 282 if (addr == FDT_ADDR_T_NONE) 283 return -EINVAL; 284 285 priv->regs = ioremap(addr, size); 286 priv->hw = hw; 287 288 return 0; 289 } 290 291 static const struct udevice_id bmips_cpu_ids[] = { 292 { 293 .compatible = "brcm,bcm6328-cpu", 294 .data = (ulong)&bmips_cpu_bcm6328, 295 }, { 296 .compatible = "brcm,bcm6348-cpu", 297 .data = (ulong)&bmips_cpu_bcm6348, 298 }, { 299 .compatible = "brcm,bcm6358-cpu", 300 .data = (ulong)&bmips_cpu_bcm6358, 301 }, { 302 .compatible = "brcm,bcm63268-cpu", 303 .data = (ulong)&bmips_cpu_bcm63268, 304 }, 305 { /* sentinel */ } 306 }; 307 308 U_BOOT_DRIVER(bmips_cpu_drv) = { 309 .name = "bmips_cpu", 310 .id = UCLASS_CPU, 311 .of_match = bmips_cpu_ids, 312 .bind = bmips_cpu_bind, 313 .probe = bmips_cpu_probe, 314 .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv), 315 .ops = &bmips_cpu_ops, 316 .flags = DM_FLAG_PRE_RELOC, 317 }; 318 319 #ifdef CONFIG_DISPLAY_CPUINFO 320 int print_cpuinfo(void) 321 { 322 struct cpu_info cpu; 323 struct udevice *dev; 324 int err; 325 char desc[100]; 326 327 err = uclass_get_device(UCLASS_CPU, 0, &dev); 328 if (err) 329 return 0; 330 331 err = cpu_get_info(dev, &cpu); 332 if (err) 333 return 0; 334 335 err = cpu_get_desc(dev, desc, sizeof(desc)); 336 if (err) 337 return 0; 338 339 printf("Chip ID: %s, MIPS: ", desc); 340 print_freq(cpu.cpu_freq, "\n"); 341 342 return 0; 343 } 344 #endif 345