1 /* 2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 3 * 4 * Derived from linux/arch/mips/bcm63xx/cpu.c: 5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 6 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <cpu.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <asm/io.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define REV_CHIPID_SHIFT 16 20 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) 21 #define REV_LONG_CHIPID_SHIFT 12 22 #define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) 23 #define REV_REVID_SHIFT 0 24 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) 25 26 #define REG_BCM6328_OTP 0x62c 27 #define BCM6328_TP1_DISABLED BIT(9) 28 29 #define REG_BCM6318_STRAP_OVRDBUS 0x900 30 #define OVRDBUS_6318_FREQ_SHIFT 23 31 #define OVRDBUS_6318_FREQ_MASK (0x3 << OVRDBUS_6318_FREQ_SHIFT) 32 33 #define REG_BCM6328_MISC_STRAPBUS 0x1a40 34 #define STRAPBUS_6328_FCVO_SHIFT 7 35 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) 36 37 #define REG_BCM6348_PERF_MIPSPLLCFG 0x34 38 #define MIPSPLLCFG_6348_M1CPU_SHIFT 6 39 #define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT) 40 #define MIPSPLLCFG_6348_N2_SHIFT 15 41 #define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT) 42 #define MIPSPLLCFG_6348_N1_SHIFT 20 43 #define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT) 44 45 #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8 46 #define DMIPSPLLCFG_6358_M1_SHIFT 0 47 #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT) 48 #define DMIPSPLLCFG_6358_N1_SHIFT 23 49 #define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT) 50 #define DMIPSPLLCFG_6358_N2_SHIFT 29 51 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT) 52 53 #define REG_BCM6362_MISC_STRAPBUS 0x1814 54 #define STRAPBUS_6362_FCVO_SHIFT 1 55 #define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT) 56 57 #define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0 58 #define DMIPSPLLCFG_6368_P1_SHIFT 0 59 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) 60 #define DMIPSPLLCFG_6368_P2_SHIFT 4 61 #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT) 62 #define DMIPSPLLCFG_6368_NDIV_SHIFT 16 63 #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT) 64 #define REG_BCM6368_DDR_DMIPSPLLDIV 0x12a4 65 #define DMIPSPLLDIV_6368_MDIV_SHIFT 0 66 #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT) 67 68 #define REG_BCM63268_MISC_STRAPBUS 0x1814 69 #define STRAPBUS_63268_FCVO_SHIFT 21 70 #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) 71 72 struct bmips_cpu_priv; 73 74 struct bmips_cpu_hw { 75 int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size); 76 ulong (*get_cpu_freq)(struct bmips_cpu_priv *); 77 int (*get_cpu_count)(struct bmips_cpu_priv *); 78 }; 79 80 struct bmips_cpu_priv { 81 void __iomem *regs; 82 const struct bmips_cpu_hw *hw; 83 }; 84 85 /* Specific CPU Ops */ 86 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf, 87 int size) 88 { 89 unsigned short cpu_id; 90 unsigned char cpu_rev; 91 u32 val; 92 93 val = readl_be(priv->regs); 94 cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; 95 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; 96 97 snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev); 98 99 return 0; 100 } 101 102 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf, 103 int size) 104 { 105 unsigned int cpu_id; 106 unsigned char cpu_rev; 107 u32 val; 108 109 val = readl_be(priv->regs); 110 cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT; 111 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; 112 113 snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev); 114 115 return 0; 116 } 117 118 static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv) 119 { 120 return 333000000; 121 } 122 123 static ulong bcm6318_get_cpu_freq(struct bmips_cpu_priv *priv) 124 { 125 unsigned int mips_pll_fcvo; 126 127 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6318_STRAP_OVRDBUS); 128 mips_pll_fcvo = (mips_pll_fcvo & OVRDBUS_6318_FREQ_MASK) 129 >> OVRDBUS_6318_FREQ_SHIFT; 130 131 switch (mips_pll_fcvo) { 132 case 0: 133 return 166000000; 134 case 1: 135 return 400000000; 136 case 2: 137 return 250000000; 138 case 3: 139 return 333000000; 140 default: 141 return 0; 142 } 143 } 144 145 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv) 146 { 147 unsigned int mips_pll_fcvo; 148 149 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS); 150 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK) 151 >> STRAPBUS_6328_FCVO_SHIFT; 152 153 switch (mips_pll_fcvo) { 154 case 0x12: 155 case 0x14: 156 case 0x19: 157 return 160000000; 158 case 0x1c: 159 return 192000000; 160 case 0x13: 161 case 0x15: 162 return 200000000; 163 case 0x1a: 164 return 384000000; 165 case 0x16: 166 return 400000000; 167 default: 168 return 320000000; 169 } 170 } 171 172 static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv) 173 { 174 return 240000000; 175 } 176 177 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv) 178 { 179 unsigned int tmp, n1, n2, m1; 180 181 tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG); 182 n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT; 183 n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT; 184 m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT; 185 186 return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1); 187 } 188 189 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv) 190 { 191 unsigned int tmp, n1, n2, m1; 192 193 tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG); 194 n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT; 195 n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT; 196 m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT; 197 198 return (16 * 1000000 * n1 * n2) / m1; 199 } 200 201 static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv) 202 { 203 unsigned int mips_pll_fcvo; 204 205 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS); 206 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK) 207 >> STRAPBUS_6362_FCVO_SHIFT; 208 209 switch (mips_pll_fcvo) { 210 case 0x03: 211 case 0x0b: 212 case 0x13: 213 case 0x1b: 214 return 240000000; 215 case 0x04: 216 case 0x0c: 217 case 0x14: 218 case 0x1c: 219 return 160000000; 220 case 0x05: 221 case 0x0e: 222 case 0x16: 223 case 0x1e: 224 case 0x1f: 225 return 400000000; 226 case 0x06: 227 return 440000000; 228 case 0x07: 229 case 0x17: 230 return 384000000; 231 case 0x15: 232 case 0x1d: 233 return 200000000; 234 default: 235 return 320000000; 236 } 237 } 238 239 static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv) 240 { 241 unsigned int tmp, p1, p2, ndiv, m1; 242 243 tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG); 244 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT; 245 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT; 246 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >> 247 DMIPSPLLCFG_6368_NDIV_SHIFT; 248 249 tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV); 250 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT; 251 252 return (((64 * 1000000) / p1) * p2 * ndiv) / m1; 253 } 254 255 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv) 256 { 257 unsigned int mips_pll_fcvo; 258 259 mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS); 260 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK) 261 >> STRAPBUS_63268_FCVO_SHIFT; 262 263 switch (mips_pll_fcvo) { 264 case 0x3: 265 case 0xe: 266 return 320000000; 267 case 0xa: 268 return 333000000; 269 case 0x2: 270 case 0xb: 271 case 0xf: 272 return 400000000; 273 default: 274 return 0; 275 } 276 } 277 278 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv) 279 { 280 u32 val = readl_be(priv->regs + REG_BCM6328_OTP); 281 282 if (val & BCM6328_TP1_DISABLED) 283 return 1; 284 else 285 return 2; 286 } 287 288 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv) 289 { 290 return 1; 291 } 292 293 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv) 294 { 295 return 2; 296 } 297 298 static const struct bmips_cpu_hw bmips_cpu_bcm3380 = { 299 .get_cpu_desc = bmips_short_cpu_desc, 300 .get_cpu_freq = bcm3380_get_cpu_freq, 301 .get_cpu_count = bcm6358_get_cpu_count, 302 }; 303 304 static const struct bmips_cpu_hw bmips_cpu_bcm6318 = { 305 .get_cpu_desc = bmips_short_cpu_desc, 306 .get_cpu_freq = bcm6318_get_cpu_freq, 307 .get_cpu_count = bcm6345_get_cpu_count, 308 }; 309 310 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = { 311 .get_cpu_desc = bmips_long_cpu_desc, 312 .get_cpu_freq = bcm6328_get_cpu_freq, 313 .get_cpu_count = bcm6328_get_cpu_count, 314 }; 315 316 static const struct bmips_cpu_hw bmips_cpu_bcm6338 = { 317 .get_cpu_desc = bmips_short_cpu_desc, 318 .get_cpu_freq = bcm6338_get_cpu_freq, 319 .get_cpu_count = bcm6345_get_cpu_count, 320 }; 321 322 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = { 323 .get_cpu_desc = bmips_short_cpu_desc, 324 .get_cpu_freq = bcm6348_get_cpu_freq, 325 .get_cpu_count = bcm6345_get_cpu_count, 326 }; 327 328 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = { 329 .get_cpu_desc = bmips_short_cpu_desc, 330 .get_cpu_freq = bcm6358_get_cpu_freq, 331 .get_cpu_count = bcm6358_get_cpu_count, 332 }; 333 334 static const struct bmips_cpu_hw bmips_cpu_bcm6362 = { 335 .get_cpu_desc = bmips_short_cpu_desc, 336 .get_cpu_freq = bcm6362_get_cpu_freq, 337 .get_cpu_count = bcm6358_get_cpu_count, 338 }; 339 340 static const struct bmips_cpu_hw bmips_cpu_bcm6368 = { 341 .get_cpu_desc = bmips_short_cpu_desc, 342 .get_cpu_freq = bcm6368_get_cpu_freq, 343 .get_cpu_count = bcm6358_get_cpu_count, 344 }; 345 346 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = { 347 .get_cpu_desc = bmips_long_cpu_desc, 348 .get_cpu_freq = bcm63268_get_cpu_freq, 349 .get_cpu_count = bcm6358_get_cpu_count, 350 }; 351 352 /* Generic CPU Ops */ 353 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size) 354 { 355 struct bmips_cpu_priv *priv = dev_get_priv(dev); 356 const struct bmips_cpu_hw *hw = priv->hw; 357 358 return hw->get_cpu_desc(priv, buf, size); 359 } 360 361 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info) 362 { 363 struct bmips_cpu_priv *priv = dev_get_priv(dev); 364 const struct bmips_cpu_hw *hw = priv->hw; 365 366 info->cpu_freq = hw->get_cpu_freq(priv); 367 info->features = BIT(CPU_FEAT_L1_CACHE); 368 info->features |= BIT(CPU_FEAT_MMU); 369 info->features |= BIT(CPU_FEAT_DEVICE_ID); 370 371 return 0; 372 } 373 374 static int bmips_cpu_get_count(struct udevice *dev) 375 { 376 struct bmips_cpu_priv *priv = dev_get_priv(dev); 377 const struct bmips_cpu_hw *hw = priv->hw; 378 379 return hw->get_cpu_count(priv); 380 } 381 382 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size) 383 { 384 snprintf(buf, size, "Broadcom"); 385 386 return 0; 387 } 388 389 static const struct cpu_ops bmips_cpu_ops = { 390 .get_desc = bmips_cpu_get_desc, 391 .get_info = bmips_cpu_get_info, 392 .get_count = bmips_cpu_get_count, 393 .get_vendor = bmips_cpu_get_vendor, 394 }; 395 396 /* BMIPS CPU driver */ 397 int bmips_cpu_bind(struct udevice *dev) 398 { 399 struct cpu_platdata *plat = dev_get_parent_platdata(dev); 400 401 plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 402 "reg", -1); 403 plat->device_id = read_c0_prid(); 404 405 return 0; 406 } 407 408 int bmips_cpu_probe(struct udevice *dev) 409 { 410 struct bmips_cpu_priv *priv = dev_get_priv(dev); 411 const struct bmips_cpu_hw *hw = 412 (const struct bmips_cpu_hw *)dev_get_driver_data(dev); 413 fdt_addr_t addr; 414 fdt_size_t size; 415 416 addr = devfdt_get_addr_size_index(dev_get_parent(dev), 0, &size); 417 if (addr == FDT_ADDR_T_NONE) 418 return -EINVAL; 419 420 priv->regs = ioremap(addr, size); 421 priv->hw = hw; 422 423 return 0; 424 } 425 426 static const struct udevice_id bmips_cpu_ids[] = { 427 { 428 .compatible = "brcm,bcm3380-cpu", 429 .data = (ulong)&bmips_cpu_bcm3380, 430 }, { 431 .compatible = "brcm,bcm6318-cpu", 432 .data = (ulong)&bmips_cpu_bcm6318, 433 }, { 434 .compatible = "brcm,bcm6328-cpu", 435 .data = (ulong)&bmips_cpu_bcm6328, 436 }, { 437 .compatible = "brcm,bcm6338-cpu", 438 .data = (ulong)&bmips_cpu_bcm6338, 439 }, { 440 .compatible = "brcm,bcm6348-cpu", 441 .data = (ulong)&bmips_cpu_bcm6348, 442 }, { 443 .compatible = "brcm,bcm6358-cpu", 444 .data = (ulong)&bmips_cpu_bcm6358, 445 }, { 446 .compatible = "brcm,bcm6362-cpu", 447 .data = (ulong)&bmips_cpu_bcm6362, 448 }, { 449 .compatible = "brcm,bcm6368-cpu", 450 .data = (ulong)&bmips_cpu_bcm6368, 451 }, { 452 .compatible = "brcm,bcm63268-cpu", 453 .data = (ulong)&bmips_cpu_bcm63268, 454 }, 455 { /* sentinel */ } 456 }; 457 458 U_BOOT_DRIVER(bmips_cpu_drv) = { 459 .name = "bmips_cpu", 460 .id = UCLASS_CPU, 461 .of_match = bmips_cpu_ids, 462 .bind = bmips_cpu_bind, 463 .probe = bmips_cpu_probe, 464 .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv), 465 .ops = &bmips_cpu_ops, 466 .flags = DM_FLAG_PRE_RELOC, 467 }; 468 469 #ifdef CONFIG_DISPLAY_CPUINFO 470 int print_cpuinfo(void) 471 { 472 struct cpu_info cpu; 473 struct udevice *dev; 474 int err; 475 char desc[100]; 476 477 err = uclass_get_device(UCLASS_CPU, 0, &dev); 478 if (err) 479 return 0; 480 481 err = cpu_get_info(dev, &cpu); 482 if (err) 483 return 0; 484 485 err = cpu_get_desc(dev, desc, sizeof(desc)); 486 if (err) 487 return 0; 488 489 printf("Chip ID: %s, MIPS: ", desc); 490 print_freq(cpu.cpu_freq, "\n"); 491 492 return 0; 493 } 494 #endif 495