1 /* 2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 3 * 4 * Derived from linux/arch/mips/bcm63xx/cpu.c: 5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 6 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <cpu.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <asm/io.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define REV_CHIPID_SHIFT 16 20 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) 21 #define REV_LONG_CHIPID_SHIFT 12 22 #define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) 23 #define REV_REVID_SHIFT 0 24 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) 25 26 #define REG_BCM6328_OTP 0x62c 27 #define BCM6328_TP1_DISABLED BIT(9) 28 29 #define REG_BCM6328_MISC_STRAPBUS 0x1a40 30 #define STRAPBUS_6328_FCVO_SHIFT 7 31 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) 32 33 #define REG_BCM6348_PERF_MIPSPLLCFG 0x34 34 #define MIPSPLLCFG_6348_M1CPU_SHIFT 6 35 #define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT) 36 #define MIPSPLLCFG_6348_N2_SHIFT 15 37 #define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT) 38 #define MIPSPLLCFG_6348_N1_SHIFT 20 39 #define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT) 40 41 #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8 42 #define DMIPSPLLCFG_6358_M1_SHIFT 0 43 #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT) 44 #define DMIPSPLLCFG_6358_N1_SHIFT 23 45 #define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT) 46 #define DMIPSPLLCFG_6358_N2_SHIFT 29 47 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT) 48 49 #define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0 50 #define DMIPSPLLCFG_6368_P1_SHIFT 0 51 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) 52 #define DMIPSPLLCFG_6368_P2_SHIFT 4 53 #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT) 54 #define DMIPSPLLCFG_6368_NDIV_SHIFT 16 55 #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT) 56 #define REG_BCM6368_DDR_DMIPSPLLDIV 0x12a4 57 #define DMIPSPLLDIV_6368_MDIV_SHIFT 0 58 #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT) 59 60 #define REG_BCM63268_MISC_STRAPBUS 0x1814 61 #define STRAPBUS_63268_FCVO_SHIFT 21 62 #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) 63 64 struct bmips_cpu_priv; 65 66 struct bmips_cpu_hw { 67 int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size); 68 ulong (*get_cpu_freq)(struct bmips_cpu_priv *); 69 int (*get_cpu_count)(struct bmips_cpu_priv *); 70 }; 71 72 struct bmips_cpu_priv { 73 void __iomem *regs; 74 const struct bmips_cpu_hw *hw; 75 }; 76 77 /* Specific CPU Ops */ 78 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf, 79 int size) 80 { 81 unsigned short cpu_id; 82 unsigned char cpu_rev; 83 u32 val; 84 85 val = readl_be(priv->regs); 86 cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; 87 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; 88 89 snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev); 90 91 return 0; 92 } 93 94 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf, 95 int size) 96 { 97 unsigned int cpu_id; 98 unsigned char cpu_rev; 99 u32 val; 100 101 val = readl_be(priv->regs); 102 cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT; 103 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; 104 105 snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev); 106 107 return 0; 108 } 109 110 static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv) 111 { 112 return 333000000; 113 } 114 115 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv) 116 { 117 unsigned int mips_pll_fcvo; 118 119 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS); 120 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK) 121 >> STRAPBUS_6328_FCVO_SHIFT; 122 123 switch (mips_pll_fcvo) { 124 case 0x12: 125 case 0x14: 126 case 0x19: 127 return 160000000; 128 case 0x1c: 129 return 192000000; 130 case 0x13: 131 case 0x15: 132 return 200000000; 133 case 0x1a: 134 return 384000000; 135 case 0x16: 136 return 400000000; 137 default: 138 return 320000000; 139 } 140 } 141 142 static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv) 143 { 144 return 240000000; 145 } 146 147 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv) 148 { 149 unsigned int tmp, n1, n2, m1; 150 151 tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG); 152 n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT; 153 n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT; 154 m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT; 155 156 return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1); 157 } 158 159 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv) 160 { 161 unsigned int tmp, n1, n2, m1; 162 163 tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG); 164 n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT; 165 n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT; 166 m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT; 167 168 return (16 * 1000000 * n1 * n2) / m1; 169 } 170 171 static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv) 172 { 173 unsigned int tmp, p1, p2, ndiv, m1; 174 175 tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG); 176 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT; 177 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT; 178 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >> 179 DMIPSPLLCFG_6368_NDIV_SHIFT; 180 181 tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV); 182 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT; 183 184 return (((64 * 1000000) / p1) * p2 * ndiv) / m1; 185 } 186 187 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv) 188 { 189 unsigned int mips_pll_fcvo; 190 191 mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS); 192 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK) 193 >> STRAPBUS_63268_FCVO_SHIFT; 194 195 switch (mips_pll_fcvo) { 196 case 0x3: 197 case 0xe: 198 return 320000000; 199 case 0xa: 200 return 333000000; 201 case 0x2: 202 case 0xb: 203 case 0xf: 204 return 400000000; 205 default: 206 return 0; 207 } 208 } 209 210 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv) 211 { 212 u32 val = readl_be(priv->regs + REG_BCM6328_OTP); 213 214 if (val & BCM6328_TP1_DISABLED) 215 return 1; 216 else 217 return 2; 218 } 219 220 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv) 221 { 222 return 1; 223 } 224 225 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv) 226 { 227 return 2; 228 } 229 230 static const struct bmips_cpu_hw bmips_cpu_bcm3380 = { 231 .get_cpu_desc = bmips_short_cpu_desc, 232 .get_cpu_freq = bcm3380_get_cpu_freq, 233 .get_cpu_count = bcm6358_get_cpu_count, 234 }; 235 236 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = { 237 .get_cpu_desc = bmips_long_cpu_desc, 238 .get_cpu_freq = bcm6328_get_cpu_freq, 239 .get_cpu_count = bcm6328_get_cpu_count, 240 }; 241 242 static const struct bmips_cpu_hw bmips_cpu_bcm6338 = { 243 .get_cpu_desc = bmips_short_cpu_desc, 244 .get_cpu_freq = bcm6338_get_cpu_freq, 245 .get_cpu_count = bcm6345_get_cpu_count, 246 }; 247 248 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = { 249 .get_cpu_desc = bmips_short_cpu_desc, 250 .get_cpu_freq = bcm6348_get_cpu_freq, 251 .get_cpu_count = bcm6345_get_cpu_count, 252 }; 253 254 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = { 255 .get_cpu_desc = bmips_short_cpu_desc, 256 .get_cpu_freq = bcm6358_get_cpu_freq, 257 .get_cpu_count = bcm6358_get_cpu_count, 258 }; 259 260 static const struct bmips_cpu_hw bmips_cpu_bcm6368 = { 261 .get_cpu_desc = bmips_short_cpu_desc, 262 .get_cpu_freq = bcm6368_get_cpu_freq, 263 .get_cpu_count = bcm6358_get_cpu_count, 264 }; 265 266 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = { 267 .get_cpu_desc = bmips_long_cpu_desc, 268 .get_cpu_freq = bcm63268_get_cpu_freq, 269 .get_cpu_count = bcm6358_get_cpu_count, 270 }; 271 272 /* Generic CPU Ops */ 273 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size) 274 { 275 struct bmips_cpu_priv *priv = dev_get_priv(dev); 276 const struct bmips_cpu_hw *hw = priv->hw; 277 278 return hw->get_cpu_desc(priv, buf, size); 279 } 280 281 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info) 282 { 283 struct bmips_cpu_priv *priv = dev_get_priv(dev); 284 const struct bmips_cpu_hw *hw = priv->hw; 285 286 info->cpu_freq = hw->get_cpu_freq(priv); 287 info->features = BIT(CPU_FEAT_L1_CACHE); 288 info->features |= BIT(CPU_FEAT_MMU); 289 info->features |= BIT(CPU_FEAT_DEVICE_ID); 290 291 return 0; 292 } 293 294 static int bmips_cpu_get_count(struct udevice *dev) 295 { 296 struct bmips_cpu_priv *priv = dev_get_priv(dev); 297 const struct bmips_cpu_hw *hw = priv->hw; 298 299 return hw->get_cpu_count(priv); 300 } 301 302 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size) 303 { 304 snprintf(buf, size, "Broadcom"); 305 306 return 0; 307 } 308 309 static const struct cpu_ops bmips_cpu_ops = { 310 .get_desc = bmips_cpu_get_desc, 311 .get_info = bmips_cpu_get_info, 312 .get_count = bmips_cpu_get_count, 313 .get_vendor = bmips_cpu_get_vendor, 314 }; 315 316 /* BMIPS CPU driver */ 317 int bmips_cpu_bind(struct udevice *dev) 318 { 319 struct cpu_platdata *plat = dev_get_parent_platdata(dev); 320 321 plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 322 "reg", -1); 323 plat->device_id = read_c0_prid(); 324 325 return 0; 326 } 327 328 int bmips_cpu_probe(struct udevice *dev) 329 { 330 struct bmips_cpu_priv *priv = dev_get_priv(dev); 331 const struct bmips_cpu_hw *hw = 332 (const struct bmips_cpu_hw *)dev_get_driver_data(dev); 333 fdt_addr_t addr; 334 fdt_size_t size; 335 336 addr = devfdt_get_addr_size_index(dev_get_parent(dev), 0, &size); 337 if (addr == FDT_ADDR_T_NONE) 338 return -EINVAL; 339 340 priv->regs = ioremap(addr, size); 341 priv->hw = hw; 342 343 return 0; 344 } 345 346 static const struct udevice_id bmips_cpu_ids[] = { 347 { 348 .compatible = "brcm,bcm3380-cpu", 349 .data = (ulong)&bmips_cpu_bcm3380, 350 }, { 351 .compatible = "brcm,bcm6328-cpu", 352 .data = (ulong)&bmips_cpu_bcm6328, 353 }, { 354 .compatible = "brcm,bcm6338-cpu", 355 .data = (ulong)&bmips_cpu_bcm6338, 356 }, { 357 .compatible = "brcm,bcm6348-cpu", 358 .data = (ulong)&bmips_cpu_bcm6348, 359 }, { 360 .compatible = "brcm,bcm6358-cpu", 361 .data = (ulong)&bmips_cpu_bcm6358, 362 }, { 363 .compatible = "brcm,bcm6368-cpu", 364 .data = (ulong)&bmips_cpu_bcm6368, 365 }, { 366 .compatible = "brcm,bcm63268-cpu", 367 .data = (ulong)&bmips_cpu_bcm63268, 368 }, 369 { /* sentinel */ } 370 }; 371 372 U_BOOT_DRIVER(bmips_cpu_drv) = { 373 .name = "bmips_cpu", 374 .id = UCLASS_CPU, 375 .of_match = bmips_cpu_ids, 376 .bind = bmips_cpu_bind, 377 .probe = bmips_cpu_probe, 378 .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv), 379 .ops = &bmips_cpu_ops, 380 .flags = DM_FLAG_PRE_RELOC, 381 }; 382 383 #ifdef CONFIG_DISPLAY_CPUINFO 384 int print_cpuinfo(void) 385 { 386 struct cpu_info cpu; 387 struct udevice *dev; 388 int err; 389 char desc[100]; 390 391 err = uclass_get_device(UCLASS_CPU, 0, &dev); 392 if (err) 393 return 0; 394 395 err = cpu_get_info(dev, &cpu); 396 if (err) 397 return 0; 398 399 err = cpu_get_desc(dev, desc, sizeof(desc)); 400 if (err) 401 return 0; 402 403 printf("Chip ID: %s, MIPS: ", desc); 404 print_freq(cpu.cpu_freq, "\n"); 405 406 return 0; 407 } 408 #endif 409