1 /* 2 * Copyright (C) 2016 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm/device.h> 11 #include <linux/bitops.h> 12 #include <linux/io.h> 13 #include <linux/sizes.h> 14 15 #include "clk-uniphier.h" 16 17 /** 18 * struct uniphier_clk_priv - private data for UniPhier clock driver 19 * 20 * @base: base address of the clock provider 21 * @data: SoC specific data 22 */ 23 struct uniphier_clk_priv { 24 void __iomem *base; 25 const struct uniphier_clk_data *data; 26 }; 27 28 static int uniphier_clk_enable(struct clk *clk) 29 { 30 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); 31 unsigned long id = clk->id; 32 const struct uniphier_clk_gate_data *p; 33 34 for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) { 35 u32 val; 36 37 if (p->id != id) 38 continue; 39 40 val = readl(priv->base + p->reg); 41 val |= BIT(p->bit); 42 writel(val, priv->base + p->reg); 43 44 return 0; 45 } 46 47 dev_err(priv->dev, "clk_id=%lu was not handled\n", id); 48 return -EINVAL; 49 } 50 51 static const struct uniphier_clk_mux_data * 52 uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id) 53 { 54 const struct uniphier_clk_mux_data *p; 55 56 for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) { 57 if (p->id == id) 58 return p; 59 } 60 61 return NULL; 62 } 63 64 static ulong uniphier_clk_get_rate(struct clk *clk) 65 { 66 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); 67 const struct uniphier_clk_mux_data *mux; 68 u32 val; 69 int i; 70 71 mux = uniphier_clk_get_mux_data(priv, clk->id); 72 if (!mux) 73 return 0; 74 75 if (!mux->nr_muxs) /* fixed-rate */ 76 return mux->rates[0]; 77 78 val = readl(priv->base + mux->reg); 79 80 for (i = 0; i < mux->nr_muxs; i++) 81 if ((mux->masks[i] & val) == mux->vals[i]) 82 return mux->rates[i]; 83 84 return -EINVAL; 85 } 86 87 static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate) 88 { 89 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); 90 const struct uniphier_clk_mux_data *mux; 91 u32 val; 92 int i, best_rate_id = -1; 93 ulong best_rate = 0; 94 95 mux = uniphier_clk_get_mux_data(priv, clk->id); 96 if (!mux) 97 return 0; 98 99 if (!mux->nr_muxs) /* fixed-rate */ 100 return mux->rates[0]; 101 102 /* first, decide the best match rate */ 103 for (i = 0; i < mux->nr_muxs; i++) { 104 if (mux->rates[i] > best_rate && mux->rates[i] <= rate) { 105 best_rate = mux->rates[i]; 106 best_rate_id = i; 107 } 108 } 109 110 if (best_rate_id < 0) 111 return -EINVAL; 112 113 val = readl(priv->base + mux->reg); 114 val &= ~mux->masks[best_rate_id]; 115 val |= mux->vals[best_rate_id]; 116 writel(val, priv->base + mux->reg); 117 118 debug("%s: requested rate = %lu, set rate = %lu\n", __func__, 119 rate, best_rate); 120 121 return best_rate; 122 } 123 124 const struct clk_ops uniphier_clk_ops = { 125 .enable = uniphier_clk_enable, 126 .get_rate = uniphier_clk_get_rate, 127 .set_rate = uniphier_clk_set_rate, 128 }; 129 130 static int uniphier_clk_probe(struct udevice *dev) 131 { 132 struct uniphier_clk_priv *priv = dev_get_priv(dev); 133 fdt_addr_t addr; 134 135 addr = dev_get_addr(dev->parent); 136 if (addr == FDT_ADDR_T_NONE) 137 return -EINVAL; 138 139 priv->base = devm_ioremap(dev, addr, SZ_4K); 140 if (!priv->base) 141 return -ENOMEM; 142 143 priv->data = (void *)dev_get_driver_data(dev); 144 145 return 0; 146 } 147 148 static const struct udevice_id uniphier_clk_match[] = { 149 { 150 .compatible = "socionext,uniphier-sld3-mio-clock", 151 .data = (ulong)&uniphier_mio_clk_data, 152 }, 153 { 154 .compatible = "socionext,uniphier-ld4-mio-clock", 155 .data = (ulong)&uniphier_mio_clk_data, 156 }, 157 { 158 .compatible = "socionext,uniphier-pro4-mio-clock", 159 .data = (ulong)&uniphier_mio_clk_data, 160 }, 161 { 162 .compatible = "socionext,uniphier-sld8-mio-clock", 163 .data = (ulong)&uniphier_mio_clk_data, 164 }, 165 { 166 .compatible = "socionext,uniphier-pro5-sd-clock", 167 .data = (ulong)&uniphier_mio_clk_data, 168 }, 169 { 170 .compatible = "socionext,uniphier-pxs2-sd-clock", 171 .data = (ulong)&uniphier_mio_clk_data, 172 }, 173 { 174 .compatible = "socionext,uniphier-ld11-mio-clock", 175 .data = (ulong)&uniphier_mio_clk_data, 176 }, 177 { 178 .compatible = "socionext,uniphier-ld20-sd-clock", 179 .data = (ulong)&uniphier_mio_clk_data, 180 }, 181 { /* sentinel */ } 182 }; 183 184 U_BOOT_DRIVER(uniphier_clk) = { 185 .name = "uniphier-clk", 186 .id = UCLASS_CLK, 187 .of_match = uniphier_clk_match, 188 .probe = uniphier_clk_probe, 189 .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv), 190 .ops = &uniphier_clk_ops, 191 }; 192