xref: /openbmc/u-boot/drivers/clk/sunxi/clk_v3s.c (revision 90571a4a)
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (C) 2018 Amarula Solutions.
4  * Author: Jagan Teki <jagan@amarulasolutions.com>
5  */
6 
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <asm/arch/ccu.h>
12 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
13 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
14 
15 static struct ccu_clk_gate v3s_gates[] = {
16 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
17 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
18 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
19 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
20 
21 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
22 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
23 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
24 
25 	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
26 };
27 
28 static struct ccu_reset v3s_resets[] = {
29 	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
30 
31 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
32 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
33 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
34 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
35 
36 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
37 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
38 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
39 };
40 
41 static const struct ccu_desc v3s_ccu_desc = {
42 	.gates = v3s_gates,
43 	.resets = v3s_resets,
44 };
45 
46 static int v3s_clk_bind(struct udevice *dev)
47 {
48 	return sunxi_reset_bind(dev, ARRAY_SIZE(v3s_resets));
49 }
50 
51 static const struct udevice_id v3s_clk_ids[] = {
52 	{ .compatible = "allwinner,sun8i-v3s-ccu",
53 	  .data = (ulong)&v3s_ccu_desc },
54 	{ }
55 };
56 
57 U_BOOT_DRIVER(clk_sun8i_v3s) = {
58 	.name		= "sun8i_v3s_ccu",
59 	.id		= UCLASS_CLK,
60 	.of_match	= v3s_clk_ids,
61 	.priv_auto_alloc_size	= sizeof(struct ccu_priv),
62 	.ops		= &sunxi_clk_ops,
63 	.probe		= sunxi_clk_probe,
64 	.bind		= v3s_clk_bind,
65 };
66