1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (C) 2018 Amarula Solutions. 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <asm/arch/ccu.h> 12 #include <dt-bindings/clock/sun8i-r40-ccu.h> 13 #include <dt-bindings/reset/sun8i-r40-ccu.h> 14 15 static struct ccu_clk_gate r40_gates[] = { 16 [CLK_BUS_OTG] = GATE(0x060, BIT(25)), 17 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), 18 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), 19 [CLK_BUS_EHCI2] = GATE(0x060, BIT(28)), 20 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)), 21 [CLK_BUS_OHCI1] = GATE(0x060, BIT(30)), 22 [CLK_BUS_OHCI2] = GATE(0x060, BIT(31)), 23 24 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), 25 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), 26 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), 27 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), 28 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), 29 [CLK_BUS_UART5] = GATE(0x06c, BIT(21)), 30 [CLK_BUS_UART6] = GATE(0x06c, BIT(22)), 31 [CLK_BUS_UART7] = GATE(0x06c, BIT(23)), 32 33 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), 34 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), 35 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)), 36 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)), 37 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), 38 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)), 39 }; 40 41 static struct ccu_reset r40_resets[] = { 42 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), 43 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), 44 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), 45 46 [RST_BUS_OTG] = RESET(0x2c0, BIT(25)), 47 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), 48 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), 49 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(28)), 50 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)), 51 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)), 52 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)), 53 54 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), 55 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), 56 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), 57 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)), 58 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)), 59 [RST_BUS_UART5] = RESET(0x2d8, BIT(21)), 60 [RST_BUS_UART6] = RESET(0x2d8, BIT(22)), 61 [RST_BUS_UART7] = RESET(0x2d8, BIT(23)), 62 }; 63 64 static const struct ccu_desc r40_ccu_desc = { 65 .gates = r40_gates, 66 .resets = r40_resets, 67 }; 68 69 static int r40_clk_bind(struct udevice *dev) 70 { 71 return sunxi_reset_bind(dev, ARRAY_SIZE(r40_resets)); 72 } 73 74 static const struct udevice_id r40_clk_ids[] = { 75 { .compatible = "allwinner,sun8i-r40-ccu", 76 .data = (ulong)&r40_ccu_desc }, 77 { } 78 }; 79 80 U_BOOT_DRIVER(clk_sun8i_r40) = { 81 .name = "sun8i_r40_ccu", 82 .id = UCLASS_CLK, 83 .of_match = r40_clk_ids, 84 .priv_auto_alloc_size = sizeof(struct ccu_priv), 85 .ops = &sunxi_clk_ops, 86 .probe = sunxi_clk_probe, 87 .bind = r40_clk_bind, 88 }; 89