xref: /openbmc/u-boot/drivers/clk/sunxi/clk_h3.c (revision 04b24965)
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (C) 2018 Amarula Solutions.
4  * Author: Jagan Teki <jagan@amarulasolutions.com>
5  */
6 
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <asm/arch/ccu.h>
12 #include <dt-bindings/clock/sun8i-h3-ccu.h>
13 #include <dt-bindings/reset/sun8i-h3-ccu.h>
14 
15 static struct ccu_clk_gate h3_gates[] = {
16 	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
17 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
18 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
19 	[CLK_BUS_EHCI2]		= GATE(0x060, BIT(26)),
20 	[CLK_BUS_EHCI3]		= GATE(0x060, BIT(27)),
21 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
22 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
23 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
24 	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
25 
26 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
27 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
28 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
29 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
30 
31 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
32 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
33 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
34 	[CLK_USB_PHY3]		= GATE(0x0cc, BIT(11)),
35 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
36 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
37 	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
38 	[CLK_USB_OHCI3]		= GATE(0x0cc, BIT(19)),
39 };
40 
41 static struct ccu_reset h3_resets[] = {
42 	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
43 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
44 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
45 	[RST_USB_PHY3]		= RESET(0x0cc, BIT(3)),
46 
47 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(23)),
48 	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(24)),
49 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(25)),
50 	[RST_BUS_EHCI2]		= RESET(0x2c0, BIT(26)),
51 	[RST_BUS_EHCI3]		= RESET(0x2c0, BIT(27)),
52 	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(28)),
53 	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(29)),
54 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(30)),
55 	[RST_BUS_OHCI3]		= RESET(0x2c0, BIT(31)),
56 
57 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
58 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
59 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
60 	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
61 };
62 
63 static const struct ccu_desc h3_ccu_desc = {
64 	.gates = h3_gates,
65 	.resets = h3_resets,
66 };
67 
68 static int h3_clk_bind(struct udevice *dev)
69 {
70 	return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
71 }
72 
73 static const struct udevice_id h3_ccu_ids[] = {
74 	{ .compatible = "allwinner,sun8i-h3-ccu",
75 	  .data = (ulong)&h3_ccu_desc },
76 	{ .compatible = "allwinner,sun50i-h5-ccu",
77 	  .data = (ulong)&h3_ccu_desc },
78 	{ }
79 };
80 
81 U_BOOT_DRIVER(clk_sun8i_h3) = {
82 	.name		= "sun8i_h3_ccu",
83 	.id		= UCLASS_CLK,
84 	.of_match	= h3_ccu_ids,
85 	.priv_auto_alloc_size	= sizeof(struct ccu_priv),
86 	.ops		= &sunxi_clk_ops,
87 	.probe		= sunxi_clk_probe,
88 	.bind		= h3_clk_bind,
89 };
90