1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (C) 2018 Amarula Solutions. 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <asm/arch/ccu.h> 12 #include <dt-bindings/clock/sun4i-a10-ccu.h> 13 #include <dt-bindings/reset/sun4i-a10-ccu.h> 14 15 static struct ccu_clk_gate a10_gates[] = { 16 [CLK_AHB_OTG] = GATE(0x060, BIT(0)), 17 [CLK_AHB_EHCI0] = GATE(0x060, BIT(1)), 18 [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)), 19 [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)), 20 [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)), 21 22 [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), 23 [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), 24 [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), 25 [CLK_APB1_UART3] = GATE(0x06c, BIT(19)), 26 [CLK_APB1_UART4] = GATE(0x06c, BIT(20)), 27 [CLK_APB1_UART5] = GATE(0x06c, BIT(21)), 28 [CLK_APB1_UART6] = GATE(0x06c, BIT(22)), 29 [CLK_APB1_UART7] = GATE(0x06c, BIT(23)), 30 31 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(6)), 32 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(7)), 33 [CLK_USB_PHY] = GATE(0x0cc, BIT(8)), 34 }; 35 36 static struct ccu_reset a10_resets[] = { 37 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), 38 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), 39 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), 40 }; 41 42 static const struct ccu_desc a10_ccu_desc = { 43 .gates = a10_gates, 44 .resets = a10_resets, 45 }; 46 47 static int a10_clk_bind(struct udevice *dev) 48 { 49 return sunxi_reset_bind(dev, ARRAY_SIZE(a10_resets)); 50 } 51 52 static const struct udevice_id a10_ccu_ids[] = { 53 { .compatible = "allwinner,sun4i-a10-ccu", 54 .data = (ulong)&a10_ccu_desc }, 55 { .compatible = "allwinner,sun7i-a20-ccu", 56 .data = (ulong)&a10_ccu_desc }, 57 { } 58 }; 59 60 U_BOOT_DRIVER(clk_sun4i_a10) = { 61 .name = "sun4i_a10_ccu", 62 .id = UCLASS_CLK, 63 .of_match = a10_ccu_ids, 64 .priv_auto_alloc_size = sizeof(struct ccu_priv), 65 .ops = &sunxi_clk_ops, 66 .probe = sunxi_clk_probe, 67 .bind = a10_clk_bind, 68 }; 69