1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Copyright (C) 2018 SiFive, Inc. 6 * Wesley Terpstra 7 * Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H 20 #define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H 21 22 #include <linux/types.h> 23 24 /* DIVQ_VALUES: number of valid DIVQ values */ 25 #define DIVQ_VALUES 6 26 27 /* 28 * Bit definitions for struct analogbits_wrpll_cfg.flags 29 * 30 * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be 31 * programmed to enter bypass 32 * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset 33 * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal 34 * feedback mode 35 * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external 36 * feedback mode (not yet supported by this driver) 37 * 38 * The flags WRPLL_FLAGS_INT_FEEDBACK_FLAG and WRPLL_FLAGS_EXT_FEEDBACK_FLAG are 39 * mutually exclusive. If both bits are set, or both are zero, the struct 40 * analogbits_wrpll_cfg record is uninitialized or corrupt. 41 */ 42 #define WRPLL_FLAGS_BYPASS_SHIFT 0 43 #define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT) 44 #define WRPLL_FLAGS_RESET_SHIFT 1 45 #define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT) 46 #define WRPLL_FLAGS_INT_FEEDBACK_SHIFT 2 47 #define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT) 48 #define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT 3 49 #define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT) 50 51 /** 52 * struct analogbits_wrpll_cfg - WRPLL configuration values 53 * @divr: reference divider value (6 bits), as presented to the PLL signals. 54 * @divf: feedback divider value (9 bits), as presented to the PLL signals. 55 * @divq: output divider value (3 bits), as presented to the PLL signals. 56 * @flags: PLL configuration flags. See above for more information. 57 * @range: PLL loop filter range. See below for more information. 58 * @_output_rate_cache: cached output rates, swept across DIVQ. 59 * @_parent_rate: PLL refclk rate for which values are valid 60 * @_max_r: maximum possible R divider value, given @parent_rate 61 * @_init_r: initial R divider value to start the search from 62 * 63 * @divr, @divq, @divq, @range represent what the PLL expects to see 64 * on its input signals. Thus @divr and @divf are the actual divisors 65 * minus one. @divq is a power-of-two divider; for example, 1 = 66 * divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value. 67 * 68 * When initially passing a struct analogbits_wrpll_cfg record, the 69 * record should be zero-initialized with the exception of the @flags 70 * field. The only flag bits that need to be set are either 71 * WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK. 72 * 73 * Field names beginning with an underscore should be considered 74 * private to the wrpll-cln28hpc.c code. 75 */ 76 struct analogbits_wrpll_cfg { 77 u8 divr; 78 u8 divq; 79 u8 range; 80 u8 flags; 81 u16 divf; 82 u32 _output_rate_cache[DIVQ_VALUES]; 83 unsigned long _parent_rate; 84 u8 _max_r; 85 u8 _init_r; 86 }; 87 88 /* 89 * Function prototypes 90 */ 91 92 int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c, 93 u32 target_rate, 94 unsigned long parent_rate); 95 96 unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c); 97 98 unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c, 99 unsigned long parent_rate); 100 101 #endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */ 102